ADS5242IPAP

          ADS5242 SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • • • • • • • • • • • • • • Maximum Sample Rate: 65MSPS 12-Bit Resolution No Missing Codes Total Power Dissipation Internal Reference: 660mW External Reference: 594mW CMOS Technology Simultaneous Sample-and-Hold 70.8dBFS SNR at 10MHz IF 3.3V Digital/Analog Supply Serialized LVDS Outputs Integrated Frame and Bit Patterns Option to Double LVDS Clock Output Currents Four Current Modes for LVDS Pin- and Format-Compatible Family HTQFP-64 PowerPAD™ Package An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock. The ADS5242 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The device is available in an HTQFP-64 PowerPAD package and is specified over a –40°C to +85°C operating range. LCLK P 6x ADCLK LCLK N 12x ADCLK APPLICATIONS PLL ADCLK P 1x ADCLK Portable Ultrasound Systems Tape Drives Test Equipment Optical Networking Communications ADCLK ADCLK N RELATED PRODUCTS IN3 P IN3 N IN4 P IN4 N S/H S/H MODEL SAMPLE RATE (MSPS) CHANNELS ADS5240 12 40 4 12−Bit ADC Serializer 12−Bit ADC Serializer OUT2 P OUT2 N OUT3 P OUT3 N OUT4 P OUT4 N Registers Reference INT/EXT RESOLUTION (BITS) Serializer Control PD The ADS5242 is a high-performance, 65MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. 12−Bit ADC OUT1 P OUT1 N RESET DESCRIPTION S/H Serializer SDATA IN2 P IN2 N 12−Bit ADC CS S/H SCLK IN1 P IN1 N REFT VC M REFB • • • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD (2) PACKAGE DESIGNATOR ADS5242 HTQFP-64 PAP (1) (2) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +85°C ADS5242IPAP ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5242IPAP Tray, 160 ADS5242IPAPT Tape and Reel, 250 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. Thermal pad size: 5.29mm × 5.29mm (min), 6.50mm × 6.50mm (max). ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage Range, AVDD –0.3V to +3.8V Supply Voltage Range, LVDD –0.3V to +3.8V Voltage Between AVSS and LVSS –0.3V to +0.3V Voltage Between AVDD and LVDD –0.3V to +0.3V Voltage Applied to External REF Pins –0.3V to +2.4V All LVDS Data and Clock Outputs Analog Input Pins (2) Operating Free-Air Temperature Range, TA Lead Temperature, 1.6mm (1/16" from case for 10s) Junction Temperature Storage Temperature Range (1) (2) 2 –0.3V to +2.4V –0.3V to min. [3.3V, (AVDD + 0.3V)] –40°C to +85°C +260°C +105°C –65°C to +150°C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. The DC voltage applied on the input pins should not go below –0.3V. Also, the DC voltage should be limited to the lower of either 3.3V or (AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and +3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed 1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V. ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 RECOMMENDED OPERATING CONDITIONS ADS5242 PARAMETER MIN TYP MAX UNITS 3.0 3.3 3.6 V SUPPLIES AND REFERENCES Analog Supply Voltage, AVDD Output Driver Supply Voltage, LVDD 3.0 3.3 3.6 V REFT — External Reference Mode 1.825 1.95 2 V REFB — External Reference Mode 0.9 0.95 1.075 V REFCM = (REFT + REFB)/2 – External Reference VCM ± 50mV Mode (1) Reference = (REFT – REFB) – External Reference Mode 0.75 1.0 V 1.1 VCM ± 50mV Analog Input Common-Mode Range (1) V V CLOCK INPUT AND OUTPUTS ADCLK Input Sample Rate (low-voltage TTL) 20 65 MSPS ADCLK Duty Cycle 45 55 % 0.6 V Low-Level Voltage Clock Input High-Level Voltage Clock Input 2.2 ADCLKP and ADCLKN Outputs (LVDS) 20 65 MHz V LCLKP and LCLKN Outputs (LVDS) (2) 120 390 MHz Operating Free-Air Temperature, TA –40 +85 °C Thermal Characteristics: (1) (2) θJA 20.4 °C/W θJC 14.5 °C/W These voltages need to be set to 1.45V ± 50mV if they are derived independent of VCM. 6 × ADCLK. 3 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 ELECTRICAL CHARACTERISTICS TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. All values are applicable after the device has been reset. ADS5242 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LSB DC ACCURACY No Missing Codes Tested DNL Differential Nonlinearity INL Integral Nonlinearity fIN = 5MHz –0.95 ±0.31 +1.0 fIN = 5MHz –2.5 ±0.41 +2.5 LSB +0.75 %FS Offset Error (1) –0.75 ±6 Offset Temperature Coefficient Fixed Attenuation in Channel (2) 1.5 Fixed Attenuation Matching Across Channels Gain Error/Reference Error (3) ppm/°C VREFT – VREFB –2.5 %FS ±0.01 0.2 dB ±1.0 +2.5 %FS ±20 Gain Error Temperature Coefficient ppm/°C POWER REQUIREMENTS (4) Internal Reference Power Dissipation Analog Only (AVDD) 500 545 mW Output Driver (LVDD) 160 191 mW 660 736 mW Total Power Dissipation External Reference Power Dissipation Analog Only (AVDD) 434 mW Output Driver (LVDD) 160 mW 594 mW Total Power Dissipation Total Power-Down Clock Running 92 149 mW REFERENCE VOLTAGES VREFT Reference Top (internal) 1.9 1.95 2.0 V VREFB Reference Bottom (internal) 0.9 0.95 1.0 V VCM Common-Mode Voltage 1.4 1.45 1.5 VCM Output Current (5) VREFT Reference Top (external) VREFB Reference Bottom (external) (1) (2) (3) (4) (5) (6) 4 ±50mV Change in Voltage ±2.0 1.825 0.9 V mA 1.95 2.0 V 0.95 1.075 V External Reference Common-Mode VCM ± 50mV V External Reference Input Current (6) 0.5 mA Offset error is the deviation of the average code with a –1dBFS coherent sinusoid input from mid-code (2048). Fixed attenuation in the channel arises due to a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at the analog input pins are changed from –VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (VREFT – VREFB). The reference voltages are trimmed at production so that (VREFT – VREFB) is within ± 25mV of the ideal value of 1V. This specification does not include fixed attenuation. Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V. VCM provides the common-mode current for the inputs of all four channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of the VCM buffer if loaded externally. Average current drawn from the reference pins in the external reference mode. ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 ELECTRICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. All values are applicable after the device has been reset. ADS5242 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Differential Input Capacitance 4.0 pF VCM ± 50 mV Internal Reference 2.03 VPP External Reference 2.03 × (VREFT – VREFB) VPP 3.0 CLK Cycles 300 MHz Analog Input Common-Mode Range Differential Input Voltage Range Voltage Overload Recovery Time (7) Input Bandwidth –3dBFS, 25Ω Series Resistances DIGITAL DATA INPUTS VIH High-Level Input Voltage 2.2 V VIL Low-Level Input Voltage 0.6 CIN Input Capacitance 3.0 V pF DIGITAL DATA OUTPUTS Data Format Straight Offset Binary Data Bit Rate 240 780 Mbps 20 MHz SERIAL INTERFACE SCLK Serial Clock Input Frequency (7) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value when the pulse is switched from ON (high) to OFF (low). REFERENCE SELECTION MODE INT/EXT DESCRIPTION Internal Reference; FSR = 2.03VPP 1 Default with internal pull-up. External Reference; FSR = 2.03 × (VREFT – VREFB) 0 Internal reference is powered down. The common-mode voltage of the external reference should be within 50mV of VCM. VCM is derived from the internal bandgap voltage. 5 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 AC CHARACTERISTICS TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5242 PARAMETER CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS fIN = 1MHz SFDR Spurious-Free Dynamic Range HD2 2nd-Order Harmonic Distortion HD3 3rd-Order Harmonic Distortion SNR Signal-to-Noise Ratio SINAD Signal-to-Noise and Distortion ENOB Effective Number of Bits Crosstalk IMD3 6 Two-Tone, Third-Order Intermodulation Distortion 88 dBc 85 dBc fIN = 10MHz 85 dBc fIN = 20MHz 85 dBc fIN = 1MHz 98 dBc 95 dBc fIN = 10MHz 95 dBc fIN = 20MHz 92 dBc fIN = 1MHz 88 dBc 85 dBc fIN = 10MHz 85 dBc fIN = 20MHz 85 dBc fIN = 1MHz 71.1 dBFS fIN = 5MHz fIN = 5MHz fIN = 5MHz fIN = 5MHz 77 84 77 71 dBFS fIN = 10MHz 70.8 dBFS fIN = 20MHz 70.1 dBFS fIN = 1MHz 70.9 dBFS 70.8 dBFS fIN = 10MHz 70.6 dBFS fIN = 20MHz 69.9 dBFS 11.5 Bits –88 dBc 95 dBFS fIN = 5MHz fIN = 5MHz 5MHz Full-Scale Signal Applied to 3 Channels; Measurement Taken on the Channel with No Input Signal f1 = 9.5MHz at –7dBFS f2 = 10.2MHz at –7dBFS 69 68.5 11.1 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 LVDS DIGITAL DATA AND CLOCK OUTPUTS Test conditions at IO = 3.5mA, RLOAD = 100Ω, CLOAD = 6pF, and 50% duty cycle. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between each of the LVDS pins and ground. CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch transmission line of 100Ω characteristic impedance between the device and the load. All LVDS specifications are characterized, but not parametrically tested at production. LCLKOUT refers to (LCLKP – LCLKN); ADCLKOUT refers to (ADCLKP – ADCLKN); DATA OUT refers to (OUTP – OUTN); and ADCLK refers to the input sampling clock. PARAMETER CONDITIONS MIN TYP MAX UNITS VOH Output Voltage High, OUTP or OUTN RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8 1265 1365 1465 mV VOL Output Voltage Low, OUTP or OUTN RLOAD = 100Ω ± 1% 940 1040 1140 mV |VOD| Output Differential Voltage RLOAD = 100Ω ± 1% 275 325 375 mV VOS Output Offset Voltage (2) RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8 1.1 1.2 1.3 DC SPECIFICATIONS (1) V RO Output Impedance, Differential Normal Operation 13 kΩ RO Output Impedance, Differential Power-Down 20 kΩ CO Output Capacitance (3) 4 pF RLOAD = 100Ω ± 1% 10 mV ∆VOS Change Between 0 and 1 RLOAD = 100Ω ± 1% 25 mV ISOUT Output Short-Circuit Current Drivers Shorted to Ground 40 mA Drivers Shorted Together 12 mA % |∆VOD| Change in |VOD| Between 0 and 1 ISOUTNP Output Current DRIVER AC SPECIFICATIONS ADCLKOUT Clock Duty Cycle (4) 45 50 55 LCLKOUT Duty Cycle (4) 40 50 60 Data Setup Time (5) (6) 0.4 Data Hold Time (7) (6) % ns 0.25 LVDS Outputs Rise/Fall Time (8) ns IO = 2.5mA 400 IO = 3.5mA 180 300 IO = 4.5mA 230 IO = 6.0mA 180 ps 500 ps ps ps LCLKOUT Rising Edge to ADCLKOUT Rising Edge (9) 0.37 0.64 0.9 ns ADCLKOUT Rising Edge to LCLKOUT Falling Edge (9) 0.37 0.64 0.9 ns ADCLKOUT Rising Edge to DATA OUT Transition (9) –0.3 0 +0.3 ns (1) (2) (3) (4) (5) (6) (7) (8) (9) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1. VOS refers to the common-mode of OUTP and OUTN. Output capacitance inside the device, from either OUTP or OUTN to ground. Measured between zero crossings. DATA OUT (OUTP – OUTN) crossing zero to LCLKOUT (LCLKP – LCLKN) crossing zero. Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, as well as effects of clock jitter within the device. LCLKOUT crossing zero to DATA OUT crossing zero. Measured from –100mV to +100mV on the differential output for rise time, and +100mV to –100mV for fall time. Measured between zero crossings. SWITCHING CHARACTERISTICS TMIN = –40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 50 ns 4 6.5 ns SWITCHING SPECIFICATIONS tSAMPLE tD(A) Aperture Delay (1) 15.4 2 Aperture Jitter (uncertainty) tD(pipeline) Latency tPROP Propagation Delay (2) (1) (2) 3 1 ps 6.5 Cycles 4.8 6.5 ns Rising edge of ADCLK to actual instant when data is sampled within the ADC. Falling edge of ADCLK to zero-crossing of rising edge of ADCLKOUT. 7 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 LVDS TIMING DIAGRAM (PER ADC CHANNEL) Sample n Sample n + 6 Input 1 t SAMPLE ADCLK tS 2 LCLKP 6X ADCLK LCLK N OUTP SERIAL DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 OUTN Sample n data ADCLKP 1X ADCLK ADCLKN tD(A) tPROP 6.5 Clock Cycles NOTE: Serial data bit format shown in LSB first mode. RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING AVDD (3V to 3.6V) t1 AVDD LVDD (3V to 3.6V) t2 LVDD t3 t4 t7 t5 Device Ready For ADC Operation t6 RESET Device Ready For Serial Register Write CS Device Ready For ADC Operation Start of Clock ADCLK t8 NOTE: 10µs < t1 < 50ms; 10µs < t2 < 50ms; −10ms < t3 < 10ms; t4 > 10ms; t 5 > 100ns; t6 > 100ns; t 7 > 10ms; and t8 > 100µs. 8 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 POWER-DOWN TIMING 1µs 500µs PD Device Fully Powers Down Device Fully Powers Up NOTE: The shown power−up time is based on 1µF bypass capacitors on the reference pins. See the Theory of Operation section for details. SERIAL INTERFACE TIMING Outputs change on next rising clock edge after CS goes high. ADCLK CS Start Sequence t6 t1 t7 Data latched on each rising edge of SCLK. t2 SCLK t3 D7 (MSB) SDATA D6 D5 D4 D3 D2 D1 D0 t4 t5 NOTE: Data is shifted in MSB first. PARAMETER DESCRIPTION MIN t1 Serial CLK Period 50 TYP MAX UNIT ns t2 Serial CLK High Time 20 ns t3 Serial CLK Low Time 20 ns t4 Minimum Data Setup Time 5 ns t5 Minimum Data Hold Time 5 ns t6 CS Fall to SCLK Rise 8 ns t7 SCLK Rise to CS Rise 8 ns 9 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 SERIAL INTERFACE REGISTERS ADDRESS DATA D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 DESCRIPTION D1 D3 D2 D0 LVDS BUFFERS (Register 0) All Data Outputs 0 0 Normal ADC Output (default after reset) 0 1 Deskew Pattern 1 0 Sync Pattern 1 1 Custom Pattern 0 Output Current in LVDS = 3.5mA 0 1 Output Current in LVDS = 2.5mA 1 0 Output Current in LVDS = 4.5mA 1 1 Output Current in LVDS = 6.0mA CLOCK CURRENT (Register 1) X X 0 Default LVDS Clock Output Current IOUT = 3.5mA (default) 0 X X 1 2X LVDS Clock Output Current (1) IOUT = 7.0mA LSB/MSB MODE (Register 1) 0 0 X X LSB First Mode 0 1 X X MSB First Mode 0 1 (default after reset) 0 1 1 See Test Patterns 0 1 0 REMARKS (default after reset) POWER-DOWN ADC CHANNELS (Register 2) 0 1 0 X D2: Power-Down for Channel 2 0 X 0 1 D0: Power-Down for Channel 1 1 Logic 1 = Channel Powered Down POWER-DOWN ADC CHANNELS (Register 3) 1 0 X 0 D3: Power-Down for Channel 4 X 0 1 0 D1: Power-Down for Channel 3 D3 D2 D1 D0 Logic 1 = Channel Powered Down CUSTOM PATTERN (Registers 4–6) (1) 0 1 0 0 X X X X 0 1 0 1 X X X X 0 1 1 0 X X X X Bits for Custom Pattern See Test Patterns Output current drive for the two clock LVDS buffers (LCLKP and LCLKN and ADCLKP and ADCLKN) is double the output current setting programmed in register 0. The current drive of the data buffers remains the same as the setting in register 0. TEST PATTERNS (1) Serial Output (2) ADC Output (3) Deskew Pattern Sync Pattern Custom Pattern (4) (1) (2) (3) (4) 10 LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6) This table indicates the LSB and MSB of the various patterns. LSB first mode means that the LSB comes out as the first bit of the word. In the MSB first mode, the MSB comes out as the first bit of the word. The first bit of the word is the one that comes soon after the rising edge of ADCLKP (the falling edge of ACDLKN). The serial output stream comes out LSB first by default. D11...D0 represent the 12 output bits from the ADC. D0(4) represents the content of bit D0 of register 4, D3(6) represents the content of bit D3 of register 6, etc. ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 PIN CONFIGURATION SCLK SDA CS AVDD AVSS AVSS AVSS ADCLK AVDD INT/EXT REFT REFB VCM ISET AVSS HTQFP AVSS Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 48 AVDD IN1P 2 47 IN4N IN1N 3 46 IN4P AVSS 4 45 AVSS AVDD 5 44 AVDD AVSS 6 43 AVSS IN2P 7 42 IN3N IN2N 8 AVSS 41 IN3P ADS5242 9 40 AVSS AVDD 10 39 AVDD LVSS 11 38 LVSS 37 RESET PD 12 LVSS 13 36 LVSS LVSS 14 35 LVSS 24 25 26 27 28 29 30 31 32 LVDD LVSS OUT4P OUT4N NC NC 23 OUT3N 22 OUT3P 21 OUT2N 20 OUT2P 19 LVSS 18 LVDD 17 OUT1N 33 ADCLKP OUT1P LCLKN 16 NC 34 ADCLKN NC LCLKP 15 11 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 PIN DESCRIPTIONS 12 NAME PIN # I/O ADCLK 56 I DESCRIPTION Data Converter Clock Input ADCLKN 34 O Negative LVDS ADC Clock Output ADCLKP 33 O Positive LVDS ADC Clock Output AVDD 1, 5, 10, 39, 44, 48, 55, 60 I Analog Power Supply AVSS 4, 6, 9, 40, 43, 45, 49, 57-59, 64 I Analog Ground CS 61 I Chip Select; 0 = Select, 1 = No Select IN1N 3 I Channel 1 Differential Analog Input Low IN1P 2 I Channel 1 Differential Analog Input High IN2N 8 I Channel 2 Differential Analog Input Low IN2P 7 I Channel 2 Differential Analog Input High IN3N 42 I Channel 3 Differential Analog Input Low IN3P 41 I Channel 3 Differential Analog Input High IN4N 47 I Channel 4 Differential Analog Input Low IN4P 46 I Channel 4 Differential Analog Input High INT/EXT 54 I Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply. ISET 50 I/O Bias Current Setting Resistor of 56.2kΩ to Ground LCLKN 16 O Negative LVDS Clock LCLKP 15 O Positive LVDS Clock LVDD 21, 27 I LVDS Power Supply LVSS 11, 13, 14, 22, 28, 35, 36, 38 I LVDS Ground NC 17, 18, 31, 32 — No Connection OUT1N 20 O Channel 1 Negative LVDS Data Output OUT1P 19 O Channel 1 Positive LVDS Data Output OUT2N 24 O Channel 2 Negative LVDS Data Output OUT2P 23 O Channel 2 Positive LVDS Data Output OUT3N 26 O Channel 3 Negative LVDS Data Output OUT3P 25 O Channel 3 Positive LVDS Data Output OUT4N 30 O Channel 4 Negative LVDS Data Output OUT4P 29 O Channel 4 Positive LVDS Data Output PD 12 I Power-Down; 0 = Normal, 1 = Power-Down. Weak pull-down to ground. REFB 52 I/O Reference Bottom Voltage (2Ω resistor in series with a capacitor ≥ 0.1µF to ground) REFT 53 I/O Reference Top Voltage (2Ω resistor in series with a capacitor ≥ 0.1µF to ground) RESET 37 I Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground. SCLK 63 I Serial Data Clock SDA 62 I Serial Data Input VCM 51 O Common-Mode Output Voltage ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 DEFINITION OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. This is the minimum sampling rate where the ADC still works. Signal-to-Noise and Distortion (SINAD) Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Duty Cycle Pulse width high is the minimum amount of time that the ADCLK pulse should be left in logic ‘1’ state to achieve rated performance. Pulse width low is the minimum time that the ADCLK pulse should be left in a low state (logic ‘0’). At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. If a device claims to have no missing codes, it means that all possible codes (for a 12-bit converter, 4096 codes) are present over the full operating range. SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but not including DC. PS SINAD  10Log 10 PN
PD SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first eight harmonics. P SNR
10Log 10 S PN SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. Effective Number of Bits (ENOB) Spurious-Free Dynamic Range The ENOB is a measure of converter performance as compared to the theoretical limit based on quantization noise. ENOB  SINAD
1.76 6.02 The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Integral Nonlinearity (INL) INL is the deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line or best fit determined by a least square curve fit. INL is independent from effects of offset, gain or quantization errors. Maximum Conversion Rate The encode rate at which parametric testing is performed. This is the maximum sampling rate where certified operation is given. Two-Tone, Third-Order Intermodulation Distortion Two-tone IMD3 is the ratio of power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component of third-order intermodulation distortion at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. 13 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel, 16kFFT, and 8 averages, unless otherwise noted. SPECTRAL PERFORMANCE fIN = 1MHz SNR = 71.1dBFS SINAD = 70.9dBFS SFDR = 88dBc 16 Averages −20 Amplitude (dBFS) SPECTRAL PERFORMANCE −30 −40 −50 −60 −70 −80 0 −10 fIN = 5MHz SNR = 71dBFS SINAD = 70.8dBFS SFDR = 85dBc 16 Averages −20 Amplitude (dBFS) 0 −10 −30 −40 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 0 5 10 15 20 25 30 32.5 0 5 Figure 2. −50 −60 −70 −80 0 −10 30 32.5 f IN = 20MHz SNR = 70.1dBFS SINAD = 69.9dBFS SFDR = 85dBc 16 Averages −20 Amplitude (dBFS) −30 −40 25 SPECTRAL PERFORMANCE fIN = 10MHz SNR = 70.8dBFS SINAD = 70.6dBFS SFDR = 85dBc 16 Averages −20 −30 −40 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 0 5 10 15 20 25 30 32.5 0 5 10 15 20 25 Frequency (MHz) Frequency (MSPS) Figure 3. Figure 4. TWO-TONE INTERMODULATION DISTORTION 0 −10 −50 −60 −70 −80 −30 −40 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 fIN = 5MHz Crosstalk = 89dBFS 16 Averages −20 Amplitude (dBFS) −30 −40 30 32.5 CROSSTALK 0 −10 f1 = 9.5MHz f 2 = 10.2MHz IMD3 = 95dBFS −20 Amplitude (dBFS) 20 Figure 1. SPECTRAL PERFORMANCE −120 0 14 15 Frequency (MHz) 0 −10 Amplitude (dBFS) 10 Frequency (MHz) 5 10 15 20 25 30 32.5 0 5 10 15 20 Frequency (MHz) Frequency (MSPS) Figure 5. Figure 6. 25 30 32.5 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel, 16kFFT, and 8 averages, unless otherwise noted. DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY 0.6 0.75 fIN = 5MHz 0.50 0.2 0.25 INL (LSB) DNL (LSB) fIN = 5MHz 0.4 0 0 −0.2 −0.25 −0.4 −0.50 −0.6 −0.75 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 Code Figure 7. Signal−to−Noise Ratio (dBFS) External Reference VREFT = 1.95V VREFB = 0.95V 72 70 68 66 64 62 60 20 30 3584 4096 40 50 60 74 External Reference VREFT = 1.95V VREFB = 0.95V 72 70 68 66 64 62 60 70 0 10 20 Input Frequency (MHz) 30 40 50 60 70 Input Frequency (MHz) Figure 9. Figure 10. SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 95 85 External Reference VREFT = 1.95V VREFB = 0.95V 90 85 80 75 70 65 60 Internal Reference Signal−to−Noise Ratio (dBFS) Spurious−Free Dynamic Range (dBc) 3072 SINAD vs INPUT FREQUENCY Signal−to−Noise Ratio+Distortion (dBFS) SNR vs INPUT FREQUENCY 10 2560 Figure 8. 74 0 2048 Code 80 75 70 65 60 55 0 10 20 30 40 Input Frequency (MHz) Figure 11. 50 60 70 0 10 20 30 40 50 60 70 80 Input Frequency (MHz) Figure 12. 15 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel, 16kFFT, and 8 averages, unless otherwise noted. SFDR vs INPUT FREQUENCY Spurious−Free Dynamic Range (dBFS) Internal Reference 80 75 70 65 60 55 10 20 30 40 50 60 70 Internal Reference 90 85 80 75 70 20 30 SWEPT POWER — SNR SWEPT POWER — SINAD 40 30 20 10 fIN = 10MHz −40 −30 −20 −10 0 70 80 80 70 60 50 40 30 20 10 fIN = 10MHz 0 −60 −50 −40 −30 −20 −10 0 Amplitude (dBFS) Figure 15. Figure 16. SWEPT POWER — SFDR SWEPT POWER — SNR 80 120 f IN = 10MHz Signal−to−Noise Ratio (dBc, dBFS) Spurious−Free Dynamic Range (dBFS, dBc) 60 Figure 14. Amplitude (dBFS) 100 80 60 40 20 −60 −50 −40 −30 Amplitude (dBFS) Figure 17. 16 50 Figure 13. 50 0 −70 40 Input Frequency (MHz) 60 −50 10 Input Frequency (MHz) 70 0 −60 0 80 80 Signal−to−Noise Ratio (dBc, dBFS) 95 65 0 Signal−to−Noise Ratio+Distortion (dBc, dBFS) Signal−to−Noise Ratio+Distortion (dBFS) SINAD vs INPUT FREQUENCY 85 −20 −10 0 70 60 50 40 30 20 10 f IN = 5MHz 0 −60 −50 −40 −30 −20 Amplitude (dBFS) Figure 18. −10 0 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel, 16kFFT, and 8 averages, unless otherwise noted. SWEPT POWER — SFDR Spurious−Free Dynamic Range (dBc, dBFS) Signal−to−Noise Ratio+Distortion (dBc, dBFS) SWEPT POWER — SINAD 80 70 60 50 40 30 20 10 f IN = 5MHz 0 −60 −50 −40 −30 −20 −10 0 120 fIN = 5MHz 100 80 60 40 20 0 −60 −50 −40 Figure 19. Figure 20. SNR vs DUTY CYCLE Signal−to−Noise Ratio+Distortion (dBFS) Signal−to−Noise Ratio (dBFS) 72 71 70 69 68 67 40 45 50 55 0 60 65 74 fIN = 5MHz 73 72 71 70 69 68 67 70 30 35 40 45 50 55 Duty Cycle (%) Duty Cycle (%) Figure 21. Figure 22. SFDR vs DUTY CYCLE 60 65 70 SNR vs SAMPLE RATE 95 76 fIN = 5MHz fIN = 5MHz Signal−to−Noise Ratio (dBFS) Spurious−Free Dynamic Range (dBc) −10 SINAD vs DUTY CYCLE 73 35 −20 Amplitude (dBFS) 74 30 −30 Amplitude (dBFS) 90 85 80 75 74 72 70 68 66 64 70 30 35 40 45 50 55 Duty Cycle (%) Figure 23. 60 65 70 20 25 30 35 40 45 50 55 60 65 Sample Rate (MSPS) Figure 24. 17 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel, 16kFFT, and 8 averages, unless otherwise noted. SFDR vs SAMPLE RATE fIN = 5MHz 74 72 70 68 66 Spurious−Free Dynamic Range (dBFS) Signal−to−Noise Ratio+Distortion (dBFS) SINAD vs SAMPLE RATE 76 64 95 fIN = 5MHz 90 85 80 75 70 20 25 30 35 40 45 50 55 60 20 65 25 30 35 Figure 25. Signal−to−Noise Ratio (dBFS) fIN = 10MHz 74 72 70 68 66 64 30 35 40 45 60 65 50 55 60 fIN = 10MHz 74 72 70 68 66 64 65 20 25 30 35 40 45 50 55 60 65 60 65 Sample Rate (MSPS) Figure 27. Figure 28. SFDR vs SAMPLE RATE IAVDD, ILVDD vs SAMPLE RATE 98 160 fIN = 10MHz IAVDD 140 94 IAVDD, ILVDD (mA) Spurious−Free Dynamic Range (dBc) 55 76 Sample Rate (MSPS) 90 86 82 78 120 100 80 60 40 ILVDD 74 20 70 0 20 25 30 35 40 45 50 Sample Rate (MSPS) Figure 29. 18 50 SINAD vs SAMPLE RATE Signal−to−Noise Ratio+Distortion (dBFS) SNR vs SAMPLE RATE 25 45 Figure 26. 76 20 40 Sample Rate (MSPS) Sample Rate (MSPS) 55 60 65 20 25 30 35 40 45 50 Sample Rate (MHz) Figure 30. 55 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, LVDS buffer current at 3.5mA per channel, 16kFFT, and 8 averages, unless otherwise noted. TOTAL POWER vs TEMPERATURE 800 700 750 650 700 Power (mW) Total Power (mW) TOTAL POWER vs SAMPLE RATE 750 600 550 650 600 550 500 450 20 25 30 35 40 45 50 55 60 500 −40 65 −15 Figure 31. Figure 32. SNR vs TEMPERATURE Signal−to−Noise Ratio+Distortion (dBFS) Signal−to−Noise Ratio (dBFS) 72 71 70 69 +10 +35 Temperature (
C) Figure 33. +60 +85 +60 +85 SINAD vs TEMPERATURE 73 −15 +35 Temperature (
C) 74 68 −40 +10 Sample Rate (MSPS) +60 +85 74 73 72 71 70 69 68 −40 −15 +10 +35 Temperature (
C) Figure 34. 19 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 THEORY OF OPERATION OVERVIEW The ADS5242 is a 4-channel, high-speed, CMOS ADC. It consists of a high-performance sample-and-hold circuit at the input, followed by a 12-bit ADC. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All four channels of the ADS5242 operate from a single clock referred to as ADCLK. The sampling clocks for each of the four channels are generated from the input clock using a carefully matched clock buffer tree. The 12x clock required for the serializer is generated internally from ADCLK using a phase lock loop (PLL). A 6x and a 1x clock are also output in LVDS format along with the data to enable easy data capture. The ADS5242 operates from internally-generated reference voltages that are trimmed to ensure matching across multiple devices on a board. This feature eliminates the need for external routing of reference lines and also improves matching of the gain across devices. The nominal values of REFT and REFB are 1.95V and 0.95V, respectively. These values imply that a differential input of –1V corresponds to the zero code of the ADC, and a differential input of +1V corresponds to the full-scale code (4095 LSB). VCM (common-mode voltage of REFT and REFB) is also made available externally through a pin, and is nominally 1.45V. The ADC employs a pipelined converter architecture consisting of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The pipeline architecture results in a data latency of 6.5 clock cycles. The output of the ADC goes to a serializer that operates from a 12x clock generated by the PLL. The 12 data bits from each channel are serialized and sent LSB first. In addition to serializing the data, the serializer also generates a 1x clock and a 6x clock. These clocks are generated in the same way the serialized data is generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit 20 data externally has multiple advantages, such as a reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS5242. The ADS5242 operates from two sets of supplies and grounds. The analog supply/ground set is denoted as AVDD/AVSS, while the digital set is denoted by LVDD/LVSS. DRIVING THE ANALOG INPUTS The analog input biasing is shown in Figure 35. The inputs are biased internally using two 600Ω resistors to enable AC-coupling. A resistor greater than 20Ω is recommended in series with each input pin. A 4pF sampling capacitor is used to sample the inputs. The choice of the external AC-coupling capacitor is dictated by the attenuation at the lowest desired input frequency of operation. The attenuation resulting from using a 10nF AC-coupling capacitor is 0.04%. ADS5242 IN+ 600Ω Input Circuitry 600Ω IN− VCM CM Buffer Internal Voltage Reference NOTE: Dashed area denotes one of four channels. Figure 35. Analog Input Bias Circuitry If the input is DC-coupled, then the output common-mode voltage of the circuit driving the ADS5242 should match the VCM (which is provided as an output pin) to within ±50mV. It is recommended that the output common-mode of the driving circuit be derived from VCM provided by the device. ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 Figure 36 shows a detailed RLC model of the sample-and-hold circuit. The circuit operates in two phases. In the sample phase, the input is sampled on two capacitors that are nominally 4pF. The sampling circuit consists of a low-pass RC filter at the input to filter out noise components that might be differentially coupled on the input pins. The next phase is the hold phase wherein the voltage sampled on the capacitors is transferred (using the amplifier) to a subsequent pipeline ADC stage. INPUT OVER-VOLTAGE RECOVERY The differential full-scale range supported by the ADS5242 is nominally 2.03V. The ADS5242 is specially designed to handle an over-voltage condition where the differential peak-to-peak voltage can exceed up to twice the ADC full-scale range. If the input common-mode is not considerably off from VCM during overload (less than 300mV around the nominal value of 1.45V), recovery from an over-voltage pulse input of twice the amplitude of a full-scale pulse is expected to be within three clock cycles when the input switches from overload to zero signal. All of the amplifiers in the SHA and ADC are specially designed for excellent recovery from an overload signal. In most applications, the ADC inputs are driven with differential sinusoidal inputs. While the pulse-type signal remains at peak overload conditions throughout its HIGH state, the sinusoid signal only attains peak overload intermittently, at its minima and maxima. This condition is much less severe for the ADC input and the recovery of the ADC output (to 1% of full-scale around the expected code). This typically happens within the second clock when the input is driven with a sinusoid of amplitude equal to twice that of the ADC differential full-scale range. IN OUT 5nH to 9nH INP 1.5pF to 2.5pF 15Ω to 25Ω 1Ω 15Ω to 25Ω IN 3.2pF to 4.8pF 60Ω to 120Ω OUT IN OUT 500Ω to 720Ω OUT OUTP 1.5pF to 1.9pF IN OUTN 500Ω to 720Ω 15Ωto 35Ω 15Ω to 25Ω 15Ω to 25Ω IN OUT 3.2pF to 4.8pF 60Ω to 120Ω IN OUT 5nH to 9nH INN 1.5pF to 2.5pF Switches that are ON in SAMPLE phase. 1Ω Switches that are ON in HOLD phase. IN OUT Figure 36. Overall Structure of the Sample-and-Hold Circuit 21 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 REFERENCE CIRCUIT DESIGN The digital beam-forming algorithm relies on gain matching across all receiver channels. A typical system would have about 24 quad ADCs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the four channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures the reference voltages are well matched across different chips. All bias currents required for the internal operation of the device are set using an external resistor to ground at pin ISET. Using a 56.2kΩ resistor on ISET generates an internal reference current of 20µA. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external resistor at ISET reduces the reference bias current and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56.2kΩ so that the internal bias margins for the various blocks are proper. Buffering the internal bandgap voltage also generates a voltage called VCM, which is set to the midlevel of REFT and REFB, and is accessible on a pin. It is meant as a reference voltage to derive the input common-mode in case the input is directly coupled. It can also be used to derive the reference common-mode voltage in the external reference mode. When using the internal reference mode, a 2Ω resistor should be added between the reference pins (REFT and REFB) and the decoupling capacitor, as shown in Figure 37. If the device is used in the external reference mode, this 2Ω resistor is not required. ADS5242 ISET REFT REFB 2Ω 0.1µF 2.2µF 56.2kΩ 2Ω 2.2µF Table 1. State of Reference Voltages for Various Combinations of PD and INT/EXT PD 0 0 1 1 INT/EXT 0 1 0 1 REFT Tri-State 1.95V Tri-State Tri-State REFB Tri-State 0.95V Tri-State Tri-State VCM 1.45V 1.45V Tri-State(1) Tri-State(1) (1) Weak pull-down (approximately 5kΩ) to ground. CLOCKING The four channels on the chip operate from a single ADCLK input. To ensure that the aperture delay and jitter are same for all the channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point all the way to the sample-and-hold amplifier. This ensures that the performance and timing for all the channels are identical. The use of the clock tree for matching introduces an aperture delay, which is defined as the delay between the rising edge of ADCLK and the actual instant of sampling. The aperture delays for all the channels are matched to the best possible extent. However, a mismatch of ±20ps (±3σ) could exist between the aperture instants of the four ADCs within the same chip. However, the aperture delays of ADCs across two different chips can be several hundred picoseconds apart. Another critical specification is the aperture jitter that is defined as the uncertainty of the sampling instant. The gates in the clock path are designed to provide an rms jitter of approximately 1ps. 0.1µF Figure 37. Internal Reference Mode The device also supports the use of external reference voltages. This mode involves forcing REFT 22 and REFB externally. In this mode, the internal reference buffer is tri-stated. Since the switching current for the four ADCs come from the externally-forced references, it is possible for the performance to be slightly less than when the internal references are used. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally-forced reference voltages matches to within 50mV of VCM. The state of the reference voltages during various combinations of PD and INT/EXT is shown in Table 1. Ideally, the input ADCLK should have a 50% duty cycle. However, while routing ADCLK to different components onboard, the duty cycle of the ADCLK reaching the ADS5242 could deviate from 50%. A smaller (or larger) duty cycle reduces the time available for sample or hold phases of each circuit, and is therefore not optimal. For this reason, the internal PLL is used to generate an internal clock that has 50% duty cycle. The input sampling instant, ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 however, is determined by the rising edge of the external clock and is not affected by jitter in the PLL. In addition to generating a 50% duty cycle clock for the ADC, the PLL also generates a 12x clock that is used by the serializer to convert the parallel data from the ADC to a serial stream of bits. serializer is 780Mbps. The data comes out LSB first, with a register programmability that allows it to revert to MSB first. The serializer also transmits a 1x clock and a 6x clock. The 6x clock (denoted as LCLKP/LCLKN) is meant to synchronize the capture of the LVDS data. The use of the PLL automatically dictates the minimum sample rate to be about 20MSPS. The PLL also requires the input clock to be free-running. If the input clock is momentarily stopped (for a duration of less than 300ns) then the PLL would require approximately 10µs to lock back to the input clock frequency. Deskew mode can be enabled as well, using a register setting. This mode gives out a data stream of alternate 0s and 1s and can be used determine the relative delay between the 6x clock and the output data for optimum capture. A 1x clock is also generated by the serializer and transmitted through the LVDS buffer. The 1x clock (referred to as ADCLKP/ADCLKN) is used to determine the start of the 12-bit data frame. Sync mode (enabled through a register setting) gives out a data of six 0s followed by six 1s. Using this mode, the 1x clock can be used to determine the start of the data frame. In addition to the deskew mode pattern and the sync mode pattern, a custom pattern can be defined by the user and output from the LVDS buffer. The LVDS buffers are tri-stated in the power-down mode. The LVDS outputs are weakly forced to 1.2V through 10kΩ resistors (from each output pin to 1.2V). LVDS BUFFERS The LVDS buffer has two current sources, as shown in Figure 38. OUTP and OUTN are loaded externally by a resistive load that is ideally about 100Ω. Depending on whether the data is 0 or 1, the currents are directed in one direction or the other through the resistor. The LVDS buffer has four current settings. The default current setting is 3.5mA, and provides a differential drop of about ±350mV across the 100Ω resistor. The single-ended output impedance of the LVDS drivers is very high because they are current-source driven. If there are excessive reflections from the receiver, it might be necessary to place a 100Ω termination resistor across the outputs of the LVDS drivers to minimize the effect of reflections. In such a situation, the output current of the LVDS drivers can be increased to regain the output swing. High External Termination Resistor Low OUTP OUTN Low High Figure 38. LVDS Buffer The LVDS buffer receives data from a serializer that takes the output data from each channel and serializes it into a single data stream. For a clock frequency of 65MHz, the data rate output of the NOISE COUPLING ISSUES High-speed mixed signals are sensitive to various types of noise coupling. One of the main sources of noise is the switching noise from the serializer and the output buffers. Maximum care is taken to isolate these noise sources from the sensitive analog blocks. As a starting point, the analog and digital domains of the chip are clearly demarcated. AVDD and AVSS are used to denote the supplies for the analog sections, while LVDD and LVSS are used to denote the digital supplies. Care is taken to ensure that there is minimal interaction between the supply sets within the device. The extent of noise coupled and transmitted from the digital to the analog sections depends on the following: 1. The effective inductances of each of the supply/ground sets. 2. The isolation between the digital and analog supply/ground sets. Smaller effective inductance of the supply/ground pins leads to better suppression of the noise. For this reason, multiple pins are used to drive each supply/ground. It is also critical to ensure that the impedances of the supply and ground lines on board are kept to the minimum possible values. Use of ground planes in the board as well as large decoupling capacitors between the supply and ground lines are necessary to get the best possible SNR from the device. 23 ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 RESET It is recommended that the isolation be maintained on board by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. After the supplies have stabilized, it is necessary to give the device an active RESET pulse. This results in all internal registers resetting to their default value of 0 (inactive). Without a reset, it is possible that some registers may be in their non-default state on power-up. This may cause the device to malfunction. When a reset is active, the device outputs ‘0’ code on all channels. However, the LVDS output clocks are unaffected by reset. The use of LVDS buffers reduces the injected noise considerably, compared to CMOS buffers. The current in the LVDS buffer is independent of the direction of switching. Also, the low output swing as well as the differential nature of the LVDS buffer results in low-noise coupling. POWER-DOWN MODE LAYOUT OF PCB WITH PowerPAD THERMALLY-ENHANCED PACKAGES The ADS5242 has a power-down pin, referred to as PD. Pulling PD high causes the device to enter the power-down mode. In this mode, the reference and clock circuitry, as well as all the channels, are powered down. Device power consumption drops to less than 100mW in this mode. In power-down mode, the internal buffers driving REFT and REFB are tri-stated and their outputs are forced to a voltage roughly equal to half of the voltage on AVDD. Speed of recovery from power-down mode depends on the value of the external capacitance on the REFT and REFB pins. For capacitances on REFT and REFB less than 1µF, the reference voltages settle to within 1% of their steady-state values in less than 500µs. Individual channels can also be selectively powered down by programming registers. The ADS5242 is housed in an 80-lead PowerPAD thermally-enhanced package. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the printed circuit board (PCB) must be designed with this technology in mind. Please refer to SLMA004 PowerPAD brief PowerPAD Made Easy (refer to our web site at www.ti.com), which addresses the specific considerations required when integrating a PowerPAD package into a PCB design. For more detailed information, including thermal modeling and repair procedures, please see the technical brief SLMA002, PowerPAD Thermally-Enhanced Package (www.ti.com). Interfacing High-Speed LVDS Outputs (SBOA104), an application report discussing the design of a simple deserializer that can deserialize LVDS outputs up to 840Mbps, can also be found on the TI web site (www.ti.com). The ADS5242 also has an internal circuit that monitors the state of stopped clocks. If ADCLK is stopped for longer than 300ns (or if it runs at a speed less than 3MHz), this monitoring circuit generates a logic signal that puts the device in a partial power-down state. As a result, the power consumption of the device is reduced when ADCLK is stopped. The recovery from such a partial power-down takes ap- proximately 100µs; this is described in Table 2. CONNECTING HIGH-SPEED, MULTI-CHANNEL ADCs TO XILINX FPGAs A separate application note (XAPP774) describing how to connect TI's high-speed, multi-channel ADCs with serial LVDS outputs to Xilinx FPGAs can be downloaded directly from the Xilinx web site (http://www.xilinx.com). Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage DESCRIPTION Recovery from power-down mode (PD = 1 to PD = 0). TYP 500µs Recovery from momentary clock stoppage ( < 300ns). 10µs Recovery from extended clock stoppage ( > 300ns). 100µs 24 REMARKS Capacitors on REFT and REFB less than 1µF. ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 Changes from A Revision (September 2005) to B Revision .......................................................................................... Page • • • • • • • • • • • • • • • • Changed unit values for references of fourth bullet in Features section. .............................................................................. 1 Changed Synch to Bit in tenth bullet of Features section...................................................................................................... 1 Deleted parallel in first paragraph of Description section. ..................................................................................................... 1 Changed unit value of ninth row in Absolute Maximum Ratings table. ................................................................................. 2 Changed W to Ω in second footnote of Absolute Maximum Ratings table............................................................................ 2 Changed Assured to Tested in first row of DC Accuracy section in Electrical Characteristics table. ................................... 4 Changed unit values for typical column in Power Requirements section of Electrical Characteristics table. ....................... 4 Changed 512 to 2048 in first footnote of Electrical Characteristics table. ............................................................................. 5 Changed 1024LSB to 4096LSB in second footnote of Electrical Characteristics table......................................................... 5 Changed Typ conditions column of AC Characteristics table................................................................................................ 6 Deleted condition value for CO row of LVDS table. ............................................................................................................... 7 Changed 10 to 12 in second footnote of Test Patterns table. ............................................................................................. 10 Changed Figure 30. ............................................................................................................................................................. 18 Deleted heavily from first sentence of first paragraph of Reference Circuit Design section in Theory of Operation. ......... 22 Changed Figure 3. ............................................................................................................................................................... 22 Changed eight to four , ±2.0 to ±20, and added (±3σ) in seventh sentence of first paragraph of Clocking section in Theory of Operation. ............................................................................................................................................................ 22 Changes from B Revision (September 2005) to C Revision .......................................................................................... Page • • Added first footnote to Test Patterns table. ......................................................................................................................... 10 Changed 1Ω to 2Ω in REFB and REFT rows of Pin Descriptions table. .............................................................................. 12 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) ADS5242IPAP ACTIVE HTQFP PAP 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS5242IPAP ADS5242IPAPT ACTIVE HTQFP PAP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 ADS5242IPAP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of