ADS54J40IRMPT

ADS54J40 ADS54J40 SBAS714C – MAY 2015 – REVISED DECEMBER 2020 SBAS714C – MAY 2015 – REVISED DECEMBER 2020 www.ti.com ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter 1 Features 3 Description • • • The ADS54J40 is a low-power, wide-bandwidth, 14bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –158 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J40 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. • • • • • • • • • 14-bit resolution, dual-channel, 1-GSPS ADC Noise floor: –158 dBFS/Hz Spectral performance (fIN = 170 MHz at –1 dBFS): – SNR: 69.0 dBFS – NSD: –155.9 dBFS/Hz – SFDR: 86 dBc (Including Interleaving Tones) – SFDR: 89 dBc (Except HD2, HD3, and interleaving tones) Spectral performance (fIN = 350 MHz at –1 dBFS): – SNR: 66.3 dBFS – NSD: –153.3 dBFS/Hz – SFDR: 75 dBc – SFDR: 85 dBc (except HD2, HD3, and interleaving tones) Channel isolation: 100 dBc at fIN = 170 MHz Input full-scale: 1.9 VPP Input bandwidth (3 dB): 1.2 GHz On-chip dither Integrated wideband DDC block JESD204B interface with subclass 1 support: – 2 lanes per ADC at 10.0 Gbps – 4 lanes per ADC at 5.0 Gbps – Support for multi-chip synchronization Power dissipation: 1.35 W/ch at 1 GSPS Package: 72-pin VQFNP (10 mm × 10 mm) The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel. Device Information ADS54J40 (1) VQFNP (72) BODY SIZE (NOM) 10.00 mm × 10.00 mm For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications spacer • • • • • • • • spacer 0 -20 Amplitude (dBFS) Radar and antenna arrays Broadband wireless Cable CMTS, DOCSIS 3.1 receivers Communications test equipment Microwave receivers Software Defined Radio (SDR) Digitizers Medical imaging and diagnostics PACKAGE(1) PART NUMBER -40 -60 -80 -100 -120 0 100 200 300 Input Frequency (MHz) 400 500 D003 (SNR = 69 dBFS; SFDR = 86 dBc; fIN = 170 MHz, IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc) FFT for 170-MHz Input Signal An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: ADS54J40 1 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 ADS54J40 Comparison................................................... 5 6 Pin Configuration and Functions...................................5 7 Specifications.................................................................. 8 7.1 Absolute Maximum Ratings........................................ 8 7.2 ESD Ratings............................................................... 8 7.3 Recommended Operating Conditions.........................9 7.4 Thermal Information....................................................9 7.5 Electrical Characteristics...........................................10 7.6 AC Characteristics.................................................... 11 7.7 Digital Characteristics............................................... 14 7.8 Timing Requirements................................................ 15 7.9 Typical Characteristics.............................................. 17 8 Detailed Description......................................................27 8.1 Overview................................................................... 27 8.2 Functional Block Diagram......................................... 27 8.3 Feature Description...................................................28 8.4 Device Functional Modes..........................................36 8.5 Register Maps...........................................................48 9 Application Information Disclaimer............................. 85 9.1 Application Information............................................. 85 9.2 Typical Application.................................................. 103 10 Power Supply Recommendations............................106 10.1 Power Sequencing and Initialization..................... 106 11 Layout......................................................................... 107 11.1 Layout Guidelines................................................. 107 11.2 Layout Example.................................................... 107 12 Device and Documentation Support........................108 12.1 Documentation Support........................................ 108 12.2 Receiving Notification of Documentation Updates108 12.3 Support Resources............................................... 108 12.4 Trademarks........................................................... 108 12.5 Electrostatic Discharge Caution............................108 12.6 Glossary................................................................108 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2017) to Revision C (December 2020) Page • Added text '(Including Interleaving Tones)' to Features bullet............................................................................ 1 • Added ADS54J40 Comparison section, moved Device Comparison Table to this section.................................5 • Changed the description of SYSREFM, SYSREFP, and PDN pins in Pin Functions table ............................... 5 • Changed fIN = 470 MHz test conditions and typical values across parameters in AC Characteristics table.... 11 • Added fIN = 720 MHz test conditions across parameters in AC Characteristics table...................................... 11 • Changed ENOB unit from dBFS to Bits in AC Characteristics table................................................................. 11 • Changed typical values of SFDR_IL parameter ...............................................................................................11 • Changed first IMD3 typical value from –85 dBFS to –89 dBFS ....................................................................... 11 • Changed first footnote in Timing Characteristics table..................................................................................... 15 • Changed typical value of FOVR latency from 18 + 4 ns to 18 ......................................................................... 15 • Changed tPD parameter name to tPDI in Timing Characteristics table.............................................................. 15 • Changed FFT for 470-MHz Input Signal at –3 dBFS figure, title, and conditions............................................. 17 • Added FFT for 720-MHz Input Signal at –6 dBFS figure.................................................................................. 17 • Changed Spurious-Free Dynamic Range vs Input Frequency figure............................................................... 17 • Changed IL Spur vs Input Frequency figure..................................................................................................... 17 • Changed 16-bit to 14-bit in first sentence of Overview section.........................................................................27 • Added DDC Block section ............................................................................................................................... 30 • Changed Table 8-6 .......................................................................................................................................... 36 • Added last sentence to Step 4 in Serial Register Readout: Analog Bank section............................................ 39 • Added last sentence to Step 4 in Serial Register Readout: JESD Bank section.............................................. 40 • Added SDOUT Timing Diagram figure............................................................................................................. 40 • Changed the JESD204B Test Patterns section ............................................................................................... 43 • Changed Serial Interface Registers diagram....................................................................................................48 • Added register addresses 1 and 2 to GENERAL REGISTERS in Register Map section ................................ 48 • Changed the name of JESD ANALOG PAGE (6A00h) to JESD ANALOG PAGE (JESD BANK PAGE SEL=6A00h) in Register Map table ................................................................................................................. 48 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Changed bit 1, register 12 of JESD ANALOG PAGE (6A00h) from 0 to ALWAYS WRITE 1 .......................... 48 Added OFFSET READ Page and OFFSET LOAD Page registers to Register Map table .............................. 48 Added ADS54J40 Access Type Codes table....................................................................................................52 Deleted legends from bit registers in Register Descriptions section.................................................................53 Added register 1h and 2h to Register Descriptions section .............................................................................53 Added text '6100h = OFFSET READ or LOAD Page' to the JESD BANK PAGE SEL[7:0] bit description.......53 Changed description of Registers 3h and 4h (address = 3h and 4h)in General Registers Page. ................... 54 Changed description of bit 0 in Register 4Fh (address = 4Fh), Master Page (080h)....................................... 58 Changed Register 53H .................................................................................................................................... 59 Changed Register 54H .................................................................................................................................... 59 Changed Register 55H .................................................................................................................................... 60 Added Register 40h ......................................................................................................................................... 62 Changed Register 4Eh .................................................................................................................................... 67 Changed Register 52h .....................................................................................................................................67 Added Register 68h ......................................................................................................................................... 68 Changed the Register ABh description.............................................................................................................69 Changed bit 1 from 0 to ALWAYS WRITE 1 in Register 12h (address = 12h), JESD Analog Page (6A00h)... 76 Changed Register 1Ah .................................................................................................................................... 79 Added Offset Read Page Register and Offset Load Page Register sections to Register Descriptions section... 81 Changed Register 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh ............................................... 82 Changed Register 00h, 04h, 08h, 0Ch ............................................................................................................ 83 Changed Register 01h, 05h, 09h, 0Dh ............................................................................................................ 83 Added Register 78h ......................................................................................................................................... 84 Added DC Offset Correction Block in the ADS54J40 section...........................................................................89 Added Idle Channel Histogram section............................................................................................................ 93 Added the Interleaving (IL) Mismatch Compensation section.......................................................................... 94 Changed the description in Transformer-Coupled Circuits section.................................................................104 Changed the Layout Guidelines .................................................................................................................... 107 Changes from Revision A (October 2015) to Revision B (January 2017) Page • Added the Device Comparison Table ................................................................................................................ 5 • Added CDM row to ESD Ratings table............................................................................................................... 8 • Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table .. 9 • Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics section.....15 • Added the FOVR latency parameter to the Timing Characteristics table......................................................... 15 • Changed Overview section ..............................................................................................................................27 • Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR traces..................................................................................................................................................... 27 • Changed SYSREF Signal section: changed Table 8-4 and added last paragraph...........................................34 • Added SYSREF Not Present (Subclass 0, 2) section.......................................................................................34 • Changed the number of clock cycles in the Fast OVR section.........................................................................35 • Deleted Lane Enable with Decimation subsection ...........................................................................................45 • Added the Program Summary of DDC Modes and JESD Link Configuration table..........................................45 • Added Figure 8-27 to Register Maps section................................................................................................... 48 • Changed the Register Map ..............................................................................................................................48 • Deleted register 39h, 3Ah, and 56h ................................................................................................................. 48 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 3 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 • • • • Added Table 8-63 .............................................................................................................................................71 Changed Power Supply Recommendations section ......................................................................................106 Added the Power Sequencing and Initialization section................................................................................. 106 Added the Receiving Notification of Documentation Updates section............................................................108 Changes from Revision * (May 2015) to Revision A (October 2015) Page • Released to production ......................................................................................................................................1 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 5 ADS54J40 Comparison Table 5-1 lists companion devices to the ADS54J40 .(TBD: Why has it been shifted to this place? ) Table 5-1. Device Comparison Table PART NUMBER SPEED GRADE (MSPS) RESOLUTION (Bits) CHANNEL ADS54J20 1000 12 2 ADS54J42 625 14 2 ADS54J40 1000 14 2 ADS54J60 1000 16 2 ADS54J66 500 14 4 ADS54J69 500 16 2 DB2P DB2M IOVDD DB1P DB1M DGND DB0P DB0M IOVDD SYNC DA0M DA0P DGND DA1M DA1P IOVDD DA2M DA2P 6 Pin Configuration and Functions 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DB3M 1 54 DA3M DB3P 2 53 DA3P DGND 3 52 DGND IOVDD 4 51 IOVDD SDIN 5 50 PDN SCLK 6 49 RES SEN 7 48 RESET DVDD 8 47 DVDD AVDD 9 46 AVDD AVDD3V 10 45 AVDD3V SDOUT 11 44 AVDD AVDD 12 43 AVDD INBP 13 42 INAP INBM 14 41 INAM AVDD 15 40 AVDD AVDD3V 16 39 AVDD3V AVDD 17 38 AVDD AGND 18 37 AGND 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC NC VCM AGND AVDD3V AVDD AGND CLKINP CLKINM AGND AVDD AVDD3V AGND SYSREFP SYSREFM AVDD AGND GND Pad (Back Side) Figure 6-1. RMP Package, 72-Pin VQFNP, Top View Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 5 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 6-1. Pin Functions PIN NAME NO. I/O DESCRIPTION CLOCK, SYSREF CLKINM 28 I Negative differential clock input for the ADC. CLKINP 27 I Positive differential clock input for the ADC. SYSREFM 34 I Negative external SYSREF input. Connect this pin to GND if not used. SYSREFP 33 I Positive external SYSREF input. Connect this pin to 1.8 V if not used. PDN 50 I/O RESET 48 I CONTROL, SERIAL Power down, active low pin. Can be configured via an SPI register setting. Can be configured to fast overrange output for channel A through the SPI. This pin has an internal 20kΩ pulldown resistor. Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor. SCLK 6 I Serial interface clock input SDIN 5 I Serial interface data input SDOUT 11 O Serial interface data output. Can be configured to fast overrange output for channel B through the SPI. SEN 7 I Serial interface enable O JESD204B serial data negative outputs for channel A O JESD204B serial data positive outputs for channel A O JESD204B serial data negative outputs for channel B O JESD204B serial data positive outputs for channel B DATA INTERFACE DA0M 62 DA1M 59 DA2M 56 DA3M 54 DA0P 61 DA1P 58 DA2P 55 DA3P 53 DB0M 65 DB1M 68 DB2M 71 DB3M 1 DB0P 66 DB1P 69 DB2P 72 DB3P 2 SYNC 63 I Synchronization input for the JESD204B port INAM 41 I Differential analog negative input for channel A INAP 42 I Differential analog positive input for channel A INBM 14 I Differential analog negative input for channel B INBP 13 I Differential analog positive input for channel B VCM 22 O Common-mode voltage, 2.1 V. Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external connection from the VCM pin to the INxP or INxM pin is required. AGND 18, 23, 26, 29, 32, 36, 37 I Analog ground AVDD 9, 12, 15, 17, 25, 30, 35, 38, 40, 43, 44, 46 I Analog 1.9-V power supply 10, 16, 24, 31, 39, 45 I Analog 3.0-V power supply for the analog buffer INPUT, COMMON MODE POWER SUPPLY AVDD3V 6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 6-1. Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION DGND 3, 52, 60, 67 I Digital ground DVDD 8, 47 I Digital 1.9-V power supply IOVDD 4, 51, 57, 64, 70 I Digital 1.15-V power supply for the JESD204B transmitter 19-21 — 49 I NC, RES NC RES Unused pins, do not connect Reserved pin. Connect to DGND. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 7 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Supply voltage range MIN MAX AVDD3V –0.3 3.6 AVDD –0.3 2.1 DVDD –0.3 2.1 IOVDD –0.2 1.4 –0.3 0.3 Voltage between AGND and DGND Voltage applied to input pins V V INAP, INBP, INAM, INBM –0.3 3 CLKINP, CLKINM –0.3 AVDD + 0.3 SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDIN, RESET, SYNC, PDN –0.2 2.1 –65 150 Storage temperature, Tstg (1) UNIT V °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 8 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(2) (3) MIN AVDD3V Supply voltage range 2.85 3 3.6 1.8 1.9 2.0 DVDD 1.7 1.9 2.0 IOVDD 1.1 1.15 1.2 1.9 Input common-mode voltage amplitude(4) (5) Input clock frequency, device clock frequency Input clock amplitude differential (VCLKP – VCLKM) Sine wave, ac-coupled LVPECL, ac-coupled 1.5 0.8 1.6 LVDS, ac-coupled Input device clock duty cycle Temperature (1) (2) (3) (4) (5) (6) 50% –40 VPP 55% 85 105(1) Operating junction, TJ MHz 0.7 45% Operating free-air, TA MHz 1000 0.75 V V 400 250(6) UNIT VPP 2 Maximum analog input frequency for 1.9-VPP input Clock inputs MAX AVDD Differential input voltage range Analog inputs NOM 125 °C Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate. SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details. After power-up, always use a hardware reset to reset the device for the first time; see Table 9-1 for details. Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs. At high frequencies, the maximum supported input amplitude reduces; see Figure 7-37 for details. See Table 8-10. 7.4 Thermal Information ADS54J40 THERMAL METRIC(1) RMP (VQFNP) UNIT 72 PINS RθJA Junction-to-ambient thermal resistance 22.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.1 °C/W RθJB Junction-to-board thermal resistance 2.4 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 2.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 9 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.5 Electrical Characteristics Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1 GSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1000 MSPS GENERAL ADC sampling rate 250 Resolution 14 Bits POWER SUPPLIES AVDD3V 3.0-V analog supply 2.85 3.0 3.6 V AVDD 1.9-V analog supply 1.8 1.9 2.0 V DVDD 1.9-V digital supply 1.7 1.9 2.0 V IOVDD 1.15-V SERDES supply 1.1 1.15 1.2 V IAVDD3V 3.0-V analog supply current VIN = full-scale on both channels 334 360 mA IAVDD 1.9-V analog supply current VIN = full-scale on both channels 359 510 mA IDVDD 1.9-V digital supply current Eight lanes active (LMFS = 8224) 197 260 mA IIOVDD 1.15-V SERDES supply current Eight lanes active (LMFS = 8224) 566 920 mA Pdis Total power dissipation Eight lanes active (LMFS = 8224) 2.71 3.1 IDVDD 1.9-V digital supply current Four lanes active (LMFS = 4244) 211 mA W IIOVDD 1.15-V SERDES supply current Four lanes active (LMFS = 4244) 618 mA Pdis Total power dissipation Four lanes active (LMFS = 4244) 2.80 W IDVDD 1.9-V digital supply current Four lanes active (LMFS = 4222), 2X decimation 197 mA IIOVDD 1.15-V SERDES supply current Four lanes active (LMFS = 4222), 2X decimation 593 mA Pdis Total power dissipation Four lanes active (LMFS = 4222), 2X decimation 2.74 W IDVDD 1.9-V digital supply current Two lanes active (LMFS = 2221), 4X decimation 176 mA IIOVDD 1.15-V SERDES supply current Two lanes active (LMFS = 2221), 4X decimation 562 mA Pdis (1) Total power dissipation Two lanes active (LMFS = 2221), 4X decimation 2.66 W Global power-down power dissipation 139 315 mW ANALOG INPUTS (INAP, INAM, INBP, INBM) Differential input full-scale voltage 1.9 VPP VIC Common-mode input voltage 2.0 V RIN Differential input resistance At 170-MHz input frequency 0.6 kΩ CIN Differential input capacitance At 170-MHz input frequency 4.7 pF Analog input bandwidth (3 dB) 50-Ω source driving ADC inputs terminated with 50 Ω 1.2 GHz 1.15 V CLOCK INPUT (CLKINP, CLKINM) Internal clock biasing (1) 10 CLKINP and CLKINM are connected to internal biasing voltage through 400 Ω See the Power-down Mode section for details. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.6 AC Characteristics Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1 GSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS Signal-to-noise ratio fIN = 100 MHz, AIN = –1 dBFS 69.5 66.2 68.4 fIN = 270 MHz, AIN = –1 dBFS 67.9 fIN = 300 MHz, AIN = –1 dBFS 67.5 fIN = 370 MHz, AIN = –1 dBFS 66.5 fIN = 470 MHz, AIN = –3 dBFS 66.5 fIN = 720 MHz, AIN = –6 dBFS 64.9 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 63.3 Noise spectral density SINAD Signal-to-noise and distortion ratio 156.5 153.2 155.4 fIN = 270 MHz, AIN = –1 dBFS 154.9 fIN = 300 MHz, AIN = –1 dBFS 154.5 fIN = 370 MHz, AIN = –1 dBFS 153.5 fIN = 470 MHz, AIN = –3 dBFS 153.5 fIN = 720 MHz, AIN = –6 dBFS 151.9 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 150.3 fIN = 10 MHz, AIN = –1 dBFS 69.6 fIN = 100 MHz, AIN = –1 dBFS 69.3 65.2 68.3 fIN = 270 MHz, AIN = –1 dBFS 67.6 fIN = 300 MHz, AIN = –1 dBFS 67 fIN = 370 MHz, AIN = –1 dBFS 65.5 fIN = 470 MHz, AIN = –3 dBFS 65.7 fIN = 720 MHz, AIN = –6 dBFS 64.1 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 63.2 fIN = 170 MHz, AIN = –1 dBFS Spurious free dynamic range (excluding IL spurs dBFS/Hz 68.8 fIN = 230 MHz, AIN = –1 dBFS fIN = 100 MHz, AIN = –1 dBFS SFDR 155.9 fIN = 230 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS dBFS 156.7 fIN = 100 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS UNIT 68.9 fIN = 230 MHz, AIN = –1 dBFS fIN = 10 MHz, AIN = -1 dBFS NSD MAX 69.7 fIN = 170 MHz, AIN = –1 dBFS SNR MIN TYP fIN = 10 MHz, AIN = –1 dBFS dBFS 83 76 86 fIN = 230 MHz, AIN = –1 dBFS 85 fIN = 270 MHz, AIN = –1 dBFS 81 fIN = 300 MHz, AIN = –1 dBFS 78 fIN = 370 MHz, AIN = –1 dBFS 73 fIN = 470 MHz, AIN = –3 dBFS 71 fIN = 720 MHz, AIN = –6 dBFS 67 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 71 dBc Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 11 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.6 AC Characteristics (continued) Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1 GSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS Second-order harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 85 90 76 85 fIN = 270 MHz, AIN = –1 dBFS 81 fIN = 300 MHz, AIN = –1 dBFS 81 fIN = 370 MHz, AIN = –1 dBFS 76 fIN = 470 MHz, AIN = –3 dBFS 71 fIN = 720 MHz, AIN = –6 dBFS 67 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 71 fIN = 10 MHz, AIN = –1 dBFS 85 fIN = 170 MHz, AIN = –1 dBFS Third-order harmonic distortio Spurious-free dynamic range (excluding HD2, HD3, and IL spur) fIN = 270 MHz, AIN = –1 dBFS 81 fIN = 300 MHz, AIN = –1 dBFS 78 fIN = 370 MHz, AIN = –1 dBFS 73 fIN = 470 MHz, AIN = –3 dBFS 71 fIN = 720 MHz, AIN = –6 dBFS 74 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 83 fIN = 10 MHz, AIN = –1 dBFS 94 12 Effective number of bits 93 95 fIN = 270 MHz, AIN = –1 dBFS 95 fIN = 300 MHz, AIN = –1 dBFS 91 fIN = 370 MHz, AIN = –1 dBFS 85 fIN = 470 MHz, AIN = –3 dBFS 89 fIN = 720 MHz, AIN = –6 dBFS 89 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 93 fIN = 10 MHz, AIN = –1 dBFS 11.3 fIN = 100 MHz, AIN = –1 dBFS 11.2 10.5 dBFS 11.1 fIN = 230 MHz, AIN = –1 dBFS 11.1 fIN = 270 MHz, AIN = –1 dBFS 10.9 fIN = 300 MHz, AIN = –1 dBFS 10.8 fIN = 370 MHz, AIN = –1 dBFS 10.6 fIN = 470 MHz, AIN = –3 dBFS 10.6 fIN = 720 MHz, AIN = –6 dBFS 10.4 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 10.2 Submit Document Feedback dBc 97 79 fIN = 230 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS ENOB 86 87 fIN = 100 MHz, AIN = –1 dBFS Non HD2, HD3 dBc 83 76 fIN = 230 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS UNIT 92 fIN = 230 MHz, AIN = –1 dBFS fIN = 100 MHz, AIN = –1 dBFS HD3 MAX fIN = 100 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS HD2 MIN TYP Bits Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.6 AC Characteristics (continued) Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1 GSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS Total harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 82 80 73 82 fIN = 270 MHz, AIN = –1 dBFS 78 fIN = 300 MHz, AIN = –1 dBFS 75 fIN = 370 MHz, AIN = –1 dBFS 70 fIN = 470 MHz, AIN = –3 dBFS 70 fIN = 720 MHz, AIN = –6 dBFS 66 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 70 fIN = 10 MHz, AIN = –1 dBFS 85 fIN = 170 MHz, AIN = –1 dBFS IMD3 Crosstalk 83 82 fIN = 270 MHz, AIN = –1 dBFS 81 fIN = 300 MHz, AIN = –1 dBFS 81 fIN = 370 MHz, AIN = –1 dBFS 77 fIN = 470 MHz, AIN = –3 dBFS 78 fIN = 720 MHz, AIN = –6 dBFS 78 fIN = 720 MHz, AIN = –6 dBFS, gain = 5 dB 74 fIN1 = 185 MHz, fIN2 = 190 MHz, AIN = –7 dBFS –89 Two-tone, third-order intermodulation fIN1 = 365 MHz, fIN2 = 370 MHz, AIN = –7 dBFS distortion –79 fIN1 = 465 MHz, fIN2 = 470 MHz, AIN = –7 dBFS –75 Full-scale, 170-MHz signal on aggressor; idle channel is victim 100 Isolation between channel A and B dBc 84 69 fIN = 230 MHz, AIN = –1 dBFS Interleaving spur UNIT 83 fIN = 230 MHz, AIN = –1 dBFS fIN = 100 MHz, AIN = –1 dBFS SFDR_IL MAX fIN = 100 MHz, AIN = –1 dBFS fIN = 170 MHz, AIN = –1 dBFS THD MIN TYP dBc dBFS dB Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 13 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.7 Digital Characteristics Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1 GSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 0.8 TYP MAX UNITS DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)(1) VIH High-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels VIL Low-level input voltage All digital inputs support 1.2-V and 1.8-V logic levels IIH High-level input current IIL Low-level input current V 0.4 SEN 0 RESET, SCLK, SDIN, PDN, SYNC 50 SEN 50 RESET, SCLK, SDIN, PDN, SYNC V µA µA 0 DIGITAL INPUTS (SYSREFP, SYSREFM) VD Differential input voltage V(CM_DIG) Common-mode voltage for SYSREF 0.35 0.45 1.4 1.3 V V DIGITAL OUTPUTS (SDOUT, PDN(3)) VOH High-level output voltage VOL Low-level output voltage DVDD – 0.1 DVDD V 0.1 V DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2) VOD Output differential voltage VOC Output common-mode voltage Transmitter short-circuit current zos (2) (3) 14 Transmitter pins shorted to any voltage between – 0.25 V and 1.45 V Single-ended output impedance Output capacitance (1) With default swing setting Output capacitance inside the device, from either output to ground 700 mVPP 450 mV –100 100 mA 50 Ω 2 pF The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ (typical) pullup resistor to IOVDD. 100-Ω differential termination. When functioning as an OVR pin for channel B. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.8 Timing Requirements Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1.0 GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted. MIN TYP MAX UNITS SAMPLE TIMING (TBD are any of these Switching Characteristics?TBD: No) Aperture delay 0.75 Aperture delay matching between two channels on the same device 1.6 ±70 Aperture delay matching between two devices at the same temperature and supply voltage ns ps ±270 ps 120 fS rms 150 µs 134 Input clock cycles OVR latency: ADC sample to OVR bit 62 Input clock cycles FOVR latency: ADC sample to FOVR signal on pin 18 Input clock cycles 4 ns Aperture jitter WAKE-UP TIMING Wake-up time to valid data after coming out of global power-down LATENCY (1) Data latency: ADC sample to digital output tPDI Propagation delay: logic gates and output buffers delay (does not change with fS) SYSREF TIMING tSU_SYSREF Setup time for SYSREF, referenced to the input clock falling edge 300 tH_SYSREF 100 Hold time for SYSREF, referenced to the input clock falling edge 900 ps ps JESD OUTPUT INTERFACE TIMING CHARACTERISTICS Unit interval 100 400 ps Serial output data rate 2.5 10 Gbps Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 Random jitter for BER of 1E-15 and lane rate = 10 Gbps tR, tF (1) 0.75 ps ps rms Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk Data rise time, data fall time: rise and fall times are measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps 35 ps Overall latency = latency + tPDI. Sample N ts_min ts_max CLKIN 1.0 GSPS SYSREF Figure 7-1. SYSREF Timing Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 15 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 N+1 N+2 N N+3 Sample tPD Data Latency: 134 Clock Cycles CLKINM CLKINP DA0P, DA0M, DB0P, DB0M D 20 Sample N-1 DA1P, DA1M, DB1P, DB1M D 11 D 20 Sample N D 10 Sample N-1 D 20 Sample N+1 D 1 Sample N D 11 D 10 Sample N+2 D 1 Sample N+1 D 10 Sample N+2 Figure 7-2. Sample Timing Requirements 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 7.9 Typical Characteristics 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to T MAX = 85°C, ADC sampling rate = 1.0 GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted. -40 -60 -80 -100 -60 -80 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 100 D001 SNR = 69.7 dBFS; SFDR = 85 dBc; IL spur = 86 dBc; non HD2, HD3 spur = 89 dBc 200 300 Input Frequency (MHz) 400 500 D002 SNR = 69.2 dBFS; SFDR = 86 dBc; IL spur = 85 dBc; non HD2, HD3 spur = 94 dBc Figure 7-3. FFT for 10-MHz Input Signal Figure 7-4. FFT for 140-MHz Input Signal 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) -40 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 D003 100 200 300 Input Frequency (MHz) 400 500 D004 SNR = 68.9 dBFS; SFDR = 86 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc SNR = 68.1 dBFS; SFDR = 84 dBc; IL spur = 86 dBc; non HD2, HD3 spur = 86 dBc Figure 7-5. FFT for 170-MHz Input Signal Figure 7-6. FFT for 230-MHz Input Signal Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 17 ADS54J40 www.ti.com 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) SBAS714C – MAY 2015 – REVISED DECEMBER 2020 -40 -60 -80 -100 -60 -80 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 100 D005 200 300 Input Frequency (MHz) 400 500 D006 SNR = 66.2 dBFS; SFDR = 72 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 78 dBc Figure 7-7. FFT for 300-MHz Input Signal Figure 7-8. FFT for 370-MHz Input Signal 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) SNR = 67.4 dBFS; SFDR = 77 dBc; IL spur = 83 dBc; non HD2, HD3 spur = 85 dBc -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 0 500 100 D007 200 300 Input Frequency (MHz) 400 500 D070 SNR = 65.3 dBFS; SFDR = 71 dBc; IL spur = 83 dBc; non HD2, HD3 spur = 89 dBFS Figure 7-9. FFT for 470-MHz Input Signal at –3 dBFS Figure 7-10. FFT for 720-MHz Input Signal at –6 dBFS 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) SNR = 66.5 dBFS; SFDR = 73 dBc; IL spur = 81 dBc; non HD2, HD3 spur = 88 dBc -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 D008 fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS, IMD3 = 85 dBFS Figure 7-11. FFT for Two-Tone Input Signal (–7 dBFS) 18 -40 100 200 300 Input Frequency (MHz) 400 500 D009 fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS, IMD3 = 103 dBFS Figure 7-12. FFT for Two-Tone Input Signal (–36 dBFS) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 SBAS714C – MAY 2015 – REVISED DECEMBER 2020 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) www.ti.com -40 -60 -80 -100 -80 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 100 D010 fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –7 dBFS, IMD3 = 80 dBFS Figure 7-13. FFT for Two-Tone Input Signal (–7 dBFS) 0 -20 -20 -60 -80 400 500 D011 Figure 7-14. FFT for Two-Tone Input Signal (–36 dBFS) 0 -40 200 300 Input Frequency (MHz) fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –36 dBFS, IMD3 = 109 dBFS Amplitude (dBFS) Amplitude (dBFS) -60 -100 -120 -100 -40 -60 -80 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 Figure 7-15. FFT for Two-Tone Input Signal (–7 dBFS) 200 300 Input Frequency (MHz) 400 500 D013 fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS, IMD3 = 109.2 dBFS Figure 7-16. FFT for Two-Tone Input Signal (–36 dBFS) -82 -76 -86 -80 -84 IMD (dBFS) -90 -94 -98 -102 -88 -92 -96 -100 -106 -110 -35 100 D012 fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –7 dBFS, IMD3 = 74.9 dBFS IMD (dBFS) -40 -104 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 -108 -35 D014 fIN1 = 185 MHz, fIN2 = 190 MHz -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D015 fIN1 = 365 MHz, fIN2 = 370 MHz Figure 7-17. Intermodulation Distortion vs Input Tone Amplitude Figure 7-18. Intermodulation Distortion vs Input Tone Amplitude Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 19 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 90 -70 AIN = -6 dBFS Ain = -3 dBFS AIN = -1 dBFS -74 85 -78 SFDR (dBc) IMD (dBFS) -82 -86 -90 -94 80 75 70 -98 65 -102 -106 -35 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 60 -7 0 100 200 300 400 500 Input Frequency (MHz) D016 fIN1 = 465 MHz, fIN2 = 470 MHz Figure 7-19. Intermodulation Distortion vs Input Tone Amplitude 90 60 52 78 48 74 44 AIN = -6 dBFS AIN = -3 dBFS AIN = -1 dBFS 70 SNR (dBFS) 82 D017 71 IL Disable, IL Spur (dBc) IL Enable, IL Spur (dBc) 56 700 Figure 7-20. Spurious-Free Dynamic Range vs Input Frequency IL Enable IL Disable 86 600 69 68 67 66 70 0 40 40 80 120 160 200 240 280 320 360 400 440 480 Input Frequency (MHz) D500 65 0 Figure 7-21. IL Spur vs Input Frequency AVDD = 1.95 V AVDD = 2 V 70 90 69.5 88 69 68.5 700 D042 84 82 67.5 80 10 35 Temperature (°C) 60 85 AVDD = 1.95 V AVDD = 2 V 86 68 -15 AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 92 SFDR (dBc) SNR (dBFS) 600 94 AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 70.5 78 -40 D020 fIN = 170 MHz -15 10 35 Temperature (°C) 60 85 D021 fIN = 170 MHz Figure 7-23. Signal-to-Noise Ratio vs AVDD Supply and Temperature 20 200 300 400 500 Input Frequency (MHz) Figure 7-22. Signal-to-Noise Ratio vs Input Frequency 71 67 -40 100 Figure 7-24. Spurious-Free Dynamic Range vs AVDD Supply and Temperature Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 79 72 AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 71 AVDD = 1.95 V AVDD = 2 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 78 AVDD = 1.95 V AVDD = 2 V 69 SFDR (dBc) SNR (dBFS) 70 68 67 77 76 75 66 74 65 64 -40 -15 10 35 Temperature (°C) 60 85 73 -40 -15 D022 fIN = 350 MHz D023 92 DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V 90 SFDR (dBc) 70.2 SNR (dBFS) 85 Figure 7-26. Spurious-Free Dynamic Range vs AVDD Supply and Temperature 71 69.4 68.6 67.8 DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V 88 86 84 -15 10 35 Temperature (°C) 60 82 -40 85 -15 D024 fIN = 170 MHz 10 35 Temperature (°C) 60 85 D025 fIN = 170 MHz Figure 7-27. Signal-to-Noise Ratio vs DVDD Supply and Temperature Figure 7-28. Spurious-Free Dynamic Range vs DVDD Supply and Temperature 70 82 DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V 69 DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V 80 68 SFDR (dBc) SNR (dBFS) 60 fIN = 350 MHz Figure 7-25. Signal-to-Noise Ratio vs AVDD Supply and Temperature 67 -40 10 35 Temperature (°C) 67 DVDD = 1.9 V DVDD = 1.95 V DVDD = 2 V 78 76 66 74 65 64 -40 -15 10 35 Temperature (°C) 60 85 72 -40 D026 fIN = 350 MHz -15 10 35 Temperature (°C) 60 85 D027 fIN = 350 MHz Figure 7-29. Signal-to-Noise Ratio vs DVDD Supply and Temperature Figure 7-30. Spurious-Free Dynamic Range vs DVDD Supply and Temperature Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 21 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 71 94 AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V 92 90 70 SFDR (dBc) SNR (dBFS) 70.5 AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V 69.5 69 88 86 84 68.5 82 68 -40 -15 10 35 Temperature (°C) 60 80 -40 85 -15 10 35 Temperature (°C) D028 fIN = 170 MHz 60 85 D029 fIN = 170 MHz Figure 7-31. Signal-to-Noise Ratio vs AVDD3V Supply and Temperature Figure 7-32. Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature 71 82 AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V 70 AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V AVDD3V = 2.85 V AVDD3V = 3 V AVDD3V = 3.1 V AVDD3V = 3.2 V 80 SFDR (dBc) 69 SNR (dBFS) AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V 68 67 AVDD3V = 3.3 V AVDD3V = 3.4 V AVDD3V = 3.5 V AVDD3V = 3.6 V 78 76 66 74 65 64 -40 -15 10 35 Temperature (°C) 60 72 -40 85 -15 fIN = 350 MHz 85 D031 Figure 7-34. Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature 110 79 Gain = 0 dB Gain = 2 dB Gain = 4 dB 76 Gain = 6 dB Gain = 8 dB Gain = 10 dB Gain = 12 dB Gain = 0 dB Gain = 2 dB Gain = 4 dB 105 100 73 70 SFDR (dBc) SNR (dBFS) 60 fIN = 350 MHz Figure 7-33. Signal-to-Noise Ratio vs AVDD3V Supply and Temperature 67 64 Gain = 6 dB Gain = 8 dB Gain = 10 dB Gain = 12 dB 95 90 85 80 61 75 58 70 55 65 0 80 160 240 320 Input Frequency (MHz) 400 480 0 D053 Figure 7-35. Signal-to-Noise Ratio vs Gain and Input Frequency 22 10 35 Temperature (°C) D030 80 160 240 320 Input Frequency (MHz) 400 480 D054 Figure 7-36. Spurious-Free Dynamic Range vs Gain and Input Frequency Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com Fundamental Amplitude (dBFS) 2 75 0 SNR (dBFS) -2 -4 73 200 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 160 71 120 69 80 67 40 -6 -8 -10 0 100 200 300 400 500 600 700 Input Frequency (MHz) 800 65 -70 900 1000 SFDR (dBc,dBFS) SBAS714C – MAY 2015 – REVISED DECEMBER 2020 0 -60 -50 D046 Figure 7-37. Maximum Supported Amplitude vs Frequency -40 -30 Amplitude (dBFS) -20 -10 0 D032 fIN = 170 MHz Figure 7-38. Performance vs Input Amplitude 120 69.5 90 68 60 66.5 30 0 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 74 100 72 90 70 80 68 70 66 0.2 0 D033 fIN = 350 MHz 75 Figure 7-40. Performance vs Sampling Clock Amplitude 125 73 100 72 100 69 75 66 50 63 25 0 2.2 SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 0.6 1 1.4 1.8 Differential Clock Amplitude (Vpp) D034 fIN = 170 MHz Figure 7-39. Performance vs Input Amplitude 60 0.2 60 2.2 0.6 1 1.4 1.8 Differential Clock Amplitude (Vpp) 72 95 71 90 70 85 69 80 68 30 35 D035 fIN = 350 MHz 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) 65 -70 110 SNR SFDR SFDR (dBc) 71 76 SNR (dBFS) 72.5 180 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 150 SFDR (dBc,dBFS) SNR (dBFS) 74 75 70 D036 fIN = 170 MHz Figure 7-41. Performance vs Sampling Clock Amplitude Figure 7-42. Performance vs Input Clock Duty Cycle Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 23 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 72 71 88 SNR SFDR 84 70 80 69 76 68 72 67 68 66 64 -10 PSRR with 25-mVpp Signal on AVDD PSRR with 50-mVpp Signal on AVDD3V -15 PSRR (dB) -25 SFDR (dBc) SNR (dBFS) -20 -30 -35 -40 -45 -50 65 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 60 70 -55 -60 0 50 D037 100 150 200 250 Frequency of Signal on Supply (MHz) fIN = 350 MHz Figure 7-44. Power-Supply Rejection Ratio vs Test Signal Frequency 0 -20 -20 -25 -30 -40 CMRR (dB) Amplitude (dBFS) D038 fIN = 170 MHz Figure 7-43. Performance vs Input Clock Duty Cycle -60 -80 -35 -40 -45 -100 -50 -120 -55 0 100 200 300 Input Frequency (MHz) 400 500 0 D039 50 100 150 200 250 Frequency of Input Common-Mode Signal (MHz) fIN = 170 MHz , AIN = –1 dBFS, SINAD = 65.7 dBFS, SFDR = 79 dBc, fPSRR = 5 MHz, APSRR = 25 mVPP, amplitude of fIN – fPSRR = –74 dBFS, amplitude of fIN + fPSRR = –76 dBFS Figure 7-45. Power-Supply Rejection Ratio FFT for Test Signals on the AVDD Supply 4 -20 3.5 -60 -80 D040 Figure 7-46. Common-Mode Rejection Ratio vs Test Signal Frequency 0 -40 300 fIN = 170 MHz Power Consumption (W) Amplitude (dBFS) 300 3 2.5 2 1.5 -100 -120 0 100 200 300 Input Frequency (MHz) 400 500 1 500 D041 fIN = 170.1 MHz , AIN = –1 dBFS, fCMRR = 5 MHz, ACMRR = 50 mVPP, SINAD = 67.3 dBFS, SFDR = 85 dBc, amplitude of fIN ± fCMRR= –80 dBFS 550 600 650 700 750 800 850 Sampling Speed (MSPS) 900 950 1000 D042 Figure 7-48. Power Consumption vs Sampling Speed Figure 7-47. Common-Mode Rejection Ratio FFT 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 I DVDD (mA) I AVDD (mA) I IOVDD (mA) 700 I AVDD3 (mA) Total Power (W) 2.78 0 2.76 -20 2.74 500 2.72 400 2.7 300 2.68 200 2.66 -100 2.64 85 -120 100 -40 -15 10 35 Temperature (°C) 60 Amplitude (dBFS) 600 Total Power (W) IAVDD,IDVDD,IAVDD3,IIOVDD (mA) 800 -40 -60 -80 0 25 D045 Figure 7-49. Power vs Temperature 50 75 Input Frequency (MHz) 100 125 D047 SNR = 73.1 dBFS, SFDR = 88.6 dBc 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) Figure 7-50. FFT for 60-MHz Input Signal in Decimate-by-4 Mode -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 25 50 75 Input Frequency (MHz) 100 0 125 50 75 Input Frequency (MHz) 100 125 D049 SNR = 71.1 dBFS, SFDR = 86 dBc SNR = 72.5 dBFS, SFDR = 87 dBc Figure 7-51. FFT for 170-MHz Input Signal in Decimate-by-4 Mode Figure 7-52. FFT for 300-MHz Input Signal in Decimate-by-4 Mode 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) 25 D048 -40 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 25 50 75 Input Frequency (MHz) 100 125 0 50 D050 SNR = 68.7 dBFS, SFDR = 83 dBc 100 150 Input Frequency (MHz) 200 250 D051 SNR = 70.5 dBFS, SFDR = 86 dBc Figure 7-53. FFT for 450-MHz Input Signal in Decimate-by-4 Mode Figure 7-54. FFT for 170-MHz Input Signal in Decimate-by-2 Mode Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 25 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 0 Amplitude (dBFS) -20 -40 -60 -80 -100 -120 0 50 100 150 Input Frequency (MHz) 200 250 D052 SNR = 67.6 dBFS, SFDR = 80 dBc Figure 7-55. FFT for 350-MHz Input Signal in Decimate-by-2 Mode 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8 Detailed Description 8.1 Overview The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). The ADS54J40 employs four interleaving ADCs for each channel to achieve a noise floor of – 159 dBFS/Hz. The ADS54J40 uses TI's proprietary interleaving and dither algorithms to achieve a clean spectrum with a high spurious-free dynamic range (SFDR). The device also offers various programmable decimation filtering options for systems requiring higher signal-to-noise ratio (SNR) and SFDR over a wide range of frequencies. Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify the driving network on-board. The JESD204B interface reduces the number of interface lines with two-lane and four-lane options, allowing a high system integration density. The JESD204B interface operates in subclass 1, enabling multi-chip synchronization with the SYSREF input. 8.2 Functional Block Diagram ADC ADC ADC INAP, INAM ADC Interleaving Correction DA2P, DA2M, DA3P, DA3M PLL: x20 x40 Divide-by4 CLKINP, CLKINM SYSREFP, SYSREFM Buffer ADC ADC ADC ADC INBP, INBM DA0P, DA0M, DA1P, DA1M DDC Block: 2x, 4x Decimation Mixer: fS / 16, fS / 4 Digital Block DDC Block: 2X, 4X Decimation Mixer: fS / 16, fS / 4 Digital Block Interleaving Correction JESD204B Interface Buffer SYNC DB0P, DB0M, DB1P, DB1M DB2P, DB2M, DB3P, DB3M FOVR SCLK SEN SDIN RESET PDN Control and SPI Common Mode SDOUT VCM Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 27 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3 Feature Description 8.3.1 Analog Inputs The ADS54J40 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source that enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more constant SFDR performance across input frequencies. The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in Figure 8-1. 0.77 : 2 nH 0.6 : 500 fF 150 fF 150 fF 1: 200 fF 3.3 : 3 pF 375 fF INP 40 : 0.77 : 1: 150 fF 200 fF 3.3 : 600 : 3 pF 375 fF VCM 40 : 600 : 0.77 : 150 fF 2 nH 0.6 : 500 fF 150 fF 1: 200 fF 3.3 : 3 pF 375 fF INM 40 : 0.77 : 1: 150 fF 200 fF 3.3 : 3 pF 375 fF 40 : Figure 8-1. Analog Input Network 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 The input bandwidth shown in Figure 8-2 is measured with respect to a 50-Ω differential input termination at the ADC input pins. Figure x shows the signal processing done inside the DDC block of the ADS54J40. Output Power/Input Power (dB) 0 -3 -6 -9 -12 -15 -18 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Input Frequency (MHz) D056 Figure 8-2. Transfer Function vs Frequency Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 29 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3.2 DDC Block The ADS54J40 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is followed by a DDC block consisting of three different decimate-by-2 and decimate-by-4 finite impulse response (FIR) half-band filter options. The different decimation filter options can be selected through SPI programming.Figure 8-3 shows the signal processing done inside the DDC block of the ADS54J40 Default 14-Bit Data (At 1 GSPS) Decimate-by-2 Data (At 500 MSPS) LPF 2 BPF 4 Decimate-by-4 Data (At 250 MSPS) Interleaving Engine, Ch X Digital Features 1 GSPS Data, x(n) To JESD Encoder 4 LPF Decimate-by-4, I-Data (At 250 MSPS) cos(2 n Œ fmix / fS)(1) sin(2 n Œ fmix / fS)(1) LPF Decimate-by-4 Q-Data (At 250 MSPS) 4 Mode Selection Using DECFIL MODE[3:0] Register Bits A. In IQ decimate-by-4 mode, the mixer frequency is fixed at fmix = fS / 4. For fS = 1 GSPS and fmix = 250 MHz. Figure 8-3. DDC Block 30 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3.2.1 Decimate-by-2 Filter This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 8-1 shows corner frequencies for low-pass and high-pass filter options. Table 8-1. Corner Frequencies for the Decimate-by-2 Filter CORNERS (dB) LOW PASS HIGH PASS –0.1 0.202 × fS 0.298 × fS –0.5 0.210 × fS 0.290 × fS –1 0.215 × fS 0.285 × fS –3 0.227 × fS 0.273 × fS Figure 8-4 and Figure 8-5 show the frequency response of decimate-by-2 filter from dc to fS / 2. 0.5 5 0 -20 Magnitude (dB) Magnitude (dB) -0.5 -45 -70 -1 -1.5 -2 -95 -2.5 -120 -3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency Response 0.4 0.45 0.5 0 D013 Figure 8-4. Decimate-by-2 Filter Response 0.05 0.1 0.15 Frequency Response 0.2 0.25 D014 Figure 8-5. Decimate-by-2 Filter Response (Zoomed) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 31 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer This band-pass decimation filter consists of a digital mixer and three concatenated FIR filters with a combined latency of approximately 28 output clock cycles. The alias band attenuation is approximately 55 dB and the pass-band flatness is ±0.1 dB. By default after reset, the band-pass filter is centered at fS / 16. Using the SPI, the center frequency can be programmed at N × fS / 16 (where N = 1, 3, 5, or 7). Table 8-2 shows corner frequencies for two extreme options. Table 8-2. Corner frequencies for the Decimate-by-4 Filter CORNERS (dB) CORNER FREQUENCY AT LOWER SIDE (Center Frequency fS / 16) CORNER FREQUENCY AT HIGHER SIDE (Center Frequency fS / 16) –0.1 0.011 × fS 0.114 × fS –0.5 0.010 × fS 0.116 × fS –1 0.008 × fS 0.117 × fS –3 0.006 × fS 0.120 × fS Figure 8-6 and Figure 8-7 show the frequency response of the decimate-by-4 filter for center frequencies fS / 16 and 3 × fS / 16 (N = 1 and N = 3, respectively). 0.2 10 0.1 0 0 -0.1 -20 Magnitude (dB) Magnitude (dB) -10 -30 -40 -50 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -60 -0.8 -70 -0.9 -80 -1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency Response 0.4 0.45 0.5 Figure 8-6. Decimate-by-4 Filter Response 32 0 D015 0.05 0.1 0.15 Frequency Response 0.2 0.25 D016 Figure 8-7. Decimate-by-4 Filter Response (Zoomed) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3.2.3 Decimate-by-4 Filter with IQ Outputs In this configuration, the DDC block includes a fixed digital fS / 4 mixer. Thus, the IQ pass band is approximately ±110 MHz, centered at fS / 4. This decimation filter has 41 taps with a latency of approximately ten output clock cycles. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 8-3 shows the corner frequencies for a low-pass, decimate-by-4 IQ filter. Table 8-3. Corner Frequencies for a Decimate-by-4 IQ Output Filter CORNERS (dB) LOW PASS –0.1 0.107 × fS –0.5 0.112 × fS –1 0.115 × fS –3 0.120 × fS Figure 8-8 and Figure 8-9 show the frequency response of a decimate-by-4 IQ output filter from dc to fS / 2. 0.5 5 0 -20 Magnitude (dB) Magnitude (dB) -0.5 -45 -70 -1 -1.5 -2 -95 -2.5 -120 -3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency Response 0.4 0.45 0.5 0 D011 Figure 8-8. Decimate-by-4 IQ Output Filter Response 0.025 0.05 0.075 Frequency Response 0.1 0.125 D012 Figure 8-9. Decimate-by-4 IQ Output Filter Response (Zoomed) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 33 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3.3 SYSREF Signal The SYSREF signal is a periodic signal that is sampled by the ADS54J40 device clock and used to align the boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of the local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and frames per multi-frame settings. The SYSREF signal is recommended to be a low-frequency signal in the range of 1 MHz to 5 MHz to reduce coupling to the signal path both on the printed circuit board (PCB) as well as internal in the device. The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and Table 8-4. SYSREF = LMFC / 2N (1) where • N = 0, 1, 2, and so forth. Table 8-4. Local Multi-Frame Clock Frequency (1) (2) LMFS CONFIGURATION DECIMATION LMFC CLOCK(1) (2) 4211 — fS / K 4244 — (fS / 4) / K 8224 — (fS / 4) / K 4222 2X (fS / 4) / K 2242 2X (fS / 4) / K 2221 4X (fS / 4) / K 2441 4X (IQ) (fS / 4) / K 4421 4X (IQ) (fS / 4) / K 1241 4X (fS / 4) / K K = Number of frames per multi frame (JESD digital page 6900h, address 06h, bits 4-0). fS = sampling (device) clock frequency. For example, if LMFS = 8224 then the programmed value of K is 9 (the actual value is 9 + 1 = 10 because the actual value for K = the value set in the SPI register +1). If the device clock frequency is fS = 1000 MSPS, then the local multi-frame clock frequency becomes (1000 / 4) / 10 = 25 MHz. The SYSREF signal frequency can be chosen as the LMFC frequency / 8 = 3.125 MHz. 8.3.3.1 SYSREF Not Present (Subclass 0, 2) A SYSREF pulse is required by the ADS54J40 to reset internal counters. If SYSREF is not present, as can be the case in subclass 0 or 2, this pulse can be done by doing the following register writes shown in Table 8-5. Table 8-5. Internally Pulsing SYSREF Twice Using Register Writes 34 ADDRESS (Hex) DATA (Hex) COMMENT 0-011h 80h Set the master page 0-054h 80h Enable manual SYSREF 0-053h 01h Set SYSREF high 0-053h 00h Set SYSREF low 0-053h 01h Set SYSREF high 0-053h 00h Set SYSREF low Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.3.4 Overrange Indication The ADS54J40 provides a fast overrange indication that can be presented in the digital output data stream via SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured through the SPI to output the fast OVR indicator. JESD 8b/10b encoder receives 16-bit data that is formed by 14-bit ADC data padded with two 0s as LSBs. When the FOVR indication is embedded in the output data stream, it replaces the LSB of the 16-bit data stream going to the 8b/10b encoder, as shown in Figure 8-10. 16-Bit Data Output (14-Bit ADC Data Padded with Two 0s) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0, OVR 16-Bit Data Going to the 8b, 10b Encoder Figure 8-10. Overrange Indication in a Data Stream 8.3.4.1 Fast OVR The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after only 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns), thus enabling a quicker reaction to an overrange event. The input voltage level that the overload is detected at is referred to as the threshold. The threshold is programmable using the FOVR THRESHOLD bits, as shown in Figure 8-11. The FOVR is triggered 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns) after the overload condition occurs. 0 FOVR Threshold (dBFS) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0 32 64 96 128 160 192 Threshold Decimal Value 224 255 D055 Figure 8-11. Programming Fast OVR Thresholds The input voltage level that the fast OVR is triggered at is defined by Equation 2: Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255) (2) The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS. In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3: 20log (FOVR Threshold / 255) (3) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 35 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4 Device Functional Modes 8.4.1 Power-Down Mode The ADS54J40 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN pin or SPI register writes. A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in Table 8-6. See the master page registers in Register Maps for further details. Table 8-6. Register Address for Power-Down Modes REGISTER ADDRESS REGISTER DATA COMMENT A[7:0] (Hex) 7 6 5 4 3 2 0 0 1 0 MASTER PAGE (80h) 20 21 23 24 26 MASK 1 MASK 2 CONFIG 55 PDN ADC CHA PDN BUFFER CHB PDN ADC CHB PDN BUFFER CHA PDN ADC CHA PDN BUFFER CHB PDN BUFFER CHA GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0 PDN ADC CHB 0 0 0 0 0 0 0 0 0 PDN MASK 0 0 0 0 To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However, when JESD must remain linked up when putting the device in power-down, the ADC and analog buffer can be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 8-7 shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits. Table 8-7. Power Consumption in Different Power-Down Settings REGISTER BIT COMMENT IAVDD3V (mA) IAVDD (mA) IDVDD (mA) TOTAL IIOVDD (mA) POWER (W) Default After reset, with a full-scale input signal to both channels 336 358 198 533 2.68 GBL PDN = 1 The device is in complete power-down state 2 6 22 199 0.29 GBL PDN = 0, PDN ADC CHx = 1 (x = A or B) The ADC of one channel is powered down 274 223 135 512 2.09 GBL PDN = 0, PDN BUFF CHx = 1 (x = A or B) The input buffer of one channel is powered down 262 352 194 545 2.45 GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = A or B) The ADC and input buffer of one channel is powered down 198 222 132 508 1.85 GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = A and B) The ADC and input buffer of both channels are powered down 60 85 66 484 1.02 36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.2 Device Configuration The ADS54J40 can be configured by using a serial programming interface, as described in the Serial Interface section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode. The ADS54J40 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register Maps section) to access all register bits. 8.4.2.1 Serial Interface The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 8-12. Legends used in Figure 8-12 are explained in Table 8-8. Serially shifting bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle. Register Address[11:0] SDIN R/W M P CH A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 8-12. SPI Timing Diagram Table 8-8. SPI Timing Diagram Legend SPI BITS DESCRIPTION BIT SETTINGS Read/write bit 0 = SPI write 1 = SPI read back M SPI bank access 0 = Analog SPI bank (master and ADC pages) 1 = JESD SPI bank (main digital, JESD analog, and JESD digital pages) P JESD page selection bit 0 = Page access 1 = Register access SPI access for a specific channel of the JESD SPI bank 0 = Channel A 1 = Channel B By default, both channels are being addressed. A[11:0] SPI address bits — D[7:0] SPI data bits — R/W CH Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 37 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 8-9 shows the timing requirements for the serial interface signals in Figure 8-12. Table 8-9. SPI Timing Requirements MIN TYP MAX UNIT 2 MHz fSCLK SCLK frequency (equal to 1 / tSCLK) > dc tSLOADS SEN to SCLK setup time 100 ns tSLOADH SCLK to SEN hold time 100 ns tDSU SDIN setup time 100 ns tDH SDIN hold time 100 ns 8.4.2.2 Serial Register Write: Analog Bank The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J40 analog SPI bank can be programmed by: 1. Driving the SEN pin low. 2. Initiating a serial interface cycle specifying the page address of the register whose content must be written. • Master page: write address 0011h with 80h. • ADC page: write address 0011h with 0Fh. 3. Writing the register content as shown in Figure 8-13. When a page is selected, multiple writes into the same page can be done. SDIN 0 0 0 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET Figure 8-13. Serial Register Write Timing Diagram 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.2.3 Serial Register Readout: Analog Bank The content from one of the two analog banks can be read out by: 1. Driving the SEN pin low. 2. Selecting the page address of the register whose content must be read. • Master page: write address 0011h with 80h. • ADC page: write address 0011h with 0Fh. 3. Setting the R/W bit to 1 and writing the address to be read back. 4. Reading back the register content on the SDOUT pin, as shown in Figure 8-14. When a page is selected, multiple read backs from the same page can be done. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 68 ns; see Figure 8-18. SDIN 1 0 0 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] = XX A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET SDOUT SDOUT[7:0] Figure 8-14. Serial Register Read Timing Diagram 8.4.2.4 JESD Bank SPI Page Selection The JESD SPI bank contains four pages (main digital, JESD digital, and JESD analog pages). The individual pages can be selected by: 1. Driving the SEN pin low. 2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as shown in Figure 8-15. • Write address 4003h with 00h (LSB byte of the page address). • Write address 4004h with the MSB byte of the page address. – For the main digital page: write address 4004h with 68h. – For the JESD digital page: write address 4004h with 69h. – For the JESD analog page: write address 4004h with 6Ah. SDIN 0 1 0 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET Figure 8-15. SPI Page Selection Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 39 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.2.5 Serial Register Write: JESD Bank The ADS54J40 is a dual-channel device and the JESD204B portion is configured individually for each channel by using the CH bit. Note that the P bit must be set to 1 for register writes. 1. Drive the SEN pin low. 2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0. • Write address 4003h with 00h. • Write address 4005h with 01h to enable separate control for both channels. – For the main digital page: write address 4004h with 68h. – For the JESD digital page: write address 4004h with 69h. – For the JESD analog page: write address 4004h with 6Ah. 3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as shown in Figure 8-16. When a page is selected, multiple writes into the same page can be done. SDIN 0 1 1 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET Figure 8-16. JESD Serial Register Write Timing Diagram 8.4.2.5.1 Individual Channel Programming By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h with 01h (default is 00h). 8.4.2.6 Serial Register Readout: JESD Bank The content from one of the pages of the JESD bank can be read out by: 1. Driving the SEN pin low. 2. Selecting the JESD bank page. Note that the M bit = 1 and the P bit = 0. • Write address 4003h with 00h. • Write address 4005h with 01h to enable separate control for both channels. – For the main digital page: write address 4004h with 68h. – For the JESD digital page: write address 4004h with 69h. – For the JESD analog page: write address 4004h with 6Ah. 3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read back. 4. Reading back the register content on the SDOUT pin; see Figure 8-17. When a page is selected, multiple read backs from the same page can be done. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 68 ns; see Figure 8-18. 40 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SDIN SBAS714C – MAY 2015 – REVISED DECEMBER 2020 1 1 1 0 R/W M P CH Register Address[11:0] A11 A10 A9 A8 A7 A6 A5 A4 Register Data[7:0] = XX A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN RESET SDOUT SDOUT[7:0] Figure 8-17. JESD Serial Register Read Timing Diagram SCLK tSD_DELAY SDOUT Figure 8-18. SDOUT Timing Diagram Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 41 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.3 JESD204B Interface The ADS54J40 supports device subclass 1 with a maximum output data rate of 10.0 Gbps for each serial transmitter. An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks. Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four lanes per single ADC, as shown in Figure 8-19. The JESD204B setup and configuration of the frame assembly parameters is controlled through the SPI interface. SYSREF SYNC INA JESD204B JESD204B DA[3:0] INB JESD204B JESD204B DB[3:0] Sample Clock Figure 8-19. ADS54J40 Block Diagram The JESD204B transmitter block shown in Figure 8-20 consists of the transport layer, the data scrambler, and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled. JESD204B Block Transport Layer Link Layer 8b, 10b Encoding Frame Data Mapping Scrambler 1 + x14 + x15 D[3:0] Comma Characters, Initial Lane Alignment SYNC Figure 8-20. JESD204B Transmitter Block 42 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.3.1 JESD204B Initial Lane Alignment (ILA) The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in Figure 8-21. When a logic low is detected on the SYNC input pin, the ADS54J40 starts transmitting comma (K28.5) characters to establish a code group synchronization. When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J40 starts the initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J40 transmits four multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data. SYSREF LMFC Clock LMFC Boundary Multi Frame SYNC Transmit Data xxx K28.5 Code Group Synchronization K28.5 ILA Initial Lane Alignment ILA DATA DATA Data Transmission Figure 8-21. Lane Alignment Sequence 8.4.3.2 JESD204B Test Patterns There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J40 supports a clock output-encoded test pattern, and a 12-octet RPAT. These test patterns can be enabled via an SPI register write and are located in the JESD digital page of the JESD bank. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 43 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.3.3 JESD204B Frame The JESD204B standard defines the following parameters: • • • • L is the number of lanes per link. M is the number of converters per device. F is the number of octets per frame clock period, per lane. S is the number of samples per frame per converter. Table 8-10 lists the available JESD204B formats and valid ranges for the ADS54J40 when the decimation filter is not used. The ranges are limited by the SERDES lane rate and the maximum ADC sample frequency. Note 16-bit data going to JESD 8b/10b encoder is formed by padding two 0s as LSBs into the 14-bit ADC data. Table 8-10. Default Interface Rates MINIMUM RATES MAXIMUM RATES L M F S DECIMATION SAMPLING RATE (MSPS) SERDES BIT RATE (Gbps) SAMPLING RATE (MSPS) SERDES BIT RATE (Gbps) 4 2 1 1 Not used 250 2.5 1000 10.0 4 2 4 4 Not used 250 2.5 1000 10.0 8 2 2 4 Not used 500 2.5 1000 5.0 Note In the LMFS = 8224 row of Table 8-10, the sample order in lane DA2 and DA3 are swapped. The detailed frame assembly is shown in Table 8-11. Table 8-11. Default Frame Assembly PIN LMFS = 4211 LMFS = 4244 LMFS = 8224 DA0 A3[7:0] DA1 A0[7:0] A2[15:8] A2[7:0] A3[15:8] A3[7:0] A2[15:8] A2[7:0] DA2 A0[15:8] A0[15:8] A0[7:0] A1[15:8] A1[7:0] A0[15:8] A0[7:0] DA3 A1[15:8] A1[7:0] DB0 B3[15:8] B3[7:0] DB1 B0[7:0] B2[15:8] B2[7:0] B3[15:8] B3[7:0] B2[15:8] B2[7:0] DB2 B0[15:8] B0[15:8] B0[7:0] B1[15:8] B1[7:0] B0[15:8] B0[7:0] B1[15:8] B1[7:0] DB3 44 A3[15:8] Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.3.4 JESD204B Frame Assembly with Decimation Table 8-12 lists the available JESD204B formats and valid ranges for the ADS54J40 when enabling the decimation filter. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency. Table 8-13 lists the detailed frame assembly with different decimation options. Table 8-12. Interface Rates with Decimation Filter MINIMUM RATES MAXIMUM RATES DEVICE CLOCK FREQUENCY (MSPS) OUTPUT SAMPLE RATE (MSPS) SERDES BIT RATE (Gbps) DEVICE CLOCK FREQUENCY (MSPS) OUTPUT SERDES BIT SAMPLE RATE RATE (Gbps) (MSPS) L M F S DECIMATION 4 4 2 1 4X (IQ) 500 125 2.5 1000 250 4 2 2 2 2X 500 250 2.5 1000 500 5.0 2 2 4 2 2X 300 150 3 1000 500 10.0 2 2 2 1 4X 500 125 2.5 1000 250 5.0 2 4 4 1 4X (IQ) 300 75 3 1000 250 10.0 1 2 4 1 4X 300 75 3 1000 250 10.0 5.0 Table 8-13. Frame Assembly with Decimation Filter PIN LMFS = 4222, 2X DECIMATION DA0 A1 [15:8] A1 [7:0] DA1 A0 [15:8] A0 [7:0] DB0 B1 [15:8] B1 [7:0] DB1 B0 [15:8] B0 [7:0] LMFS = 2242, 2X DECIMATION A0 [15:8] A0 [7:0] A1 [15:8] A1 [7:0] LMFS = 2221, 4X DECIMATION A0 [15:8] A0 [7:0] LMFS = 2441, 4X DECIMATION (IQ) AI0 [15:8] AI0 [7:0] AQ0 AQ0 [15:8] [7:0] LMFS = 4421, 4X DECIMATION (IQ) AQ0 [15:8] AQ0 [7:0] AI0 [15:8] AI0 [7:0] BQ0 [15:8] BQ0 [7:0] BI0 [15:8] BI0 [7:0] LMFS = 1241, 4X DECIMATION A0 [15:8] A0 [7:0] B0 [15:8] B0 [7:0] DA2 DA3 B0 [15:8] B0 [7:0] B1 [15:8] B1 [7:0] B0 [15:8] B0 [7:0] BI0 [15:8] BI0 [7:0] BQ0 BQ0 [15:8] [7:0] DB2 DB3 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 45 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 8-14. Program Summary of DDC Modes and JESD Link Configuration LMFS OPTIONS DDC MODES PROGRAMMING L M F S DEC DECIMATI MODE EN, ON DECFIL OPTIONS EN(1) 4 2 1 1 No decimation 4 2 4 4 JESD LINK (LMFS) PROGRAMMING DA_BUS_ DB_BUS_ BUS_REO BUS_REO LANE REORDER REORDER RDER RDER SHARE(6) (7) (8) EN1(9) EN2(10) DECFIL MODE[3:0](2) JESD FILTER(3) JESD MODE(4) JESD PLL MODE(5) 00 00 000 100 10 0 00h 00h 0 0 No decimation 00 00 000 010 10 0 00h 00h 0 0 8 2 2 4 No decimation (default after reset) 00 00 000 001 00 0 00h 00h 0 0 4 4 2 1 4X (IQ) 11 0011 (LPF with fS / 4 mixer) 111 001 00 0 0Ah 0Ah 1 1 4 2 2 2 2X 11 0010 (LPF) or 0110 (HPF) 110 001 00 0 0Ah 0Ah 1 1 2 2 4 2 2X 11 0010 (LPF) or 0110 (HPF) 110 010 10 0 0Ah 0Ah 1 1 100 001 00 0 0Ah 0Ah 1 1 2 2 2 1 4X 11 0000, 0100, 1000, or 1100 (all BPFs with different center frequencies). 2 4 4 1 4X (IQ) 11 0011 (LPF with an fS / 4 mixer) 111 010 10 0 0Ah 0Ah 1 1 11 0000, 0100, 1000, or 1100 (all BPFs with different center frequencies) 100 010 10 1 0Ah 0Ah 1 1 1 2 4 1 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) 4X The DEC MODE EN and DECFIL EN register bits are located in the main digital page, register 04Dh (bit 3) and register 041h (bit 4). The DECFIL MODE[3:0] register bits are located in the main digital page, register 041h (bits 5 and 2-0). The JESD FILTER register bits are located in the JESD digital page, register 001h (bits 5-3). The JESD MODE register bits are located in the JESD digital page, register 001h (bits 2:0). The JESD PLL MODE register bits are located in the JESD analog page, register 016h (bits 1-0). The LANE SHARE register bit is located in the JESD digital page, register 016h (bit 4). The DA_BUS_REORDER register bits are located in the JESD digital page, register 031h (bits 7-0). The DB_BUS_REORDER register bits are located in the JESD digital page, register 032h (bits 7-0). The BUS_REORDER EN1 register bit is located in the main digital page, register 052h (bit 7). The BUS_REORDER EN2 register bit is located in the main digital page, register 072h (bit 3). 8.4.3.4.1 JESD Transmitter Interface Each of the 10-Gbps SERDES JESD transmitter outputs requires ac coupling between the transmitter and receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in Figure 8-22. 0.1 PF DA[3:0]P, DB[3:0]P R t = ZO Transmission Line, Zo VCM Receiver R t = ZO DA[3:0]M, DB[3:0]M 0.1 PF Figure 8-22. Output Connection to Receiver 46 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.4.3.4.2 Eye Diagrams Figure 8-23 to Figure 8-26 show the serial output eye diagrams of the ADS54J40 at 5.0 Gbps and 10 Gbps with default and increased output voltage swing against the JESD204B mask. Figure 8-23. Eye at 5-Gbps Bit Rate with Default Output Swing Figure 8-24. Eye at 5-Gbps Bit Rate with Increased Output Swing Figure 8-25. Eye at 10-Gbps Bit Rate with Default Output Swing Figure 8-26. Eye at 10-Gbps Bit Rate with Increased Output Swing Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 47 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5 Register Maps Figure 8-27 shows a conceptual diagram of the serial registers. Initiate an SPI Cycle R/W, M, P, CH, Bits Decoder M=0 Analog Bank General Register (Address 00h, Keep M = 0, P = 0) Analog Bank Page Selection (Address 011h, Keep M = 0, P = 0) Value 80h Addr 20h Keep M = 0, P = 0 Addr 59h JESD Bank JESD Bank Page Selection (Address 003h and Address 004h, Keep M = 1, P = 0) General Register (Address 005h, Keep M = 1, P = 0) Value 6800h Value 0Fh Addr 0h Addr 5Fh Master Page (PDN, OVR, DC Coupling) M=1 Unused Registers (Address 01h, Address 02h. Keep M = 1, P = 0) Value 6900h Main Digital Page ADC Page (Fast OVR) Addr F7h Keep M = 1, P=1 (JESD Configuration) Addr 32h Value 6100h Keep M = 1, P=1 JESD Bank Page Selection1 (Address 001h and Address 002h, Keep M = 1, P = 0) JESD Analog Page (PLL Configuration, Output Swing, Pre-Emphasis) JESD Digital Page (Nyquist Zone, Gain, OVR, Filter) Keep M = 0, P = 0 Value 6A00h Addr 12h Addr 0h Addr 1Bh Value 0500h Value 0000h Addr 68h Addr 00h Offset Read Page (Freeze, Bypass and read internal estimate of DC Offset correction block) Keep M = 1, P=1 Addr 7Bh Keep M = 1, P=1 R/W=0/1(1) Offset Load Page (Load external estimate into DC Offset correction block) Keep M = 1, P=1 Addr 0Dh Figure 8-27. Serial Interface Registers The ADS54J40 contains two main SPI banks. The analog SPI bank gives access to the ADC analog blocks and the digital SPI bank controls the interleaving engine and anything related to the JESD204B serial interface. The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into three pages (main digital, JESD digital, and JESD analog). Table 8-15 lists a register map for the ADS54J40. 48 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 8-15. Register Map REGISTER ADDRESS REGISTER DATA(1) A[11:0] (Hex) 7 6 5 RESET 0 0 4 3 2 1 0 0 0 0 0 RESET 0 0 DISABLE BROADCAST 0 0 GENERAL REGISTERS 0 1 JESD BANK PAGE SEL1[7:0] 2 JESD BANK PAGE SEL1[15:8] 3 JESD BANK PAGE SEL[7:0] 4 JESD BANK PAGE SEL[15:8] 5 0 0 0 0 11 0 ANALOG BANK PAGE SEL MASTER PAGE (80h) 20 PDN ADC CHA 21 PDN ADC CHB PDN BUFFER CHB PDN BUFFER CHA 23 0 0 PDN ADC CHA 24 PDN ADC CHB PDN BUFFER CHB PDN BUFFER CHA 0 0 0 0 26 GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0 4F 0 0 0 0 0 0 0 EN INPUT DC COUPLING 53 0 0 0 0 0 0 EN SYSREF DC COUPLING SET SYSREF 54 ENABLE MANUAL SYSREF 0 MASK SYSREF MASK SYSREF 0 0 0 0 55 0 0 0 PDN MASK 0 0 0 0 59 FOVR CHB 0 ALWAYS WRITE 1 0 0 0 0 0 0 0 PULSE RESET ADC PAGE (0Fh) 5F FOVR THRESHOLD PROG MAIN DIGITAL PAGE (6800h) 0 0 0 0 0 40 0 IL ENGINE MODE 41 0 0 DECFIL MODE[3] DECFIL EN 0 DECFIL MODE[2:0] 42 0 0 0 0 0 NYQUIST ZONE 43 0 0 0 0 0 0 0 FORMAT SEL Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 49 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 8-15. Register Map (continued) REGISTER ADDRESS REGISTER DATA(1) A[11:0] (Hex) 7 44 0 6 5 4 4B 0 0 FORMAT EN 0 4D 0 0 0 4E CTRL NYQUIST 0 52 BUS_ REORDER EN1 0 3 2 1 0 0 CTRL IL ENGINE MODE 0 0 0 DEC MODE EN 0 0 CTRL FREEZE IL ENGINE IMPROVE IL PERF 0 0 0 0 0 0 0 0 0 0 DIG GAIN EN DIGITAL GAIN 68 0 FREEZE IL ENGINE 0 72 0 0 0 0 BUS_ REORDER EN2 0 0 0 0 AB 0 0 0 0 0 0 AD 0 0 0 0 0 0 LSB SEL EN F7 0 0 0 0 0 0 0 DIG RESET 0 TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN TX LINK DIS LSB SELECT JESD DIGITAL PAGE (6900h) 0 CTRL K 0 1 SYNC REG SYNC REG EN JESD FILTER LINK LAYER TESTMODE LINK LAYER RPAT 2 3 FORCE LMFC COUNT 5 SCRAMBLE EN JESD MODE LMFC MASK RESET 0 0 LMFC COUNT INIT 0 0 0 RELEASE ILANE SEQ 0 0 0 0 0 6 0 0 0 7 0 0 0 0 SUBCLASS FRAMES PER MULTI FRAME (K) 0 0 0 16 ALWAYS WRITE 1 0 0 LANE SHARE 0 0 0 0 31 DA_BUS_REORDER[7:0] 32 DB_BUS_REORDER[7:0] JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h) 50 12 SEL EMP LANE 1 ALWAYS WRITE 1 0 13 SEL EMP LANE 0 0 0 14 SEL EMP LANE 2 0 0 15 SEL EMP LANE 3 0 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 8-15. Register Map (continued) REGISTER ADDRESS REGISTER DATA(1) A[11:0] (Hex) 7 6 5 4 3 2 16 0 0 0 0 0 0 17 0 PLL RESET LANE PDN 1 0 LANE PDN 0 0 0 0 1A 0 0 0 0 0 0 FOVR CHA 0 0 FOVR CHA EN 0 0 0 1B JESD SWING 1 0 JESD PLL MODE OFFSET READ PAGE (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) 68 FREEZE CORR DC OFFSET CORR BW 69 0 0 74 75 0 0 0 0 BYPASS CORR ALWAYS WRITE 1 0 0 0 0 0 0 EXT CORR EN 0 0 0 ADC0_CORR_INT_EST[10:8] 0 0 0 ADC1_CORR_INT_EST[10:8] 0 ADC2_CORR_INT_EST[10:8] 0 ADC3_CORR_INT_EST[10:8] 0 ADC0_CORR_INT_EST[10:8] 0 ADC1_CORR_INT_EST[10:8] 0 ADC2_CORR_INT_EST[10:8] ADC2_CORR_INT_EST[7:0] 0 0 0 0 7A 7B DC OFFSET CORR BW ADC1_CORR_INT_EST[7:0] 78 79 DC OFFSET CORR BW ADC0_CORR_INT_EST[7:0] 76 77 DC OFFSET CORR BW 0 0 ADC3_CORR_INT_EST[7:0] 0 0 OFFSET LOAD PAGE (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0500h) 00 01 ADC0_LOAD_INT_EST[7:0] 0 0 04 05 0 0 08 09 0 0 0 ADC2_LOAD_INT_EST[7:0] 0 0 0C (1) 0 ADC1_LOAD_INT_EST[7:0] 0 0 ADC3_LOAD_INT_EST[7:0] 0D 0 0 0 0 0 ADC3_CORR_INT_EST[10:8] 78h 0 0 0 0 0 IL ENGINE FREEZE SECONDARY CONTROL X = Don't care Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 51 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.1 Example Register Writes This section provides three different example register writes. Table 8-16 describes a global power-down register write, Table 8-17 describes the register writes when the default lane setting (eight active lanes per device) is changed to four active lanes (LMFS = 4211), and Table 8-18 describes the register writes for 2X decimation with four active lanes (LMFS = 4222). Table 8-16. Global Power Down ADDRESS (Hex) DATA (Hex) 0-011h 80h Set the master page COMMENT 0-026h C0h Set the global power-down Table 8-17. Two Lanes per Channel Mode (LMFS = 4211) ADDRESS (Hex) DATA (Hex) COMMENT 4-004h 69h Select the JESD digital page 4-003h 00h Select the JESD digital page 6-001h 02h Select the digital to 40X mode 4-004h 6Ah Select the JESD analog page 6-016h 02h Set the SERDES PLL to 40X mode Table 8-18. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222) ADDRESS (Hex) DATA (Hex) 4-004h 68h Select the main digital page (6800h) COMMENT 4-003h 00h Select the main digital page (6800h) 6-041h 12h Set decimate-by-2 (low-pass filter) 6-04Dh 08h Enable decimation filter control 6-072h 08h BUS_REORDER EN2 6-052h 80h BUS_REORDER EN1 6-000h 01h 6-000h 00h 4-004h 69h Select the JESD digital page (6900h) 4-003h 00h Select the JESD digital page (6900h) 6-031h 0Ah Output bus reorder for channel A 6-032h 0Ah Output bus reorder for channel B 6-001h 31h Program the JESD MODE and JESD FILTER register bits for LMFS = 4222. Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect). Table 8-19 lists the access codes for the ADS54J40 registers. Table 8-19. ADS54J40 Access Type Codes Access Type Code Description R R Read R-W R/W Read or write W W Write -n 52 Value after reset or the default value Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2 Register Descriptions 8.5.2.1 General Registers 8.5.2.1.1 Register 0h (address = 0h) Figure 8-22. Register 0h 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 RESET W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h Table 8-20. Register 0h Field Descriptions Bit 7 6-1 0 Field Type Reset Description RESET W 0h 0 = Normal operation 1 = Internal software reset, clears back to 0 0 W 0h Must write 0 RESET W 0h 0 = Normal operation 1 = Internal software reset, clears back to 0 8.5.2.1.2 Register 1h (address = 1h) Figure 8-23. Register 1h 7 6 5 4 3 2 1 0 JESD BANK PAGE SEL1[7:0] R/W-0h Table 8-21. Register 1h Field Descriptions Bit Field Type Reset Description 7-0 JESD BANK PAGE SEL1[7:0] R/W 0h Program these bits to access the desired page in the JESD bank. 0000h = OFFSET READ Page 0500h = OFFSET LOAD Page 8.5.2.1.3 Register 2h (address = 2h) Figure 8-24. Register 2h 7 6 5 4 3 2 1 0 JESD BANK PAGE SEL1[15:8] R/W-0h Table 8-22. Register 2h Field Descriptions Bit Field Type Reset Description 7-0 JESD BANK PAGE SEL1[15:8] R/W 0h Program these bits to access the desired page in the JESD bank. 0000h = OFFSET READ Page 0500h = OFFSET LOAD Page 8.5.2.1.4 Register 3h (address = 3h) Figure 8-25. Register 3h 7 6 5 4 3 2 1 0 JESD BANK PAGE SEL[7:0] R/W-0h Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 53 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 8-23. Register 3h Field Descriptions Bit Field Type Reset Description 7-0 JESD BANK PAGE SEL[7:0] R/W 0h Program these bits to access the desired page in the JESD bank. 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected 6100h = OFFSET READ or LOAD Page 8.5.2.1.5 Register 4h (address = 4h) Figure 8-26. Register 4h 7 6 5 4 3 2 1 0 JESD BANK PAGE SEL[15:8] R/W-0h Table 8-24. Register 4h Field Descriptions 54 Bit Field Type Reset Description 7-0 JESD BANK PAGE SEL[15:8] R/W 0h Program these bits to access the desired page in the JESD bank. 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected 6100h = OFFSET READ or LOAD Page Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.1.6 Register 5h (address = 5h) Figure 8-27. Register 5h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DISABLE BROADCAST W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-25. Register 5h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 DISABLE BROADCAST R/W 0h 0 = Normal operation. Channel A and B are programmed as a pair. 1 = Channel A and B can be individually programmed based on the CH bit. 0 8.5.2.1.7 Register 11h (address = 11h) Figure 8-28. Register 11h 7 6 5 4 3 2 1 0 ANALOG PAGE SELECTION R/W-0h Table 8-26. Register 11h Field Descriptions Bit Field Type Reset Description 7-0 ANALOG BANK PAGE SEL R/W 0h Program these bits to access the desired page in the analog bank. Master page = 80h ADC page = 0Fh 8.5.2.2 Master Page (080h) Registers 8.5.2.2.1 Register 20h (address = 20h), Master Page (080h) Figure 8-29. Register 20h 7 6 5 4 3 2 1 PDN ADC CHA PDN ADC CHB R/W-0h R/W-0h 0 Table 8-27. Registers 20h Field Descriptions Bit Field Type Reset Description There are two power-down masks that are controlled through the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register bit 5 in address 26h. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. 0Fh = Power-down CHB only. F0h = Power-down CHA only. FFh = Power-down both. 7-4 PDN ADC CHA R/W 0h 3-0 PDN ADC CHB R/W 0h Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 55 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.2.2 Register 21h (address = 21h), Master Page (080h) Figure 8-30. Register 21h 7 6 5 4 3 2 1 0 PDN BUFFER CHB PDN BUFFER CHA 0 0 0 0 R/W-0h R/W-0h W-0h W-0h W-0h W-0h Table 8-28. Register 21h Field Descriptions Bit Field Type Reset Description 7-6 PDN BUFFER CHB R/W 0h 5-4 PDN BUFFER CHA R/W 0h There are two power-down masks that are controlled through the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. There are two buffers per channel. One buffer drives two ADC cores. PDN BUFFER CHx: 00 = Both buffers of a channel are active. 11 = Both buffers are powered down. 01–10 = Do not use. 3-0 0 W 0h Must write 0. 8.5.2.2.3 Register 23h (address = 23h), Master Page (080h) Figure 8-31. Register 23h 7 6 5 4 3 2 1 PDN ADC CHA PDN ADC CHB R/W-0h R/W-0h 0 Table 8-29. Register 23h Field Descriptions 56 Bit Field 7-4 PDN ADC CHA 3-0 PDN ADC CHB Type Reset Description R/W 0h R/W 0h There are two power-down masks that are controlled through the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. 0Fh = Power-down CHB only. F0h = Power-down CHA only. FFh = Power-down both. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.2.4 Register 24h (address = 24h), Master Page (080h) Figure 8-32. Register 24h 7 6 5 4 3 2 1 0 PDN BUFFER CHB PDN BUFFER CHA 0 0 0 0 R/W-0h R/W-0h W-0h W-0h W-0h W-0h Table 8-30. Register 24h Field Descriptions Bit Field Type Reset Description 7-6 PDN BUFFER CHB R/W 0h 5-4 PDN BUFFER CHA R/W 0h There are two power-down masks that are controlled through the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h. Power-down mask 2: addresses 23h and 24h. There are two buffers per channel. One buffer drives two ADC cores. PDN BUFFER CHx: 00 = Both buffers of a channel are active. 11 = Both buffers are powered down. 01–10 = Do not use. 3-0 0 W 0h Must write 0. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 57 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.2.5 Register 26h (address = 26h), Master Page (080h) Table 8-31. Register 26h 7 6 5 4 3 2 1 0 GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0 R/W-0h R/W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h Table 8-32. Register 26h Field Descriptions Bit Field Type Reset Description 7 GLOBAL PDN R/W 0h Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be programmed. 0 = Normal operation 1 = Global power-down through the SPI 6 OVERRIDE PDN PIN R/W 0h This bit ignores the power-down pin control. 0 = Normal operation 1 = Ignores inputs on the power-down pin 5 PDN MASK SEL R/W 0h This bit selects power-down mask 1 or mask 2. 0 = Power-down mask 1 1 = Power-down mask 2 0 W 0h Must write 0 4-0 8.5.2.2.6 Register 4Fh (address = 4Fh), Master Page (080h) Table 8-33. Register 4Fh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EN INPUT DC COUPLING W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-34. Register 4Fh Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 EN INPUT DC COUPLING R/W 0h The device has an internal biassing resistor of 600 Ω from VCM to the INP and INM pins. A small common-mode current flows through these resistors causing approximately a 100-mV drop. To compenste for the drop, the device raises the VCM voltage by 100-mV by default. This compensation is particularly helpful in AC-coupling applications where the common-mode voltage on the INP and INM pins is established by internal biasing resistors. In DC-coupling applications, because the common-mode voltage is established by an external circuit, there is no need to raise VCM by 100-mV. 0 = Device raises VCM voltage by 100 mV, useful in ACcoupling applications 1 = Device does not raise the VCM voltage, useful in DCcoupling applications. 0 58 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.2.7 Register 53h (address = 53h), Master Page (080h) Table 8-35. Register 53h 7 6 5 4 3 2 1 0 SET SYSREF R/W-0h 0 0 0 0 0 0 EN SYSREF DC COUPLING W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-36. Register 53h Field Descriptions Bit Field Type Reset Description 7:2 0 W 0h Must write 0 1 EN SYSREF DC COUPLING R/W 0h This bit enables a higher common-mode voltage input on the SYSREF signal (up to 1.6 V). 0 = Normal operation 1 = Enables a higher SYSREF common-mode voltage support 0 MANUAL SYSREF R/W 0h The device has a feature to apply the SYSREF signal manually through the serial interface instead of the SYSREFP, SYSREFM pins. This application can be done by first setting the ENABLE MANUAL SYSREF register bit, then using the MANUAL SYSREF bit to set the SYSREF signal high or low.0 = Set SYSREF low 1 = Set SYSREF high 8.5.2.2.8 Register 54h (address = 54h), Master Page (080h) Figure 8-33. Register 54h 7 6 ENABLE MANUAL SYSREF 0 R/W-0h W-0h 5 4 MASK SYSREF MASK SYSREF W-0h R/W-0h 3 2 1 0 0 0 0 0 W-0h W-0h W-0h W-0h Table 8-37. Register 54h Field Descriptions Bit Field Type Reset Description 7 ENABLE MANUAL SYSREF R/W 0h This bit enables manual SYSREF 6 0 W 0h Must write 0 5-4 MASK SYSREF R/W 0h 00 = Normal operation 11 = The SYSREF signal is ignored by the device irrespective of how the signal was applied (through a pin or manually by the serial interface) 01 and 10 = Not applicable 3-0 0 W 0h Must write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 59 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.2.9 Register 55h (address = 55h), Master Page (080h) Table 8-38. Register 55h 7 6 5 4 3 2 1 0 0 0 0 PDN MASK 0 0 0 0 W-0h W-0h W-0h R/W-0h W-0h W-0h W-0h W-0h Table 8-39. Register 55h Field Descriptions Bit Field Type Reset Description 7-5 0 W 0h Must write 0 PDN MASK R/W 0h This bit enables power-down via a register bit. 0 = Normal operation 1 = Power-down is enabled by powering down the internal blocks as specified in the selected power-down mask 0 W 0h Must write 0 4 3-0 60 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h) Figure 8-34. Register 59h 7 6 5 4 3 2 1 0 FOVR CHB 0 ALWAYS WRITE 1 0 0 0 0 0 W-0h W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h Table 8-40. Register 59h Field Descriptions Bit Field Type Reset Description 7 FOVR CHB W 0h This bit outputs the FOVR signal for channel B on the SDOUT pin. 0 = Normal operation 1 = The FOVR signal is available on the SDOUT pin 6 0 W 0h Must write 0 5 ALWAYS WRITE 1 R/W 0h Must write 1 0 W 0h Must write 0 4-0 8.5.2.3 ADC Page (0Fh) Register 8.5.2.3.1 Register 5F (addresses = 5F), ADC Page (0Fh) Figure 8-35. Register 5F 7 6 5 4 3 2 1 0 FOVR THRESHOLD PROG R/W-E3h Table 8-41. Register 5F Field Descriptions Bit Field Type Reset Description 7-0 FOVR THRESHOLD PROG R/W E3h Program the fast OVR thresholds together for channel A and B, as described in the Overrange Indication section. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 61 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4 Main Digital Page (6800h) Registers 8.5.2.4.1 Register 0h (address = 0h), Main Digital Page (6800h) Table 8-42. Register 0h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PULSE RESET W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-43. Register 0h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 PULSE RESET R/W 0h This bit must be pulsed after power-up or after configuring registers in the main digital page of the JESD bank. Any register bits in the main digital page (6800h) take effect only after this bit is pulsed; see the Start-Up Sequence section for the correct sequence. 0 = Normal operation 0 → 1 → 0 = This bit is pulsed 0 8.5.2.4.2 Register 40h (address = 40h), Main Digital Page (6800h) Table 8-44. Register 40h 7 6 5 4 3 2 1 0 IL ENGINE MODE W-0h Table 8-45. Register 40h Field Descriptions 62 Bit Field Type Reset Description 7-0 IL ENGINE MODE W 0h Specifies the Interleaving Engine Mode 0 = Interleaving Engine is enabled 8 = Interleaving Engine is disabled Other Values = Reserved Note that for this register setting to take effect, CTRL IL ENGINE field should be set to 1 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.3 Register 41h (address = 41h), Main Digital Page (6800h) Figure 8-36. Register 41h 7 6 5 4 3 0 0 DECFIL MODE[3] DECFIL EN 0 2 DECFIL MODE[2:0] 1 W-0h W-0h R/W-0h R/W-0h W-0h R/W-0h 0 Table 8-46. Register 41h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0 5 DECFIL MODE[3] R/W 0h This bit selects the decimation filter mode. Table 8-47 lists the bit settings. The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled. 4 DECFIL EN R/W 0h This bit enables the digital decimation filter. 0 = Normal operation, full rate output 1 = Digital decimation enabled 3 0 W 0h Must write 0 DECFIL MODE[2:0] R/W 0h These bits select the decimation filter mode. Table 8-47 lists the bit settings. The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled. 2-0 Table 8-47. DECFIL MODE Bit Settings BITS (5, 2-0) FILTER MODE DECIMATION 0000 Band-pass filter centered on 3 × fS / 16 4X 0100 Band-pass filter centered on 5 × fS / 16 4X 1000 Band-pass filter centered on 1 × fS / 16 4X 1100 Band-pass filter centered on 7 × fS / 16 4X 0010 Low-pass filter 2X 0110 High-pass filter 2X 0011 Low-pass filter with fS /4 mixer 4X (IQ) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 63 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.4 Register 42h (address = 42h), Main Digital Page (6800h) Table 8-48. Register 42h 7 6 5 4 3 0 0 0 0 0 2 NYQUIST ZONE 1 W-0h W-0h W-0h W-0h W-0h R/W-0h 0 Table 8-49. Register 42h Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 2-0 NYQUIST ZONE R/W 0h The Nyquist zone must be selected for proper interleaving correction. The CONTROL NYQUIST register bit (register 4Eh, bit 7) must be enabled to use these bits. 000 = 1st Nyquist zone (0 MHz to 500 MHz) 001 = 2nd Nyquist zone (500 MHz to 1000 MHz) 010 = 3rd Nyquist zone (1000 MHz to 1500 MHz) All others = Not used 8.5.2.4.5 Register 43h (address = 43h), Main Digital Page (6800h) Figure 8-37. Register 43h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FORMAT SEL W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-50. Register 43h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 FORMAT SEL R/W 0h This bit changes the output format. Set the FORMAT EN bit to enable control using this bit. 0 = Twos complement 1 = Offset binary 0 8.5.2.4.6 Register 44h (address = 44h), Main Digital Page (6800h) Figure 8-38. Register 44h 7 6 5 4 3 0 DIGITAL GAIN R/W-0h R/W-0h 2 1 0 Table 8-51. Register 44h Field Descriptions Bit 7 6-0 64 Field Type Reset Description 0 R/W 0h Must write 0 DIGITAL GAIN R/W 0h These bits set the digital gain setting. The DIG GAIN EN register bit (register 52h, bit 0) must be enabled to use these bits. Gain in dB = 20log (digital gain / 32) 7Fh = 127 equals a digital gain of 9.5 dB Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.7 Register 4Bh (address = 4Bh), Main Digital Page (6800h) Figure 8-39. Register 4Bh 7 6 5 4 3 2 1 0 0 0 FORMAT EN 0 0 CTRL IL ENGINE MODE 0 0 W-0h W-0h R/W-0h W-0h W-0h R/W-0h W-0h W-0h Table 8-52. Register 4Bh Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0 FORMAT EN R/W 0h This bit enables control for data format selection using the FORMAT SEL register bit. 0 = Default, output is in twos complement format 1 = Output is in offset binary format after the FORMAT SEL bit is set 0 W oh Must write 0 CTRL IL ENGINE MODE R/W 0h This bit enables control of interleaving engine mode selection using the IL ENGINE Mode register field. 0 = Default. IL Engine Mode (IL Engine enabled) 1 = IL Engine Mode is determined from IL ENGINE MODE field setting. 0 W 0h Must write 0 5 4-3 2 1-0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 65 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.8 Register 4Dh (address = 4Dh), Main Digital Page (6800h) Figure 8-40. Register 4Dh 7 6 0 0 W-0h W-0h 5 4 0 W-0h 3 2 1 0 0 DEC MOD EN 0 0 CTRL FREEZE IL ENGINE W-0h R/W-0h W-0h W-0h R/W-0h Table 8-53. Register 4Dh Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0 DEC MOD EN R/W 0h This bit enables control of decimation filter mode through the DECFIL MODE[3:0] register bits. 0 = Default 1 = Decimation mode control is enabled 3 2-1 0 66 0 W 0h Must write 0 CTRL FREEZE IL ENGINE R/W 0h This bit enables control of interleaving engine freeze/unfreeze state using the FREEZE IL ENGINE register field. 0 = IL Engine continues in its current state (either frozen or unfrozen). 1 = IL Engine state enters a frozen or unfrozen state base on FREEZE IL ENGINE register field setting. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.9 Register 4Eh (address = 4Eh), Main Digital Page (6800h) Figure 8-41. Register 4Eh 7 6 5 4 3 2 1 0 CTRL NYQUIST 0 IMPROVE IL PERF 0 0 0 0 0 R/W-0h W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h Table 8-54. Register 4Eh Field Descriptions Bit Field Type Reset Description 7 CTRL NYQUIST R/W 0h This bit enables selecting the Nyquist zone using register 42h, bits 2-0. 0 = Selection disabled 1 = Selection enabled 6 0 W 0h Must write 0 5 IMPROVE IL PERF R/W 0h Improves interleaving performance. Effective only for input frequencies that are within +/- fs / 64 band centered at n * fs / 8 (n = 1, 2, 3 or 4). For example, at a 1-Gsps sampling rate, this bit may improve IL performance when the input frequencies fall within +/- 15.625 MHz band located at 125 MHz, 250 MHz, 375 MHz and 500 MHz. 0 = Default 1 = Improves IL performance for certain input frequenies 0 W 0h Must write 0 6-0 8.5.2.4.10 Register 52h (address = 52h), Main Digital Page (6800h) Figure 8-42. Register 52h 7 6 5 4 3 2 1 0 BUS_REORD ER_EN1 0 0 0 0 0 0 DIG GAIN EN R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-55. Register 52h Field Descriptions Bit 7 6-1 0 Field Type Reset Description BUS_REORDER_EN1 R/W 0h Must write 1 in DDC mode only 0 W 0h Must write 0 DIG GAIN EN R/W 0h Enables selecting the digital gain for register 44h. 0 = Digital gain disabled 1 = Digital gain enabled Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 67 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.11 Register 68h (address = 68h), Main Digital Page (6800h) Figure 8-43. Register 68h 7 6 5 4 3 2 1 0 0 FREEZE IL ENGINE 0 W-0h W-0h W-0h Table 8-56. Register 68h Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 FREEZE IL ENGINE W 0h IL Engine Freeze/Unfreeze Configuration. 0 = IL Engine is unfrozen (i.e. Interleaving Mismatch estimation is resumed) 1 = IL Engine is frozen (i.e. Interleaving Mismatch estimation is frozen, correction continues with estimates computed prior to freeze) Note 1. Value specified here takes effect when CTRL FREEZE IL ENGINE is 1. 2. For IL Engine to be frozen, register field IL ENGINE FREEZE SECONDARY CONTROL should be set to 0 3. Unlike other register fields in the Main Digital Page, FREEZE IL ENGINE does not need a PULSE RESET to take effect. FREEZE IL ENGINE can be asserted/deasserted at any time and the setting takes effect immediatel 2 . 1-0 0 W 0h Must write 0 8.5.2.4.12 Register 72h (address = 72h), Main Digital Page (6800h) Figure 8-44. Register 72h 7 6 5 4 3 2 1 0 0 0 0 0 BUS_REORDER_EN2 0 0 0 W-0h W-0h W-0h W-0h R/W-0h W-0h W-0h W-0h Table 8-57. Register 72h Field Descriptions Bit Field 7-4 0 W 0h Must write 0 BUS_REORDER_EN2 R/W 0h Must write a 1 in DDC mode only 0 W 0h Must write 0 3 2-0 68 Type Reset Description Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.4.13 Register ABh (address = ABh), Main Digital Page (6800h) Figure 8-45. Register ABh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LSB SEL EN W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-58. Register ABh Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 LSB SEL EN R/W 0h Enable control for the LSB SELECT register bit. 0 = Default 1 = LSB of the 16-bit data (14-bit ADC data padded with two 0s as the LSBs) can be programmed as fast OVR using the LSB SELECT register bit. 0 8.5.2.4.14 Register ADh (address = ADh), Main Digital Page (6800h) Figure 8-46. Register ADh 7 6 5 4 3 2 0 0 0 0 0 0 1 LSB SELECT 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-59. Register ADh Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1-0 LSB SELECT R/W 0h These bits enable the output of the FOVR flag instead of the output data LSB. Ensure that LSB SEL EN register bit is set to 1. 00 = Output is 16-bit data (14-bit ADC data padded with two 0s as LSBs) 11 = LSB of 16-bit output data is replaced by the FOVR information for each channel. 8.5.2.4.15 Register F7h (address = F7h), Main Digital Page (6800h) Figure 8-47. Register F7h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DIG RESET W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h Table 8-60. Register F7h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 DIG RESET W 0h This bit is the self-clearing reset for the digital block and does not include interleaving correction. 0 = Normal operation 1 = Digital reset 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 69 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.5 JESD Digital Page (6900h) Registers 8.5.2.5.1 Register 0h (address = 0h), JESD Digital Page (6900h) Figure 8-48. Register 0h 7 6 5 CTRL K 0 0 R/W-0h W-0h W-0h 4 3 2 1 0 TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN TX LINK DIS R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 8-61. Register 0h Field Descriptions Bit Field Type Reset Description CTRL K R/W 0h Thib bit is the enable bit for a number of frames per multi frame. 0 = Default is five frames per multi frame 1 = Frames per multi frame can be set in register 06h 0 W 0h Must write 0 4 TESTMODE EN R/W 0h This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled 3 FLIP ADC DATA R/W 0h 0 = Normal operation 1 = Output data order is reversed: MSB to LSB. 2 LANE ALIGN R/W 0h This bit inserts the lane alignment character (K28.3) for the receiver to align to lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts lane alignment characters 1 FRAME ALIGN R/W 0h This bit inserts the lane alignment character (K28.7) for the receiver to align to lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts frame alignment characters 0 TX LINK DIS R/W 0h This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-asserted. 0 = Normal operation 1 = ILA disabled 7 6-5 70 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.5.2 Register 1h (address = 1h), JESD Digital Page (6900h) Figure 8-49. Register 1h 7 6 5 SYNC REG SYNC REG EN JESD FILTER 4 3 2 JESD MODE 1 R/W-0h R/W-0h R/W-0h R/W-01h 0 Table 8-62. Register 1h Field Descriptions Bit Field Type Reset Description 7 SYNC REG R/W 0h This bit is the register control for the sync request. 0 = Normal operation 1 = ADC output data are replaced with K28.5 characters; the SYNC REG EN register bit must also be set to 1 6 SYNC REG EN R/W 0h This bit enables register control for the sync request. 0 = Use the SYNC pin for sync requests 1 = Use the SYNC REG register bit for sync requests 5-3 JESD FILTER R/W 0h These bits and the JESD MODE bits set the correct LMFS configuration for the JESD interface. The JESD FILTER setting must match the configuration in the decimation filter page. 000 = Filter bypass mode See Table 8-63 for valid combinations for register bits JESD FILTER along with JESD MODE. 2-0 JESD MODE R/W 01h These bits select the number of serial JESD output lanes per ADC. The JESD PLL MODE register bit located in the JESD analog page must also be set accordingly. 001 = Default after reset(Eight active lanes) See Table 8-63 for valid combinations for register bits JESD FILTER along with JESD MODE. Table 8-63. Valid Combinations for JESD FILTER and JESD MODE Bits NUMBER OF ACTIVE LANES PER DEVICE REGISTER BIT JESD FILTER REGISTER BIT JESD MODE DECIMATION FACTOR 000 100 No decimation Four lanes are active 000 010 No decimation Four lanes are active 000 001 No decimation (default after reset) Eight lanes are active 111 001 4X (IQ) Four lanes are active 110 001 2X Four lanes are active 110 010 2X Two lanes are active 100 001 4X Two lanes are active 111 010 4X (IQ) Two lanes are active 100 010 4X One lane is active Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 71 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.5.3 Register 2h (address = 2h), JESD Digital Page (6900h) Figure 8-50. Register 2h 7 6 5 4 3 2 1 0 LINK LAYER TESTMODE LINK LAYER RPAT LMFC MASK RESET 0 0 0 R/W-0h R/W-0h R/W-0h W-0h W-0h W-0h Table 8-64. Register 2h Field Descriptions Bit Field Type Reset Description 7-5 LINK LAYER TESTMODE R/W 0h These bits generate a pattern as per section 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high-frequency jitter pattern) 010 = K28.5 (mixed-frequency jitter pattern) 011 = Repeat initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences) 100 = 12-octet RPAT jitter pattern All others = Not used 4 LINK LAYER RPAT R/W 0h This bit changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100). 0 = Normal operation 1 = Changes disparity 3 LMFC MASK RESET R/W 0h This bit masks the LMFC reset coming to the digital block. 0 = LMFC reset is not masked 1 = Ignore the LMFC reset request 0 W 0h Must write 0 2-0 72 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.5.4 Register 3h (address = 3h), JESD Digital Page (6900h) Figure 8-51. Register 3h 7 6 5 4 3 2 1 0 FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ R/W-0h R/W-0h R/W-0h Table 8-65. Register 3h Field Descriptions Bit Field Type Reset Description FORCE LMFC COUNT R/W 0h This bit forces the LMFC count. 0 = Normal operation 1 = Enables using a different starting value for the LMFC counter 6-2 LMFC COUNT INIT R/W 0h When SYSREF transmits to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the receiver can be synchronized early because it receives the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled. 1-0 RELEASE ILANE SEQ R/W 0h These bits delay the generation of the lane alignment sequence by 0, 1, 2, or 3 multi frames after the code group synchronization. 00 = 0 01 = 1 10 = 2 11 = 3 7 8.5.2.5.5 Register 5h (address = 5h), JESD Digital Page (6900h) Figure 8-52. Register 5h 7 6 5 4 3 2 1 0 SCRAMBLE EN 0 0 0 0 0 0 0 R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h Table 8-66. Register 5h Field Descriptions Bit 7 6-0 Field Type Reset Description SCRAMBLE EN R/W 0h This bit is the scramble enable bit in the JESD204B interface. 0 = Scrambling disabled 1 = Scrambling enabled 0 W 0h Must write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 73 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.5.6 Register 6h (address = 6h), JESD Digital Page (6900h) Figure 8-53. Register 6h 7 6 5 0 0 0 4 3 FRAMES PER MULTI FRAME (K) 2 1 W-0h W-0h W-0h R/W-8h 0 Table 8-67. Register 6h Field Descriptions Bit Field Type Reset Description 7-5 0 W 0h Must write 0 4-0 FRAMES PER MULTI FRAME (K) R/W 8h These bits set the number of multi frames. Actual K is the value in hex + 1 (that is, 0Fh is K = 16). 8.5.2.5.7 Register 7h (address = 7h), JESD Digital Page (6900h) Figure 8-54. Register 7h 7 6 5 4 3 2 1 0 0 0 0 0 SUBCLASS 0 0 0 W-0h W-0h W-0h W-0h R/W-1h W-0h W-0h W-0h Table 8-68. Register 7h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0 SUBCLASS R/W 1h This bit sets the JESD204B subclass. 000 = Subclass 0 is backward compatible with JESD204A 001 = Subclass 1 deterministic latency using the SYSREF signal 0 W 0h Must write 0 3 2-0 8.5.2.5.8 Register 16h (address = 16h), JESD Digital Page (6900h) Figure 8-55. Register 16h 7 6 5 4 3 2 1 0 1 0 0 LANE SHARE 0 0 0 0 W-1h W-0h W-0h R/W-0h W-0h W-0h W-0h W-0h Table 8-69. Register 16h Field Descriptions Bit Field Type Reset Description 7 1 W 1h Must write 1 6-5 0 W 0h Must write 0 LANE SHARE R/W 0h When using decimate-by-4, the data of both channels are output over one lane (LMFS = 1241). 0 = Normal operation (each channel uses one lane) 1 = Lane sharing is enabled, both channels share one lane (LMFS = 1241) 0 W 0h Must write 0 4 3-0 74 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.5.9 Register 31h (address = 31h), JESD Digital Page (6900h) Figure 8-56. Register 31h 7 6 5 4 3 2 1 0 DA_BUS_REORDER[7:0] R/W-0h Table 8-70. Register 31h Field Descriptions Bit Field Type Reset Description 7-0 DA_BUS_REORDER[7:0] R/W 0h Use these bits to program output connections between data streams and output lanes in decimate-by-2 and decimate-by-4 mode. Table 8-14 lists the supported combinations of these bits. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h) Figure 8-57. Register 32h 7 6 5 4 3 2 1 0 DB_BUS_REORDER[7:0] R/W-0h Table 8-71. Register 32h Field Descriptions Bit Field Type Reset Description 7-0 DB_BUS_REORDER[7:0] R/W 0h Use these bits to program output connections between data streams and output lanes in decimate-by-2 and decimate-by-4 mode. Table 8-14 lists the supported combinations of these bits. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 75 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.6 JESD Analog Page (6A00h) Registers 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h) TBD I separated this register since it is now different from the rest Figure 8-58. Register 12h 7 6 5 4 3 2 1 0 SEL EMP LANE 1 ALWAYS WRITE 1 0 R/W-0h W-0h W-0h Table 8-72. Register 12h Field Descriptions 76 Bit Field Type Reset Description 7-2 SEL EMP LANE 1, 0, 2, or 3 R/W 0h These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 000000 = 0 dB 000001 = –1 dB 000011 = –2 dB 000111 = –4.1 dB 001111 = –6.2 dB 011111 = –8.2 dB 111111 = –11.5 dB 1 ALWAYS WRITE 1 W 0h 1 = Always write 1 0 0 W 0h 0 = Must write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.6.2 Registers 13h-15h (addresses = 13h-5h), JESD Analog Page (6A00h) Figure 8-59. Register 13h 7 6 5 1 0 SEL EMP LANE 0 4 3 2 0 0 R/W-0h W-0h W-0h Figure 8-60. Register 14h 7 6 5 1 0 SEL EMP LANE 2 4 3 2 0 0 R/W-0h W-0h W-0h 1 0 Figure 8-61. Register 15h 7 6 5 4 3 2 SEL EMP LANE 3 0 0 R/W-0h W-0h W-0h Table 8-73. Registers 13h-15h Field Descriptions Bit Field 7-2 1-0 Type Reset Description SEL EMP LANE x (where x = 1, 0, 2, R/W or 3) 0h These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 000000 = 0 dB 000001 = –1 dB 000011 = –2 dB 000111 = –4.1 dB 001111 = –6.2 dB 011111 = –8.2 dB 111111 = –11.5 dB 0 0h Must write 0 W Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 77 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h) Figure 8-62. Register 16h 7 6 5 4 3 2 1 0 0 0 0 0 0 JESD PLL MODE 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-74. Register 16h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1-0 JESD PLL MODE R/W 0h These bits select the JESD PLL multiplication factor and must match the JESD MODE setting. 00 = 20X mode, four lanes per ADC 01 = Not used 10 = 40X mode, two lanes per ADC 11 = Not used Table 8-14 lists a programming summary of the DDC modes and JESD link configuration. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h) Figure 8-63. Register 17h 7 6 5 4 3 0 PLL RESET W-0h R/W-0h 2 1 0 LANE PDN 1 0 LANE PDN 0 0 0 0 R/W-0h W-0h R/W-0h W-0h W-0h W-0h Table 8-75. Register 17h Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6 PLL RESET R/W 0h Pulse this bit after powering up the device; see Table 9-1. 0 = Default 0 → 1 → 0 = The PLL RESET bit is pulsed. 5 LANE PDN 1 R/W 0h This bit powers down unused SERDES lanes DA0, DA3, DB0, and DB3 in certain LMFS settings (applicable for LMFS = 4244, 2242, 2441, 4211, and 2221). Powering down unused lanes puts the SERDES buffers in tri-state moe and saves approximately 15-mA current on the IOVDD supply. This bit must be used with LANE PDN 0 to take effect. 0 = Default 1 = DA0, DB0, DA3 and DB3 are powered down4 4 0 W 0h Must write 0 3 LANE PDN 0 R/W 0h This bit powers down unused SERDES lanes DA0, DA3, DB0, and DB3 in certain LMFS settings (applicable for LMFS = 4244, 2242, 2441, 4211, and 2221). Powering down unused lanes puts the SERDES buffers in tri-state moe and saves approximately 15-mA current on the IOVDD supply.This bit must be used with LANE PDN 1 to take effect. 0 = Dafult 1 = DA0, DB0, DA3 and DB3 are powered down4 0 W 0h Must write 0 2-0 78 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h) Figure 8-64. Register 1Ah 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FOVR CHA 0 W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h W-0h Table 8-76. Register 1Ah Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1 FOVR CHA R/W 0h This bit outputs the FOVR signal for channel A on the PDN pin. FOVR CHA EN (register 1Bh, bit 3) must be enabled for this bit to function. 0 = Normal operation 1 = The FOVR signal of channel A is available on the PDN pin 0 0 W 0h Must write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 79 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h) Figure 8-65. Register 1Bh 7 6 5 4 3 2 1 0 JESD SWING 0 FOVR CHA EN 0 0 0 R/W-0h W-0h R/W-0h W-0h W-0h W-0h Table 8-77. Register 1Bh Field Descriptions Bit Field Type Reset Description 7-5 JESD SWING R/W 0h These bits select the output amplitude VOD (mVPP) of the JESD transmitter (for all lanes). 0 = 860 mVPP 1 = 810 mVPP 2 = 770 mVPP 3 = 745 mVPP 4 = 960 mVPP 5 = 930 mVPP 6 = 905 mVPP 7 = 880 mVPP 4 0 W 0h Must write 0 3 FOVR CHA EN R/W 0h This bit enables overwrites of the PDN pin with the FOVR signal from channel A. 0 = Normal operation 1 = PDN is overwritten 0 R/W 0h Must write 0 2-0 80 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page Figure 8-66. Register 068h 7 6 5 4 3 2 1 0 FREEZE CORR DC OFFSET CORR BW DC OFFSET CORR BW DC OFFSET CORR BW DC OFFSET CORR BW BYPASS CORR ALWAYS WRITE 1 0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h W-0h Table 8-78. Register 068h Field Descriptions Bit 7 Field Type Reset Description FREEZE CORR R/W 0h Offset correction block is enabled by default. Set this bit to freeze the block. 0 = Default after reset 1 = Offset correction block is frozen See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. R/W 0h These bits allow the user to program the 3-dB bandwidth of the notch filter centered around k x fs4/ 4 (k = 0, 1, 2). The notch filter is a first-order digital filter with 3-dB bandwidth: 3-dB bandwidth normalized to fs 0 = 2.99479E-07 1 = 1.4974E-07 2 = 7.48698E-08 3 = 3.74349E-08 4 = 1.87174E-08 5 = 9.35872E-09 6 = 4.67936E-09 7 = 2.33968E-09 8 = 1.16984E-09 9 = 5.8492E-10 10 = 2.9246E-10 11 = 1.4623E-10 For example, at fs = 1 GSPS,if DC OFFSET CORR BW is set to 1, the notch filter has a 3-dB bandwidth of 149.74 Hz. DC OFFSET CORR BW 6-3 2 BYPASS CORR R/W 0h 0 = Default after reset 1 = Offset correction block is bypassed See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. 1 ALWAYS WRITE 1 R/W 0h Always write 1 0 0 W 0h Must write 0 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 81 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page Figure 8-67. Register 069h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EXT CORR EN W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h Table 8-79. Register 069h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 0h Enables loading of external estimate into offset correction block. 0 = Default after reset (device uses internal estimate for offset correction) 1 = External estimate can be loaded by using the ADCx_LOAD_EXT_EST register bits See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. 0 EXT CORR EN R/W 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page Figure 8-68. Registers 074h, 076h, 078h, 7Ah 7 6 1 0 ADCx_CORR_INT_EST[5:0] 5 4 3 2 X X R/W-0h n/a n/a Table 8-80. Registers 074h, 076h, 078h, 7Ah Field Descriptions Bit Field Type Reset Description 7-2 ADCx_CORR_INT_EST[5:0] R/W 0h Internal estimate for all four interleaving ADC cores of the dc offset corrector block can be read from these bits. Keep the R/W bit set to 1 when reading from these registers. See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. 1-0 X n/a n/a Don't care 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page Figure 8-69. Registers 075h, 077h, 079h, 7Bh 7 6 5 4 3 0 0 0 0 0 2 ADCx_CORR_INT_EST[8:6] 1 W-0h W-0h W-0h W-0h W-0h R/W-0h 0 Table 8-81. Registers 075h, 077h, 079h, 7Bh Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 0h Internal estimate for all four interleaving ADC cores of the dc offset corrector block can be read from these bits. Keep the R/W bit set to 1 when reading from these registers. See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. 2-0 82 ADCx_CORR_INT_EST[8:6] R/W Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page Figure 8-70. Registers 00h, 04h, 08h, 0Ch 7 6 1 0 ADCx_LOAD_EXT_EST[5:0] 5 4 3 2 X X R/W-0h n/a n/a Table 8-82. Registers 00h, 04h, 08h, 0Ch Field Descriptions Bit Field Type Reset Description 5-0 ADCx_LOAD_EXT_EST[5:0] R/W 0h External estimate can be loaded into the dc offset corrector blocks for all four interleaving ADC cores. See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. 1-0 X n/a n/a Don't care 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page Figure 8-71. Registers 01h, 05h, 09h, 0Dh 7 6 5 4 3 2 1 0 0 0 0 0 ADCx_LOAD_EXT_EST[8:6] W-0h W-0h W-0h W-0h W-0h R/W-0h 0 Table 8-83. Registers 01h, 05h, 09h, 0Dh Field Descriptions Bit Field Type Reset Description 7-3 0 W 0h Must write 0 0h External estimate can be loaded into the dc offset corrector blocks for all four interleaving ADC cores. See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details. 2-0 ADCx_CORR_INT_EST[8:6] R/W Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 83 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 8.5.2.8.3 Registers 78h (address = 78h), Offset Load Page Figure 8-72. Registers 078h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 IL ENGINE FREEZE SECONDARY CONTROL W W W W W W W R/W Table 8-84. Registers 078h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 IL ENGINE FREEZE SECONDARY CONTROL R/W 0h Whenever IL ENGINE freeze is required, this bit needs to be set to 0. 0 84 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9 Application Information Disclaimer Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 85 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.1.1 Start-Up Sequence The steps described in Table 9-1 are recommended as the power-up sequence with the ADS54J40 in 20X mode (LMFS = 8224). Table 9-1. Initialization Sequence STEP 1 SEQUENCE Power-up the device PAGE BEING PROGRAMMED DESCRIPTION Bring up IOVDD to 1.15 V before applying power to DVDD. Bring up DVDD to 1.9 V, AVDD to 1.9 V, and AVDD3V to 3.0 V. COMMENT — See the Power Sequencing and Initialization section for power sequence requirements. — A hardware reset clears all registers to their default values. Hardware reset Apply a hardware reset by pulsing pin 48 (low → high → low). Register writes are equivalent to a hardware reset. Write address 0-000h with 81h. 2 Reset the device General register Write address 4-001h with 00h and address 4-002h with 00h. Unused page Write address 4-003h with 00h and address 4-004h with 68h. — Write address 6-0F7h with 01h for channel A. Write address 6-000h with 01h, then address 6-000h with 00h. 3 Performance modes Reset registers in the ADC and master pages of the analog bank. This bit is a self-clearing bit. Clear any unwanted content from the unused pages of the JESD bank. Select the main digital page of the JESD bank. Use the DIG RESET register bit to reset all pages in the JESD bank. Main digital page This bit is a self-clearing bit. (JESD bank) Pulse the PULSE RESET register bit for channel A. Write address 0-011h with 80h. — Write address 0-059h with 20h. Master page (analog bank) Select the master page of the analog bank. Set the ALWAYS WRITE 1 bit. Default register writes for DDC modes and JESD link configuration (LMFS 8224). Write address 4-003h with 00h and address 4-004h with 69h. Write address 6-000h with 80h. JESD link is configured with LMFS = 8224 by default with no decimation. Write address 4-003h with 00h and address 4-004h with 6Ah. 4 Program desired registers for decimation options and JESD link configuration JESD link is configured with LMFS = 8224 by default with no decimation. Write address 6-017h with 40h. — JESD digital page (JESD bank) — JESD analog page (JESD bank) Write address 6-017h with 00h. JESD link is configured with LMFS = 8224 by default with no decimation. Write address 6-000h with 01h and address 6-000h with 00h. 5 86 Set the CTRL K bit for both channels by programming K according to the SYSREF signal later on in the sequence. See Table 8-14 for configuring the JESD digital page registers for the desired LMFS and programming appropriate DDC mode. Select the JESD analog page. See Table 8-14 for configuring the JESD analog page registers for the desired LMFS and programming appropriate DDC mode. PLL reset. PLL reset clear. Write address 4-003h with 00h and address 4-004h with 68h. Set the value of K and the SYSREF signal frequency accordingly Select the JESD digital page. Write address 4-003h with 00h and address 4-004h with 69h. Write address 6-006h with XXh (choose the value of K). — Select the main digital page. See Table 8-14 for configuring the main digital page registers for the desired Main digital page LMFS and programming appropriate DDC mode. (JESD bank) Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed. — JESD digital page (JESD bank) Submit Document Feedback Select the JESD digital page. See the SYSREF Signal section to choose the correct frequency for SYSREF. Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 9-1. Initialization Sequence (continued) STEP SEQUENCE DESCRIPTION PAGE BEING PROGRAMMED Pull the SYNCB pin (pin 63) low. 6 JESD lane alignment Pull the SYNCB pin high. COMMENT Transmit K28.5 characters. — After the receiver is synchronized, initiate an ILA phase and subsequent transmissions of ADC data. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 87 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.1.2 Hardware Reset Figure 9-1 and Table 9-2 show the timing for a hardware reset. Power Supplies t1 RESET t2 t3 SEN Figure 9-1. Hardware Reset Timing Diagram Table 9-2. Timing Requirements MIN t1 Power-on delay: delay from power-up to an active high RESET pulse t2 Reset pulse duration: active high RESET pulse duration t3 Register write delay: delay from RESET disable to SEN active TYP MAX UNIT 1 ms 10 ns 100 ns 9.1.3 SNR and Clock Jitter The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 86 dBFS for a 14-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies. (4) The SNR limitation resulting from sample clock jitter can be calculated by Equation 5: (5) The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs) is set by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6: (6) External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as bandpass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter. 88 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 The ADS54J40 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 9-2. 75 35 fS 50 fS 100 fS SNR (dBFS) 73 150 fS 200 fS 71 69 67 65 10 100 Input Frequency (MHz) D052 Figure 9-2. SNR versus Input Frequency and External Clock Jitter 9.1.4 DC Offset Correction Block in the ADS54J40 The ADS54J40 employs eight dc offset correction blocks (four per channel, one per interleaving core). Figure 9-3 shows a dc correction block diagram. Input data, x(n) (250 MSPS data from each interleaving core) 0 Output data, y(n) at 250 MSPS 1 + ± + DC Corrected data ALWAYS WRITE 1 (Reg 68h, bit 1) 0 DC Correction Engine BYPASS CORR 1 FREEZE CORR ADCx_LOAD_EXT_EST[8:0] Internal Estimate Read back path ADCx_CORR_INT_EST[8:0] EXT CORR EN Figure 9-3. DC Offset Correction Block Diagram The purpose of the dc offset correction block is to correct the dc offset of interleaving cores that mainly arise the from amplifier in the first pipeline stage. Any mismatch in dc offset among interleaving cores results in spurs at fS / 4 and fS / 2. The dc offset correction blocks estimate and correct the dc offset of the individual core, to an ideal mid-code value, and thereby remove the effect of offset mismatch. The dc offset correction block can correct the dc offset of individual core up to ±1024 codes. In applications involving dc-coupling between the ADC and the driver, the dc offset correction block can either be bypassed or frozen because the block cannot distinguish the external dc signal from the internal dc offset. Figure Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 89 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9-4 shows that when bypassed, the internal dc mismatch appears at dc, and the f S / 4 and fS / 2 frequency points and can be as big as –40 dBFS. 0 Amplitude (dBFS) -20 -40 -60 -80 -100 -120 0 100 200 300 Frequency (MHz) 400 500 D001 Figure 9-4. FFT After Bypassing the DC Offset Correction Block 9.1.4.1 Freezing the DC Offset Correction Block After the device is powered up, the dc offset correction block estimates the internal dc offset with the idle channel input before the block is frozen. When frozen, the correction block holds the last estimated value that belongs to the internal dc offset. After the correction block is frozen, an external signal can be applied. 9.1.4.2 Effect of Temperature The internal dc offset of the individual cores changes with temperature, resulting in fS / 4 and fS / 2 spurs appearing again in the spectrum at a different temperature. Figure 9-5 shows the variation of the fS / 4 spur over temperature for a typical device. -40 fs/4 Spur (dBFS) -50 -60 -70 -80 -90 -40 -15 10 35 Temperature (°C) 60 85 D068 The offset correction block was frozen at room temperature, then the temperature was varied from –40°C to +85°C. Figure 9-5. Variation of the fS / 4 Spur Over Temperature Although some systems can accept such a variation in the fS / 4 and fS / 2 spurs across temperature, other systems may require the internal dc offset profile to be calibrated with temperature. To achieve the calibration of internal dc offset, the device provides an option to read the internal estimate values from the correction block for each of the interleaving cores and also to load the values back to the correction block. For calibration, after power up, a temperature sweep can be performed with the idle channel input and the internal dc offset can be read back using the ADCx_CORR_INT_EST register bits for salient temperature points. Then during operation, when the temperature changes, corresponding estimates can be externally loaded to the correction block using the ADCx_LOAD_EXT_EST register bits. 90 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 The dc offset corrector block is enabled by default. For a given channel, the device can disable and freeze the block, read the block estimate, and load the external estimate. Table 9-3 lists an example of the required SPI writes for reading an internal estimate of the dc offset correction block, and then loading the estimate back to the corrector. Table 9-3. Format (16-Bit Address, 8-Bit Data) STEP ADDRESS (Hex)(1) DATA (Hex) 4-005 01 4-004 61 4-003 00 4-002 00 4-001 00 E-074 xx COMMENT This setting disables broadcast mode (channel A and B can be individually programmed) Select the offset read page (61000000h) Data from offset read page can be read as below (keep the R/W bit = 1) Reading an internal estimate from both channels Reading the internal estimate [5:0] for core 0, channel A on the SDOUT pin E-075 xx Reading the internal estimate [8:6] for core 0, channel A on the SDOUT pin E-076 xx Reading the internal estimate [5:0] for core 1, channel A on the SDOUT pin E-077 xx Reading the internal estimate [8:6] for core 1, channel A on the SDOUT pin E-078 xx Reading the internal estimate [5:0] for core 2, channel A on the SDOUT pin E-079 xx Reading the internal estimate [8:6] for core 2, channel A on the SDOUT pin E-07A xx Reading the internal estimate [5:0] for core 3, channel A on the SDOUT pin E-07B xx Reading the internal estimate [8:6] for core 3, channel A on the SDOUT pin F-074 xx Reading the internal estimate [5:0] for core 0, channel B on the SDOUT pin F-075 xx Reading the internal estimate [8:6] for core 0, channel B on the SDOUT pin F-076 xx Reading the internal estimate [5:0] for core 1, channel B on the SDOUT pin F-077 xx Reading the internal estimate [8:6] for core 1, channel B on the SDOUT pin F-078 xx Reading the internal estimate [5:0] for core 2, channel B on the SDOUT pin F-079 xx Reading the internal estimate [8:6] for core 2, channel B on the SDOUT pin F-07A xx Reading the internal estimate [5:0] for core 3, channel B on the SDOUT pin F-07B xx Reading the internal estimate [8:6] for core 3, channel B on the SDOUT pin Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 91 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 9-3. Format (16-Bit Address, 8-Bit Data) (continued) STEP Loading an external estimate to both channels (1) 92 ADDRESS (Hex)(1) DATA (Hex) 6-069 01 Enables the external correction bit located in the offset read page for channel A 7-069 01 Enables the external correction bit located in the offset read page for channel B 4-004 61 4-003 00 4-002 05 4-001 00 COMMENT Change the page to the offset load page (61000500h) 6-000 xx Loading the external estimate [5:0] for core 0, channel A through SPI writes 6-001 xx Loading the external estimate [8:6] for core 0, channel A through SPI writes 6-004 xx Loading the external estimate [5:0] for core 1, channel A through SPI writes 6-005 xx Loading the external estimate [8:6] for core 1, channel A through SPI writes 6-008 xx Loading the external estimate [5:0] for core 2, channel A through SPI writes 6-009 xx Loading the external estimate [8:6] for core 2, channel A through SPI writes 6-00C xx Loading the external estimate [5:0] for core 3, channel A through SPI writes 6-00D xx Loading the external estimate [8:6] for core 3, channel A through SPI writes 7-000 xx Loading the external estimate [5:0] for core 0, channel B through SPI writes 7-001 xx Loading the external estimate [8:6] for core 0, channel B through SPI writes 7-004 xx Loading the external estimate [5:0] for core 1, channel B through SPI writes 7-005 xx Loading the external estimate [8:6] for core 1, channel B through SPI writes 7-008 xx Loading the external estimate [5:0] for core 2, channel B through SPI writes 7-009 xx Loading the external estimate [8:6] for core 2, channel B through SPI writes 7-00C xx Loading the external estimate [5:0] for core 3, channel B through SPI writes 7-00D xx Loading the external estimate [8:6] for core 3, channel B through SPI writes The address field is represented in four hex bits in a-bcd format, where a contains information about the R/W, M, P, and CH bits, and bcd contains the actual address of the register. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.1.5 Idle Channel Histogram 7000 2800 6000 2400 5000 2000 Code Occurrence Code Occurrence Figure 9-6 shows a histogram of output codes for when no signal is applied at the analog inputs of the ADS54J40 . Figure 9-7 shows that when the dc offset correction block of the device is bypassed, the output code histogram becomes multi-modal with as many as four peaks because the ADS54J40 is a 4-way interleaved ADC with each ADC core having a different internal dc offset. 4000 3000 2000 1000 0 8184 1600 1200 800 400 D060 0 8080 8100 8120 8140 8160 8180 8200 8220 8240 8260 8280 Output Code D061 Figure 9-6. Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is On) Figure 9-7. Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is Off) 8187 8190 8193 8196 Output Code 8199 8202 Figure 9-8 shows that when the dc offset correction block is frozen (instead of bypassed), the output code histogram improves (compared to when bypassed). However, when the temperature changes, the dc offset difference among interleaving cores may increase resulting in increased spacing between peaks in the histogram. 8000 7000 Code Occurrence 6000 5000 4000 3000 2000 1000 0 8180 8182 8184 8186 8188 8190 8192 8194 8196 8198 8200 Output Code D062 D107 Figure 9-8. Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is Frozen) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 93 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.1.6 Interleaving (IL) Mismatch Compensation 9.1.6.1 Introduction The ADC in ADS54J40 is an interleaved ADC, which is realized by interleaving the outputs of 4 component ADCs running at one-fourth of the final rate. Gain/timing mismatches between the 4 component ADCs give rise to images in the spectrum, located at Fin + kFs/4, k = 1,2,3, where Fin is the input frequency and Fs is the overall ADC sampling frequency. Note that the frequencies Fin + kFs/4 will alias and fall within [-Fs/2,Fs/2] when the ADC out is observed. The Interleaving (IL) mismatch corrector module in ADS54J40 compensates for these images. Input Analog Signal IL Mismatch Corrector ADC Digital Data To DDC/Output Digital Correction Parameters IL Mismatch Parameters Estimator Analog Correction Parameters Figure 9-9. Block diagram of Interleaving mismatch Compensation 9.1.6.2 Features 1. IL mismatch correction has 2 components – Analog Correction component and Digital Correction component. The correction parameters are provided by the ‘IL Mismatch Parameters Estimator’ block shown in Fig 1. 2. Tracking of IL mismatch parameters happens continuously in the background, based on incoming data (except under certain specific conditions listed in item 5). 3. IL mismatch estimation uses Nyquist band information programmed by the user, for proper estimation from the input signals. Note that for higher Nyquist signals, the IL spurs are at Fin_alias + kFs/4 (k = 1,2,3) where Fin_alias is the aliased input frequency between [-Fs/2,Fs/2]. This effectively gives the location of IL spurs at the ADC output. a. Any change in Nyquist band should be succeeded by a “pulse reset”. A pulse reset signal resets the internal IL mismatch estimation and correction and the JESD link. However; all other registers written into the IL engine or the status of the rest of the system is unaffected by a pulse reset. The IL mismatch parameters would be reestimated for the new Nyquist band after a pulse reset b. In typical use cases, signals would be present only within one Nyquist band. However, if there are signals across multiple Nyquist bands (for eg the desired bands in multiple Nyquist bands may not alias after sampling enabling them to be separated later), it is possible that IL performance may be degraded. So it is 94 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 advisable to disable IL engine to get raw IL performance. The typical raw IL performance is shown in Figure 9-10. Typical raw IL Performance 90 60 86 56 82 52 78 48 74 44 70 0 40 IL Disable, IL Spur (dBc) IL Enable, IL Spur (dBc) IL Enable IL Disable 40 80 120 160 200 240 280 320 360 400 440 480 Input Frequency (MHz) D500 Figure 9-10. Typical raw IL Performance 4. IL image performance starts to degrade gracefully for signal frequency components > 0.9 x Fs/2, for 1st Nyquist signals, as digital correction cannot accurately correct for signals very close to Nyquist band edge . a. For signals in higher Nyquist bands, the performance degrades gracefully for aliased frequency components 0.9Fs/2 5. IL correction accuracy will continue to be maintained unless any of the following conditions are hit: a. Persistent Signal absence: The IL estimator works on the input signals to estimate and track IL mismatch parameters over time. So if no input signal is present, then IL mismatch estimation is not possible. See item 5f for further details. No Estimation Signal not present OFF Time b. Persistent very weak signal only: As IL estimator works on input signals, it needs reasonable-powered signals present for some continuous period of time to get IL estimates properly. The signal power in atleast one frequency band of width Fs/256 has to be > -35 dBFs for proper IL estimation. Further such signal needs to be present in chunks of atleast 100 µs for an integrated ON period of at least 10 ms over a Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 95 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 total time of 100 ms for proper IL estimation. See item 5f for further details. Estimation Valid Signal ON time > 10ms Signal OFF time ON OFF 0 ms 100 ms Time No Estimation Signal ON time < 10ms Signal OFF time ON OFF 0 ms 100 ms Time Estimation Valid Integrated Signal ON time > 10ms, with individual ON times > 100us ON OFF ON OFF ON OFF 0 ms ON OFF ON OFF ON OFF ON OFF 100 ms Time No Estimation Integrated Signal ON time > 10ms, BUT individual ON times < 100us O OF N F O OF N F O OF N F 0 ms O OF N F O OF N F O OF N F O OF N F O OF N F O OF N F O OF N F Time O OF N F O OF N F O OF N F O OF N F 100 ms c. Consistent Signal saturation: Whenever signal is saturated, signal gets distorted and IL estimation is no longer possible. IL estimation is possible if signal amplitude is < -0.5 dBFs for more than 100 µs in one 96 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 chunk and such chunks make up atleast 10 ms in a 100 ms window. See item 5f for further details. No Estimation Signal not saturated for > 10ms Signal Saturated Normal Sat 0 ms 100 ms Time No Estimation Signal not saturated for < 10ms Signal Saturated Normal Sat 0 ms 100 ms Time Estimation Valid Non-saturated(normal) time blocks > 100us with total normal block time > 10ms Nor mal Nor mal Sat Sat Nor mal Nor mal Sat 0 ms Nor mal Sat Sat Nor mal Nor mal Sat Nor mal Sat 100 ms Time No Estimation Non-saturated(normal) time blocks < 100us with total normal block time > 10ms No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat No rm al Sat 0 ms Submit Document Feedback Product Folder Links: ADS54J40 Sat 100 ms Time Copyright © 2020 Texas Instruments Incorporated No rm al 97 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 d. Signal presence in a very small band only around kfs/8: If input signal is present only within 5e-7 x Fs of kFs/8 (k = 0,1,2,3), then no IL estimation is possible as the IL signal and IL image are not separable. See No Estimation Signal only around kfs/8 +/-500Hz around fs/4 Fs/4 Fs/2 = 512 MHz item 5f for further details. e. Presence of high power signal component in the IL image band: In some cases, the signal component (such as Sig1) may be present in the IL image band of other components of the signal (such as Sig0). This signal component in IL image band (Sig1) acts as an interferer for IL estimation of the first component (Sig0). If the ratio of the power of the signal component causing IL mismatch (power of Sig0) to the power of the signal component in the IL image band (power of Sig1) is less than 25 dB, then IL estimation cannot be done for that signal component (Sig0). See item 5f for further details No Estimation Estimation Valid Sig0 Pwr_diff_dB < 25 dB Sig0 Pwr_diff_dB > 25 dB Sig1 IL image Sig1 IL image IL image of Sig1 IL image of Sig0 IL image of Sig0 IL image of Sig1 Frequency Frequency f. In the normal course of operation, old IL mismatch estimates are retained and used for correction even if there are no current IL mismatch estimates due to any of the conditions listed in 5a – 5e. This enables good performance when any of the conditions in 5a-5e are present for a short duration. However if any of the conditions that prevent estimation listed in 5a – 5e persist for a large time (>40s), then the estimated digital IL mismatch parameters are reset and the digital IL mismatch parameters are re-estimated when the conditions for estimation becomes favorable again. • If the user knows apriori that such a condition will occur and would like the old IL correction to be retained, then a good option is to freeze the IL engine as in item 6. This freeze stops the IL engine and so the old IL estimates are not discarded. Digital IL mismatch estimates are reset IL mismatch estimates not available continuously for a long period No Estimation No Estimation No Estimation ««. No Estimation No Estimation No Estimation 40s 0 Time 98 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 g. Signal and IL image overlap: If signal component is present around kfs/8 (k = 0,1,2,3), then the IL image band will also overlap with the signal making it difficult to estimate IL mismatch parameters. Overlap of signal and IL image bands around kfs/8 should be < Fs/256 MHz for 90% of the time for proper IL estimation. Note that if this condition cannot be ensured, then IL performance will be degraded. If this condition is violated in a known period, then the user can freeze IL engine when this condition occurs as described in section 6. Otherwise, user has to switch to options in items 6 or 7 to avoid performance Estimation Valid Nonoverlap > 4 MHz No Estimation Nonoverlap < 4 MHz IL image kfs/8, k=1/ Frequency IL image kfs/8, k=1/ Frequency 2/3 2/3 degradation 6. Freezing the IL Engine: If the user knows apriori that any of the conditions in item 5f occurs and would like the old IL correction to be retained, then a good option is to freeze the IL engine. Or, if the user knows that condition in 5g is violated at a known time, then also freezing the IL engine is a good option. Once IL engine is frozen, all past IL estimates/correction are retained and no updates are done to the IL estimates. Once the conditions described above are no longer present, then the IL engine can be unfrozen. The IL engine then starts updating the estimates as though the entire period for which it was frozen did not exist at all. Table 9-4. IL Freeze SPI Address SPI Data Comments 0x4005 0x1 Enable per channel writes 0x4004 0x68 Page Select 0x4003 0x00 Page Select 0x4002 0x00 Page Select 0x4001 0x00 Page Select 0x604D 0x01 Validity for IL Freeze/Unfreeze for CHA 0x704D 0x01 Validity for IL Freeze/Unfreeze for CHB 0x6068 0x04 Freeze IL Engine for CHA 0x7068 0x04 Freeze IL Engine for CHB 0x4004 0x61 Page Select 0x4003 0x00 Page Select 0x4002 0x05 Page Select 0x4001 0x00 Page Select 0x6078 0x00 IL Engine Freeze Secondary Control for CHA 0x7078 0x00 IL Engine Freeze Secondary Control for CHB 0x4004 0x68 Page Select 0x4003 0x00 Page Select 0x4002 0x00 Page Select Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 99 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Table 9-4. IL Freeze (continued) SPI Address SPI Data Comments 0x4001 0x00 Page Select Table 9-5. IL Unfreeze SPI Address SPI Data Comments 0x4005 0x00 Enable per channel writes 0x4004 0x68 Page Select 0x4003 0x00 Page Select 0x4002 0x00 Page Select 0x4001 0x00 Page Select 0x604D 0x01 Validity for IL Freeze/Unfreeze for CHA 0x704D 0x01 Validity for IL Freeze/Unfreeze for CHB 0x6068 0x00 Unfreeze IL Engine for CHA 0x7068 0x00 Unfreeze IL Engine for CHB 7. In case the limitations in items 5 cannot be worked around in the user system and the limitations are permanent (eg a system where the entire band from [0,fs/2) is nearly fully occupied or signals present around kfs/8 with overlap < Fs/256), then there are 2 options a. Power up/Temp based IL calibration - Do calibration using a single tone (single tone frequency in [0.77fs/2, 0.9 x fs/2], single tone power in [-0.5, -25] dBFs), either one-time or whenever temperature changes by more than a desired threshold, and then freeze IL estimation module. During calibration, the normal input should be bypassed and the calibration signal should be input to ADS54J40 for 100 ms for high power signals (≥ - 3 dBFs) and 500 ms for lower powered signals. Once the calibration time is complete, IL estimation should be frozen and normal signal may be input to ADS54J40. To determine the temperature change for which calibration needs to be done, the user can refer to typical variation of IL spur with temperature, under freeze conditions, as shown in Figure 9-11 . Power Up Device Load Default Config Freeze IL Calibration Provide calib signal: Single tone @ Fin in [0.77fs/2,0.9fs/ 2]. Power in [-0.5,-25] dBFS Wait for calibration to complete: 100ms for high powers (>=-3dBFs) and 500ms for lower powers Connect Regular Input Signal Flowchart For Powerup IL calibration Figure 9-11. Flowchart for Powerup IL Calibratuion 100 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 Replace regular input signal with calibration signal: Single tone @ Fin in [0.77fs/2,0.9fs/2]. Power in [-0.5,-25] dBFS Freeze IL Calibration Unfreeze IL Calibration Wait for calibration to complete: 100ms for high powers (>=3dBFs) and 500ms for lower powers Connect Regular Input Signal Flowchart For IL Calibration whenever temperature changes significantly Figure 9-12. Flow chart for intermittent IL calibration b. Disable IL correction – IL performance would be limited to raw IL performance as shown in figure in the data sheet. Note that the disable IL correction sequence includes “pulse reset”. A pulse reset signal resets the internal IL mismatch estimation and correction and the JESD link. Therefore, in case IL correction disable is desired, it is preferable to insert this sequence within the device bring up sequence, just before the final pulse reset is issued. Table 9-6. IL Disable SPI Address SPI Data Comments 0x4005 0x0 Enable single channel writes 0x4004 0x68 Selecting page 0x4003 0x00 Selecting page 0x4002 0x00 Selecting page 0x4001 0x00 Selecting page 0x604B 0x04 Validity for IL Correction Disable for CHA 0x704B 0x04 Validity for IL Correction Disable for CHB 0x6040 0x08 Disable IL Correction for CHA 0x7040 0x08 Disable IL Correction for CHB 0x6000 0x01 Pulse reset assert 0x6000 0x00 Pulse reset de-assert Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 101 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.1.6.3 Temperature variation IL mismatch parameters estimator tracks IL mismatch variations across temperature and gives good performance under normal conditions. However if IL mismatch estimation is frozen, the residual IL mismatch seen would vary with temperature as shown in Figure 9-13. To reduce the residual IL mismatch below this level, customer may put the system in calibration mode whenever significant temperature change is detected or based on a certain time lapse from the last calibration. -50 Interleaving Spur (dVFS) -55 -60 -65 -70 -75 -80 -85 -90 fIN+3fS/4 fIN+fS/2 fIN+fS/4 -95 -100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) D501 Figure 9-13. Residual IL Spur for signal at 400 Mhz vs Temperature after freezing IL calibration at 25°C 102 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.2 Typical Application The ADS54J40 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 9-14. DVDD 10 k 5: 50 : Driver 0.1 PF 0.1 PF 50 : 2 pF SPI Master 5: GND GND 0.1 PF GND 0.1 PF IOVDD 0.1 PF 100 : SYSREFM AVDD AVDD AGND 3 DB3M SYSREFP 4 DB3P AGND 5 DGND 0.1 PF GND 6 IOVDD AVDD3V 7 SDIN AVDD3V 8 SCLK Low-Jitter Clock Generator AVDD 9 SEN AGND GND 0.1 PF DVDD CLKINM 10 AVDD CLKINP 11 AVDD3V AGND 12 SDOUT AVDD AVDD 0.1 PF GND 13 AVDD 10 nF AVDD3V 14 INBP AGND GND 0.1 PF AVDD3V 15 INBM 0.1 PF 16 AVDD VCM DVDD AVDD3V NC NC AVDD AGND NC 17 10nF AVDD AVDD3V 18 GND 0.1 PF AVDD3V AVDD 2 100-: Differential 1 10 nF 19 72 20 71 21 70 22 69 23 68 24 67 25 66 26 65 27 64 GND Pad (Back Side) 28 63 29 62 30 61 31 60 32 59 33 58 34 57 35 56 36 55 DB2P DB2M IOVDD IOVDD 10 nF DB1P 10 nF GND DB1M DGND DB0P 10 nF GND DB0M IOVDD IOVDD 0.1 PF SYNC GND DA0M FPGA DA0P DGND DA1M 10 nF GND DA1P IOVDD IOVDD 10 nF 10 nF DA2M GND DA2P GND 37 38 39 40 42 43 44 45 46 47 49 51 52 53 10 nF 54 DA3M DA3P DGND IOVDD PDN RES RESET AVDD3V GND 50 100-: Differential 10 nF DVDD AVDD AVDD 48 DVDD AVDD AVDD3V AVDD AVDD INAP INAM AVDD AVDD3V AVDD AGND AVDD3V 41 0.1 PF GND 0.1 PF GND 0.1 PF IOVDD GND 5: 50 : Driver 0.1 PF 0.1 PF 50 : GND 2 pF 5: NOTE: GND = AGND and DGND connected in the PCB layout. Figure 9-14. AC-Coupled Receiver Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 103 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.2.1 Design Requirements 9.2.1.1 Transformer-Coupled Circuits Transformer-Coupled Circuits Typical applications involving transformer-coupled circuits are discussed in this section. To achieve good phase and amplitude balances at the ADC input, surface-mount transformers can be used (for example transformers such as ADT1-1WT or WBC1-1 can be used for frequencies up to 300 MHz and TC1-1-13M+ for higher frequencies) to achieve good phase and amplitude balances at the ADC inputs. When designing dc-driving circuits, the ADC input impedance must be considered. Figure 9-15 and Figure 9-16 show the impedance (ZIN = RIN || CIN) across the ADC input pins. 5 Differential Input Capacitance (pF) Differential Input Resistance (k:) 1.4 1.2 1 0.8 0.6 0.4 0.2 4.75 4.5 4.25 4 3.75 3.5 3.25 3 2.75 2.5 2.25 0 0 100 200 300 400 500 600 700 Frequency (MHz) 800 0 900 1000 D103 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 D102 Figure 9-16. CIN vs Input Frequency Figure 9-15. RIN vs Input Frequency By using the simple drive circuit of Figure 9-17, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit. 0.1 F T1 T2 0.1 F 5 CHx_INP 25 0.1 F RIN 0.1 F 1:1 CIN 25 5 CHx_INM 1:1 Device Figure 9-17. Input Drive Circuit 9.2.2 Detailed Design Procedure For optimum performance, the analog inputs must be driven differentially. This architecture improves commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 9-17. 104 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 9.2.3 Application Curves 0 0 -20 -20 Amplitude (dBFS) Amplitude (dBFS) Figure 9-18 and Figure 9-19 show the typical performance at 170 MHz and 230 MHz, respectively. -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 0 100 200 300 Input Frequency (MHz) 400 500 0 D003 SNR = 68.9 dBFS; SFDR = 86 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc Figure 9-18. FFT for 170-MHz Input Signal 100 200 300 Input Frequency (MHz) 400 500 D004 SNR = 68.1 dBFS; SFDR = 84 dBc; IL spur = 86 dBc; non HD2, HD3 spur = 86 dBc Figure 9-19. FFT for 230-MHz Input Signal Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 105 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 10 Power Supply Recommendations The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating voltage minimum and maximum specifications of different supplies, see the Recommended Operating Conditions table. 10.1 Power Sequencing and Initialization Figure 10-1 shows the suggested power-up sequencing for the device. Note that the 1.15-V IOVDD supply must rise before the 1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the internal default register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V AVDD), can come up in any order during the power sequence. The power supplies can ramp up at any rate and there is no hard requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of microseconds but is recommend to be a few milliseconds). IOVDD = 1.15 V DVDD = 1.9 V AVDD = 1.9 V AVDD = 3 V Figure 10-1. Power Sequencing for the ADS54Jxx Family of Devices 106 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 11 Layout 11.1 Layout Guidelines The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 11-1. The ADS54J40 EVM User's Guide, SLAU652, provides a complete layout of the EVM. Some important points to remember during board layout are: • • • • • Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as illustrated in the reference layout of Figure 11-1 as much as possible. In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 11-1 as much as possible. Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output traces must not be kept parallel to the analog input traces because this configuration can result in coupling from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate arrays (FPGAs) or an application-specific integrated circuits (ASICs)] must be matched in length to avoid skew among outputs. At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source. The PDN and SDOUT traces must be routed away from the analog input traces. When the PDN and SDOUT pins are programmed to carry OVR information, the proximity of these pins to the analog traces may result in degradation of the ADC performance because of coupling. For best performance, the PDN and SDOUT traces must not overlap or cross the path of the analog input traces even if routed on different layers of the PCB. 11.2 Layout Example Figure 11-1. ADS54J40 EVM Layout Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 107 ADS54J40 www.ti.com SBAS714C – MAY 2015 – REVISED DECEMBER 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • ADS54J20 Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter • ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter • ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter • ADS54J66 Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC • ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter • ADS54J40EVM User's Guide 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 108 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS54J40IRMP ACTIVE VQFN RMP 72 168 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ54J40 ADS54J40IRMPT ACTIVE VQFN RMP 72 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 AZ54J40 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of