SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
FEATURES
D 14-Bit Resolution
D 125−MSPS Sample Rate
D High Signal−to−Noise Ratio (SNR):
D
70.5 dBFS at 100 MHz fIN (TYP)
High Spurious−Free Dynamic Range (SFDR):
82 dBc at 100−MHz fIN (TYP)
2.3-VPP Differential Input Voltage
D
D Internal Voltage Reference
D 3.3-V Single-Supply Voltage
D Analog Power Dissipation: 578 mW
D
D
− Total Power Dissipation: 780 mW
Serial Programming Interface
TQFP-64 PowerPADE Package
D One Assembly/Test Site
D One Fabrication Site
D Available in Military (−555C/1255C)
D
D
D
Temperature Range(1)
Extended Product Life Cycle
Extended Product−Change Notification
Product Traceability
APPLICATIONS
D Wireless Communication
D Test and Measurement Instrumentation
D Single and Multichannel Digital Receivers
D Communication Instrumentation
D
− Radar, Infrared
Video and Imaging
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
D Controlled Baseline
(1) Custom temperature ranges available.
DESCRIPTION
The ADS5500 is a high-performance, 14-bit 125−MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed
for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5500 has
excellent power consumption of 780 mW at 3.3-V single-supply voltage. This allows an even higher system
integration density. The provided internal reference simplifies system design requirements. A parallel CMOScompatible output ensures seamless interfacing with common logic.
The ADS5500 is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of
−55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2008, Texas Instruments Incorporated
!" # $% # ! &%'$ () (%$#
$!" #&$!$# & * "# ! +# #%"# #(( ,-)
(%$ &$## (# $##- $%( # ! &"#)
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
AVDD
CLK+
CLKOUT
Timing Circuitry
CLK-
VIN+
Digital
Error
Correction
14-Bit
Pipeline
ADC Core
S&H
VIN-
CM
DRVDD
D0
.
.
.
D13
OVR
DFS
Control Logic
Internal
Reference
Serial Programming Register
AGND
Output
Control
SEN
SDATA
SCLK
A D S 5500
DRGND
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5500−EP
HTQFP-64(2)
PowerPAD
PAP
−55°C to 125°C
ADS5500M
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
ADS5500MPAPEP
Tray, 160
ADS5500MPAPREP
Tape and Reel, 1000
(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max).
2
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ADS5500-EP
UNIT
−0.3 to +3.7
V
±0.1
V
Analog input to AGND
−0.15 to +2.5
V
Logic input to DRGND
−0.3 to DRVDD
+ 0.3
V
Digital data output to DRGND
−0.3 to DRVDD
+ 0.3
V
30
mA
Analog Input
−55 to +125
°C
Differential input range
+142
°C
−65 to +150
°C
Input common-mode voltage,
VCM(1)
Digital Output
Supply
Voltage
AVDD to
AGND,
DRVDD to
DRGND
AGND to
DRGND
Input current (any input)
Operating temperature range
Junction temperature
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
PARAMETER
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
TQFP−64 PowerPADTM Package
Thermal Characteristics
PARAMETER
Thermal
resistance,
junction to
ambient (see
(1) and (2)),
RTJA
Thermal
resistance,
junction to
case (see (1)
and (2)), RTJC
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
MIN
TYP
MAX
UNIT
Analog supply voltage, AVDD
3
3.3
3.6
V
Output driver supply voltage, DRVDD
3
3.3
3.6
V
Supplies
2.3
Maximum output load
PowerPAD NOT
CONNECTED
TO PCB
THERMAL
PLAN
PowerPAD
CONNECTED
TO PCB
THERMAL
PLANE(2)
75.83ºC/W
42.2ºC/W
21.47ºC/W
7.8ºC/W
0.38ºC/W
0.38ºC/W
1.6
10
V
pF
Clock Input
ADCLK input sample
rate (sine wave) 1/tC
DLL ON
60
125
DLL OFF
10
80
Clock amplitude, sine wave,
differential(2)
SAME
PACKAGE
FORM
WITHOUT
PowerPAD
1.5
VPP
Clock duty cycle(3)
3
MSPS
VPP
50%
Open free-air temperature
−55
125
(1) Input common-mode should be connected to CM.
(2) See Figure 14 for more information.
(3) See Figure 13 for more information.
°C
(1) Specified with the PowerPAD bond pad on the backside of the
package soldered to a 2-oz Cu plate PCB thermal plane.
(2) Airflow is at 0 LFM (no airflow)
3
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Long-term high−temperature storage and/or extended use at maximum recommended operating conditions may
result in a reduction of overall device life. See Figure 1 for additional information on thermal derating.
Electromigration failure mode applies to powered part; Kirkendall voiding failure mode is a function of temperature
only.
0.0001
150 °C (10.5 kHours, 1.2 Years)
1/Time to Failure − Hours
150 °C
(21 kHours, 2.4 Years)
Estimated Device life
ElectroMigration Fail Mode
125 °C (32 kHours, 3.8 Years)
0.00001
105 °C (87 kHours, >10 Years)
125 °C (47 kHours, 55.8 Years)
0.000001
0.0000001
Estimated Device Life
Wire Bond Kirkendall
Voiding Fail Mode
105 °C (8 MHours, >100 Years)
1/TJ − Constant Device Junction Temperature
Figure 1. Time-to-Failure vs Junction Temperature
4
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS
Typ, min, and max values at TA = 25°C, full temperature range is TMIN = −55°C to TMAX = 125°C, sampling rate = 125 MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3 V, DLL On, −1−dBFS differential input, and 3-VPP differential clock (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
14 Tested
Bits
2.3
VPP
kΩ
Analog Inputs
Differential input range
Differential input impedance
See Figure 5
Differential input capacitance
See Figure 5
6.6
Total analog input common-mode current
Analog input bandwidth
Source impedance = 50 Ω
4
pF
4(1)
mA
750
MHz
Conversion Characteristics
Maximum sample rate
Data latency
See note (2)
See timing diagram, See Figure 2
125
MSPS
16.5
Clock Cycles
Reference bottom voltage, VREFM
0.97
V
Reference top voltage, VREFP
2.11
Internal Reference Voltages
Reference error
Room temp
−4%
Full temp range
−5%
V
4%
5%
1.55 ±0.05
Common-mode voltage output, VCM
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
Differential linearity error, DNL
fIN = 10 MHz
Integral linearity error, INL
fIN = 10 MHz
−0.9
±0.75
1.1
Room temp
−5
5
Full temp range
−8
8
LSB
LSB
±1.5
mV
Offset temperature coefficient
0.0007
%/°C
Gain error
±0.45
%FS
Gain temperature coefficient
0.01
∆%/°C
Offset error
Dynamic AC Characteristics
fIN = 10 MHz
Room temp
Full temp range
70.5
71.5
68
71.5
fIN = 30 MHz
fIN = 55 MHz
Signal-to-noise ratio (SNR)
RMS output noise
fIN = 70 MHz
71.5
71.5
Room temp
Full temp range
70
71.2
66.5
71
fIN = 100 MHz
fIN = 150 MHz
70.5
fIN = 225 MHz
Input tied to common-mode
69.1
fIN = 10 MHz
70.1
1.1
Room temp
82
84
Full temp range
76
84
fIN = 30 MHz
fIN = 55 MHz
Spurious-free dynamic range (SFDR)
fIN = 70 MHz
dBFS
LSB
84
79
Room temp
80
83
Full temp range
75
82
fIN = 100 MHz
fIN = 150 MHz
82
fIN = 225 MHz
74
dBc
78
(1) 2-mA per input
(2) See Recommended Operating Conditions.
5
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS(continued)
Typ, min, and max values at TA = 25°C, full temperature range is TMIN = −55°C to TMAX = 125°C, sampling rate = 125 MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3 V, DLL On, −1−dBFS differential input, and 3-VPP differential clock (unless otherwise noted)
PARAMETER
CONDITIONS
fIN = 10 MHz
MIN
TYP
Room temp
82
91
Full temp range
77
86
fIN = 30 MHz
fIN = 55 MHz
Second−harmonic (HD2)
fIN = 70 MHz
84
Room temp
80
87
Full temp range
75
83
78
74
Room temp
82
89
Full temp range
77
88
fIN = 30 MHz
fIN = 55 MHz
Worst-harmonic/spur
(other than HD2 and HD3)
fIN = 70 MHz
90
79
Room temp
80
85
Full temp range
75
82
fIN = 100 MHz
fIN = 150 MHz
82
fIN = 225 MHz
fIN = 10 MHz Room temp
76
fIN = 70 MHz
86
fIN = 10 MHz
fIN = 70 MHz
88
Room temp
Room temp
Full temp range
69
70
66.5
70
70
Room temp
Full temp range
68.5
69
65
69.5
69
fIN = 225 MHz
66.4
6
fIN = 70 MHz
dBc
69
Room temp
80
85
Full temp range
76
83
fIN = 30 MHz
fIN = 55 MHz
Total harmonic distortion (THD)
dBc
69.5
fIN = 100 MHz
fIN = 150 MHz
fIN = 10 MHz
dBc
80
fIN = 30 MHz
fIN = 55 MHz
Signal-to-noise + distortion (SINAD)
dBc
84
fIN = 225 MHz
Third harmonic (HD3)
UNIT
86
fIN = 100 MHz
fIN = 150 MHz
fIN = 10 MHz
MAX
82
77
Room temp
Full temp range
77.5
81
74
79.5
fIN = 100 MHz
fIN = 150 MHz
79
fIN = 225 MHz
71.8
75
dBc
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS(continued)
Typ, min, and max values at TA = 25°C, full temperature range is TMIN = −55°C to TMAX = 125°C, sampling rate = 125 MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3 V, DLL On, −1−dBFS differential input, and 3-VPP differential clock (unless otherwise noted)
PARAMETER
CONDITIONS
Effective number of bits (ENOB)
MIN
TYP
fIN = 70 MHz
f = 10.1 MHz, 15.1 MHz
(−7 dBFS each tone)
Two-tone intermodulation distortion (IMD)
MAX
11.3
UNIT
Bits
85
f = 30.1 MHz, 35.1 MHz
(−7 dBFS each tone)
85
f = 50.1 MHz, 55.1 MHz
(−7 dBFS each tone)
88
dBc
Power Supply
VIN = full-scale, fIN = 5 5 MHz,
AVDD = DRVDD = 3.3V
VIN = full-scale, fIN = 5 5 MHz,
AVDD = DRVDD = 3.3V
Total supply current, ICC
Analog supply current, IAVDD
VIN = full-scale, fIN = 55 MHz,
AVDD = DRVDD = 3.3 V
Analog only
Output buffer supply current, IDRVDD
236
265
mA
175
190
mA
61
75
mA
578
627
mW
Power dissipation
Total power with 10−pF load on
digital output to ground
780
875
mW
Standby power
With clocks running
181
250
mW
DIGITAL CHARACTERISTICS
Typ, min, and max values at TA = 25°C, full temperature range is TMIN = −55°C to TMAX = 125°C, sampling rate = 125 MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3 V, DLL On, −1 dBFS differential input, and 3-VPP differential clock (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
µA
10
µA
Low-level input current
Input current for RESET
Input capacitance
Digital Outputs(1)
Low-level output voltage
High-level output voltage
Output capacitance
CLOAD = 10 pF(2), fS = 125 MSPS
CLOAD = 10 pF(2), fS = 125 MSPS
−20
µA
4
pF
0.3
V
3
V
3
pF
(1) For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load.
(2) Equivalent capacitance to ground of (load + parasitics of transmission lines)
7
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TIMING CHARACTERISTCS
Analog
Input
Signal
Sample
N
N+2
N+1
N+4
N+3
N + 15
N + 17
N + 16
tPDI
tA
Input Clock
tSETUP
Output Clock
tHOLD
N - 17
N - 16
Data Out
(D0−D13)
N - 15
N - 13
N- 3
N- 2
N- 1
N
Data Invalid
16.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 2. Timing Diagram
TIMING CHARACTERISTICS (1)
Typ, min, and max values at TA = 25°C, min and max specified over the full recommended operating temperature range,
AVDD = DRVDD = 3.3 V, 3−VPP differential clock, and CLOAD = 10 pF (unless otherwise noted)
PARAMETER
DESCRIPTION
TYP
UNIT
ns
Switching Specification
Aperture delay, tA
Input CLK falling edge to data sampling point
1
Aperture jitter (uncertainty)
300
fs
Data setup time, tSU
Uncertainty in sampling instant
Data valid(2) to 50% of CLKOUT rising edge
2.5
ns
Data hold time, th
50% of CLKOUT rising edge to data becoming invalid(2)
2.1
ns
Input clock to output data valid
start(3)(4), tSTART
Input clock rising edge to Data valid start delay
2.2
ns
Input clock to output data valid
end(3)(4), tEND
Input clock rising edge to Data valid end delay
6.9
ns
Output clock jitter, tJIT
Uncertainty in CLKOUT rising edge, peak−to−peak
150
ps
Output clock rise time, tr
Rise time of CLKOUT measured from 20% to 80% of
DRVDD
1.7
ns
Output clock fall time, tf
Fall time of CLKOUT measured from 80% to 20% of
DRVDD
1.5
ns
Input clock to output clock delay,
tPDI
Data rise time, tr
Input clock rising edge, zero crossing, to output clock
rising edge 50%
4.8
ns
Data rise time measured from 20% to 80% of DRVDD
3.6
ns
Data fall time, tf
Data fall time measured from 80% to 20% of DRVDD
2.8
ns
Latency Time for a sample to
propagate to the ADC outputs
17.5
Clock Cycles
17.5 clock cycles
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) Data valid refers to 2 V for LOGIC high and 0.8 V for LOGIC low.
(2) See the Output Information section for details on using the input clock for data capture.
(4) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add one−half clock period for the valid number
for a falling−edge CLKOUT polarity.
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
RESET TIMING CHARACTERISTICS
Typ, min, and max values at TA = 25°C, min and max specified over the full recommended operating temperature range,
AVDD = DRVDD = 3.3 V, 3−VPP differential clock (unless otherwise noted)
DESCRIPTION
PARAMETER
TYP
UNIT
40
ms
Switching Specification
Delay from power−up of AVDD and DRVDD to output
stable
Power−up time
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
D Data is loaded at every 16th SCLK falling edge
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
while SEN is low.
D In case the word length exceeds a multiple of
D Serial shift of bits is enabled when SEN is low.
16 bits, the excess bits are ignored.
SCLK shifts serial data at falling edge.
D Data can be loaded in multiple of 16-bit words within
D Minimum width of data stream for a valid loading is
a single active SEN pulse.
16 clocks.
A3
SDATA
A2
A1
A0
D11
ADDRESS
D10
D9
D0
DATA
MSB
Figure 3. DATA Communication Is 2 Byte, MSB First
tSLOADS
tSLOADH
SEN
tWSCLK
tWSCLK
tSCLK
SCLK
tOS
SDATA
tOH
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL
tSCLK
PARAMETER
SCLK period
MIN(1)
TYP(1)
MAX(1)
50
ns
tWSCLK
SCLK duty cycle
tSLOADS
SEN to SCLK setup time
8
ns
tSLOADH
SCLK to SEN hold time
6
ns
Data setup time
8
ns
6
ns
tDS
tDH
Data hold time
(1) Min, typ, and max values are characterized, but not production tested.
25%
UNIT
50%
75%
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Table 2. Serial Register Table
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
DLL
OFF
0
DLL OFF = 0: Internal DLL is on, recommended for
60−125 MSPS clock speed
DLL OFF = 1: Internal DLL is off, recommended for
10−80 MSPS clock speed
1
1
1
0
0
TP
TP
0
0
0
0
0
0
0
0
0
TP: Test modes for output data capture
TP = 0, TP = 0: Normal mode of operation,
TP = 0
TP = 1: All output lines are pulled to ’0’, TP = 1
TP = 0: All output lines are pulled to ’1’, TP = 1
TP = 1: A continuous stream of ’10’ comes out on
all output lines
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
0
0
PDN = 0: Normal mode of operation,
PDN = 1: Device is put in power down (low current)
mode
10
DESCRIPTION
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (VDFS)
DATA FORMAT
CLOCK OUTPUT POLARITY
1
6
Straight binary
Data valid on rising edge
V DFS t
AV DD
5
12
1
AV DD u V DFS u
3
AV DD
Twos complement
Data valid on rising edge
2
3
7
AV DD u V DFS u
12
AV DD
Straight binary
Data valid on falling edge
Twos complement
Data valid on falling edge
V DFS u
5
6
AV DD
PIN CONFIGURATION
DRVDD
DRGND
D4
D5
D6
D7
D8
D9
DRGND
DRVDD
DRGND
D10
D11
D12
D13 (MSB)
OVR
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DRGND 1
48 DRGND
SCLK 2
47 D3
SDATA 3
46 D2
SEN 4
45 D1
AVDD 5
44 D0 (LSB)
AGND 6
43 CLKOUT
AVDD 7
42 DRGND
A D S 5500
AGND 8
41 OE
P o w erP A D
AVDD 9
40 DFS
(Connected to Analog Ground)
CLKP 10
39 AVDD
CLKM 11
38 AGND
AGND 12
37 AVDD
AGND 13
36 AGND
AGND 14
35 RESET
AVDD 15
34 AVDD
AGND 16
33 AVDD
AGND
IREF
REFM
REFP
AVDD
AGND
AVDD
AGND
AVDD
AGND
AVDD
AGND
INM
INP
AGND
CM
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
PIN ASSIGNMENTS
TERMINAL
NO.
NAME
NO.
OF PINS
I/O
AVDD
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
12
I
Analog power supply
AGND
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
14
I
Analog ground
DRVDD
49, 58
2
I
Output driver power supply
DRGND
1, 42, 48, 50, 57, 59
6
I
Output driver ground
INP
19
1
I
Differential analog input (positive)
INM
20
1
I
Differential analog input (negative)
REFP
29
1
O
Reference voltage (positive), 0.1-µF capacitor in series with a 1-Ω
resistor to GND
REFM
30
1
O
Reference voltage (negative), 0.1-µF capacitor in series with a
1-Ω resistor to GND
IREF
31
1
I
Current set, 56-kΩ resistor to GND, do not connect capacitors
CM
17
1
O
Common-mode output voltage
RESET
35
1
I
Reset (active high), 200-kΩ resistor to AVDD
OE
41
1
I
Output enable (active high)
DFS
40
1
I
Data format and clock out polarity select(1)
CLKP
10
1
I
Data converter differential input clock (positive)
CLKM
11
1
I
Data converter differential input clock (negative)
SEN
4
1
I
Serial interface chip select
SDATA
3
1
I
Serial interface data
SCLK
2
1
I
Serial interface clock
44−47, 51−56, 60−63
14
O
Parallel data output
OVR
64
1
O
Over-range indicator bit
CLKOUT
43
1
O
CMOS clock out in sync with data
D0 (LSB)−D13 (MSB)
DESCRIPTION
NOTE: PowerPAD is connected to analog ground.
(1) The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are
listed in Table 3 on page 11.
12
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB
Aperture Delay
The delay in time between the falling edge of the input
sampling clock and the actual time at which the sampling
occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Width/Duty Cycle
A perfect differential sine−wave clock results in a 50%
clock duty cycle on the internal coversion clock. Pulse
width high is the minimum amount of time that the
ENCODE pulse should be left in logic 1 state to achieve
rated performance. Pulse width low is the minimum time
that the ENCODE pulse should be left in a low state (logic
0). At a given clock rate, these specifications define an
acceptable clock duty cycle.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly one
LSB apart. DNL is the deviation of any single LSB
transition at the digital output from an ideal one LSB step
at the analog input. If a device claims to have no missing
codes, it means that all possible codes (for a 14-bit
converter, 16384 codes) are present over the full operating
range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine−wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
ENOB + SINAD * 1.76
6.02
If SINAD is not known, SNR can be used exceptionally to
calculate ENOB (ENOBSNR).
Effective Resolution Bandwidth
The highest input frequency where the SNR (dB) is
dropped by 3 dB for a full-scale input amplitude
Gain Error
The amount of deviation between the ideal transfer
function and the measured transfer function (with the offset
error removed) when a full-scale analog input voltage is
applied to the ADC, resulting in all ones in the digital code.
Gain error is usually given in LSB or as a percent of
full-scale range (%FSR).
Integral Nonlinearity (INL)
The deviation of the transfer function from a reference line
measured in fractions of one LSB using a best straight line
or best fit determined by a least square curve fit. INL is
independent from effects of offset, gain, or quantization
errors.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
This is the maximum sampling rate where certified
operation is given.
Minimum Conversion Rate
The minimum sampling rate where the ADC still works.
Nyquist Sampling
When the sampled frequencies of the analog input signal
are below fCLOCK/2, it is called Nyquist sampling. The
Nyquist frequency is fCLOCK/2, which can vary depending
on the sample rate (fCLOCK).
Offset Error
The deviation of output code from mid-code when both
inputs are tied to common-mode
Propagation Delay
The delay between the input clock rising edge and the time
when all data bits are within valid logic levels
Signal-to-Noise and Distortion (SINAD)
The RMS value of the sine wave fIN (input sine wave for an
ADC) to the RMS value of the noise of the converter from
DC to the Nyquist frequency, including harmonic content.
It is typically expressed in decibels (dB). SINAD includes
harmonics, but excludes DC.
SINAD + 20Log (10)
Input(VS )
Noise ) Harmonics
Signal-to-Noise Ratio (Without Harmonics)
SNR is a measure of signal strength relative to background
noise. The ratio is usually measured in dB. If the incoming
signal strength in µV is VS, and the noise level (also in µV)
is VN, the SNR in dB is given by the formula:
SNR + 20Log (10)
VS
VN
This is the ratio of the RMS signal amplitude, VS (set one
dB below full-scale), to the RMS value of the sum of all
other spectral components, VN, excluding harmonics and
dc.
13
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Spurious-Free Dynamic Range (SFDR)
The ratio of the RMS value of the analog input sine wave
to the RMS value of the peak spur observed in the
frequency domain. It may be reported in dBc (that is, it
degrades as signal levels are lowered), or in dBFS (always
related back to converter full-scale). The peak spurious
component may or may not be a harmonic.
Temperature Drift
Temperature drift (for offset error and gain error) specifies
the maximum change from the initial temperature value to
the value at TMIN or TMAX.
14
Total Harmonic Distortion (THD)
The ratio of the RMS signal amplitude of the input sine
wave to the RMS value of distortion appearing at multiples
(harmonics) of the input, typically given in dBc
Two-Tone Intermodulation Distortion Rejection
The ratio of the RMS value of either input tone (f1, f2) to the
RMS value of the worst third-order intermodulation
product (2f1 − f2; 2f2 − f1). It is reported in dBc.
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
SPECTRAL PERFORMANCE
(FFT for 15MHz Input Signal)
SFDR = 84.0dBc
SNR = 71.2dBFS
THD = 84.0dBc
SINAD = 71.0dBFS
Amplitude (dB)
Amplitude (dB)
SPECTRAL PERFORMANCE
(FFT for 2MHz Input Signal)
40
50
60
Frequency (MHz)
0
10
20
Amplitude (dB)
Amplitude (dB)
30
40
50
60
Frequency (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
62.5
10
20
0
10
40
Amplitude (dB)
20
30
40
50
60
50
60
Frequency (MHz)
Amplitude (dB)
30
Frequency (MHz)
50
60
62.5
10
60
SPECTRAL PERFORMANCE
(FFT for 100MHz Input Signal)
SFDR = 84.4dBc
SNR = 71.2dBFS
THD = 81.3dBc
SINAD = 70.9dBFS
0
50
SFDR = 85.1dBc
SNR = 71.4dBFS
THD = 83.6dBc
SINAD = 71.1dBFS
SPECTRAL PERFORMANCE
(FFT for 80MHz Input Signal)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
40
SPECTRAL PERFORMANCE
(FFT for 70MHz Input Signal)
SFDR = 81.0dBc
SNR = 71.2dBFS
THD = 80.2dBc
SINAD = 70.7dBFS
0
30
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for 60MHz Input Signal)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
62.5
30
62.5
20
SFDR = 84.8dBc
SNR = 71.5dBFS
THD = 83.2dBc
SINAD = 71.2dBFS
62.5
10
62.5
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
SFDR = 84.3dBc
SNR = 71.1dBFS
THD = 81.6dBc
SINAD = 70.7dBFS
0
10
20
30
40
Frequency (MHz)
15
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
SPECTRAL PERFORMANCE
(FFT for 225MHz Input Signal)
SFDR = 77.8dBc
SNR = 70.0dBFS
THD = 75.3dBc
SINAD = 69.0dBFS
20
30
40
50
60
Frequency (MHz)
SFDR = 73.0dBc
SNR = 69.1dBFS
THD = 70.0dBc
SINAD = 66.5dBFS
0
10
SFDR = 67.4dBc
SNR = 68.0dBFS
THD = 64.7dBc
SINAD = 63.0dBFS
50
60
f1 = 10.1MHz, -7dBFS
f2 = 15.1MHz, -7dBFS
2−tone IMD = 88.0dBc
-20
-40
Power (dBFS)
Amplitude (dB)
40
TWO−TONE INTERMODULATION
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-60
-80
-100
-120
-140
30
40
50
60
Frequency (MHz)
0
10
20
30
40
50
60
60
62.5
20
62.5
10
62.5
0
Frequency (MHz)
TWO−TONE INTERMODULATION
TWO−TONE INTERMODULATION
0
0
f1 = 30.1MHz, -7dBFS
f2 = 35.1MHz, -7dBFS
2−tone IMD = 87.0dBc
- 20
f1 = 50.1MHz, -7dBFS
f2 = 55.1MHz, -7dBFS
2−tone IMD = 89.0dBc
-20
-40
Power (dBFS)
- 40
Power (dBFS)
30
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for 300MHz Input Signal)
- 60
- 80
-60
-80
-100
-100
-120
-120
-140
-140
10
20
30
40
Frequency (MHz)
50
60
62.5
0
16
20
62.5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
62.5
0
Amplitude (dB)
Amplitude (dB)
SPECTRAL PERFORMANCE
(FFT for 150MHz Input Signal)
0
10
20
30
40
Frequency (MHz)
50
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
DIFFERENTIAL NONLINEARITY (DNL)
INTEGRAL NONLINEARITY (INL)
Code
Code
SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY
90
76
85
74
80
72
SNR (dBFS)
SFDR (dBc)
SPURIOUS−FREE DYNAMIC RANGE vs
INPUT FREQUENCY
75
70
65
70
68
66
64
60
fS = 125MSPS
DLL On
55
fS = 125MSPS
DLL On
62
60
50
0
50
100
150
200
250
0
300
50
85
85
SNR (dBFS)
SFDR (dBc)
90
SFDR
75
SNR
70
fS = 125MSPS
fIN = 150MHz
DRVDD = 3.3V
65
150
200
250
300
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
90
80
100
Input Frequency (MHz)
Input Frequency (MHz)
SNR (dBFS)
SFDR (dBc)
16384
fS = 125MSPS
fIN = 10MHz
AIN = -0.5dBFS
14336
16384
10240
8192
6144
4096
2048
0
-1.50
14336
-1.25
12288
fS = 125MSPS
fIN = 10MHz
AIN = -0.5dBFS
-1.00
12288
-0.75
10240
-0.50
0
0
-0.25
8192
0.50
0.25
LSB
LSB
0.75
6144
1.00
4096
1.25
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
2048
1.50
SFDR
80
75
SNR
70
fS = 125MSPS
fIN = 70MHz
DRVDD = 3.3V
65
60
60
3.0
3.1
3.2
3.3
AVDD (V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AVDD (V)
17
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
79
84
78
SFDR
82
SFDR
77
80
SNR (dBFS)
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
76
fS = 125MSPS
fIN = 150MHz
AVDD = 3.3V
75
74
73
72
fS = 125MSPS
fIN = 70MHz
AVDD = 3.3V
78
76
74
71
SNR
72
70
SNR
70
69
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
DRVDD (V)
POWER DISSIPATION vs SAMPLE RATE
3.6
fIN = 70MHz
750
Power Dissipation (mW)
Power Dissipation (mW)
3.5
POWER DISSIPATION vs SAMPLING FREQUENCY
AVDD = DRVDD = 3.3V
fIN = 150MHz
800
750
700
650
600
DLL On
700
650
DLL Off
600
550
550
500
10
30
50
70
90
110
130
10
150
20
30
40
50
60
70
80
90 100 110 120
125
500
Sampling Frequency (MSPS)
Sample Rate (MSPS)
SIGNAL−TO−NOISE RATIO AND
SPURIOUS−FREE DYNAMIC RANGE vs TEMPERATURE
AC PERFORMANCE vs INPUT AMPLITUDE
90
90
SNR (dBFS)
80
70
AC Performance (dB)
85
SFDR
SNR (dBFS)
SFDR (dBc)
3.4
800
850
80
75
SNR
70
fS = 125MSPS
fIN = 70MHz
DLL On
65
-40
0
60
50
40
SFDR (dBc)
30
20
SNR (dBc)
10
0
fS = 125MSPS
fIN = 70MHz
DLL On
-10
-20
60
25
Temperature (_C)
18
3.3
DRVDD (V)
40
85
-30
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
AC PERFORMANCE vs INPUT AMPLITUDE
AC PERFORMANCE vs INPUT AMPLITUDE
90
90
SNR (dBFS)
80
70
60
AC Performance (dB)
AC Performance (dB)
SNR (dBFS)
80
70
SFDR (dBc)
50
40
30
SNR (dBc)
20
10
0
fS = 125MSPS
fIN = 150MHz
DLL On
-10
-20
-30
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
60
SFDR (dBc)
50
40
SNR (dBc)
30
20
10
0
fS = 125MSPS
f IN = 220MHz
DLL On
-10
-20
-30
0
-90
-80
-70
Input Amplitude (dBFS)
35
85
30
80
SNR (dBFS)
SFDR (dBc)
90
25
20
15
8222
8221
8220
8219
8218
8217
8216
50
8215
0
8214
55
8213
-10
0
SNR
65
5
8212
-20
70
60
8211
-30
SFDR
75
10
8210
-40
AC PERFORMANCE vs CLOCK AMPLITUDE
40
8209
-50
Input Amplitude (dBFS)
OUTPUT NOISE HISTOGRAM
Occurrence (%)
-60
fS = 125MSPS
fIN = 70MHz
0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude (V)
Output Code
WCDMA TONE
0
fS = 150MSPS
fIN = 125MHz
Amplitude (dB)
-20
-40
-60
-80
-100
-120
-140
0
10
20
30
40
50
60
Frequency (MHz)
19
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
SIGNAL−TO−NOISE RATIO (SNR) WITH DLL ON
73
150
71
140
71
72
69
130
71
71
110
69
72
70
70
100
90
69
72
80
73
70
69
68
71
68
69
73
68
70
60
70
72
67
69
50
SNR (dB)
Sample Frequency (MSPS)
120
71
72
40
0
69
50
100
150
67
68
200
250
66
300
Input Frequency (MHz)
SIGNAL−TO−NOISE RATIO (SNR) WITH DLL OFF
80
71
69
70
72
73
70
72
73
70
69
50
70
71
67
66
40
72
73
30
64
68
69
73
67
66
70
20
65
71
71
64
67
63
68
62
10
0
50
100
62
66
69
72
150
Input Frequency (MHz)
20
68
68
200
250
60
300
SNR (dB)
Sample Frequency (MSPS)
60
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On( unless
otherwise noted)
SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL ON
150
83
77
140
71
80
80
68
85
130
83
83
110
74
77
77
86
80
83
86
100
71
80
68
90 86
75
80
77
83
SFDR (dBc)
Sample Frequency (MSPS)
120
74
89
70
60
83
86
89
70
80
71
86
68
83
50
77
74
65
40
0
50
100
150
Input Frequency (MHz)
200
250
300
SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL OFF
88
80
78
88
86
80
70
84
84
88 86
86
82
84
76
88
60
74
82
86
72
50
78
80
80
70
68
78
76
86
40
86
76
82
SFDR (dBc)
Sample Frequency (MSPS)
70
74
74
30
72
72
84
88
20
80
86
70
78
84
76 74
82
70
68
68
72
70
66
10
0
50
100
150
200
250
300
Input Frequency (MHz)
21
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
SECOND HARMONIC (HD2) WITH DLL ON
150
83
86
140
98 89
130
92
89
100
92
89
80 77
80
83
83
68
95
98
70
74
86
92
89
85
71
89
80
90
83
86
95
86
98
90
77
80
89
86
92
95
74
92
120
Sample Frequency (MSPS)
92
86
86
110
68
80
71
89
89
77
83
86
77
86
89
HD2 (dBc)
86
95
74
71
75
60
92
98 95
92
50
92
70
83
68
98 95
89
95
86
80
77
74
71
40
65
0
50
100
150
200
250
300
Input Frequency (MHz)
SECOND HARMONIC (HD2) WITH DLL OFF
90 87 84
93
70
95
93
96
99
96
78
60
Sample Frequency (MSPS)
68
81
90
75
99
87
50
93
99
40
85
68
81
99
99
80
90
96
78
75
99
30
84
72
72
87
75
84
81
93
20
68
78
84
70
72
87
75
10
0
50
100
150
Input Frequency (MHz)
22
200
250
300
HD2 (dBc)
80
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
otherwise noted)
THIRD HARMONIC (HD3) WITH DLL ON
150
83
77
80
89
140
71
74
68
90
86
86
130
86
83
85
86
89
83
110
80
77
86
71
77
74
80
77
100
80
86
90
83
83
86
89
80
75
92
89
70
86
86
92
60
HD3 (dBc)
120
70
86
50
83
83
89
86
89
40
65
0
50
100
150
200
250
300
Input Frequency (MHz)
THIRD HARMONIC (HD3) WITH DLL OFF
80
87
90
87 84
90
90
70
81
78
84
78
60
87
72
75
50
40
80
78
84 81
87
HD3 (dBc)
Sample Frequency (MSPS)
85
84
75
30
75
87
84
90
20
72
84
81
78
70
81
84
10
0
50
100
72
75
87
150
200
72
250
300
Input Frequency (MHz)
23
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
APPLICATION INFORMATION
through the pipeline every half clock cycle. This process
results in a data latency of 16.5 clock cycles, after which
the output data is available as a 14-bit parallel word,
coded in either straight offset binary or binary
twos−complement format.
INPUT CONFIGURATION
The analog input for the ADS5500 consists of a
differential architecture implemented using a switched
capacitor technique, shown in Figure 5.
SAMPLE W
3a
PHASE
SAMPLE
PHASE
SWITCH
THEORY OF OPERATION
The ADS5500 is a low-power, 14-bit, 125−MSPS,
CMOS, switched−capacitor, pipeline ADC that
operates from a single 3.3-V supply. The conversion
process is initiated by a falling edge of the external input
clock. Once the signal is captured by the input S&H, the
input sample is sequentially converted by a series of
small resolution stages, with the outputs combined in a
digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample
W1a
L1
R1a
C1a
INP
CP1
CP3
L2
SWITCH
SAMPLE
W2
PHASE
R1b
R3
SWITCH
CACROSS
C1b
VINCM
1V
INM
W1b
SAMPLE
PHASE
CP4
SAMPLE W
3a
PHASE
L1, L2 : 6nh to 10nh effective
R1a, R1b : 25W to 35W
C1a, C1b : 2.2pF to 2.6pF
CP1, CP2 : 2.5pF to 3.5pF
CP3, CP4, : 1.2pF to 1.8pF
CACROSS : 0.8pF to 1.2pF
R3 : 80W to 120W
Switches: W1a, W1b : On Resistance: 25Wto 35W
W2 : On Resistance: 7.5W to 15W
W3a, W3b : On Resistance: 40Wto 60W
W1a, W1b, W2, W3a, W3b : Off Resistance: 1e10
All switches are on in sample phase.
Approximately half of every clock period is a sample phase.
Figure 5. Analog Input Stage
24
SWITCH
CP2
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
This differential input topology produces a high level of
ac performance for high sampling rates. It also results
in a high usable input bandwidth, especially important
for high intermediate frequency (IF) or undersampling
applications. The ADS5500 requires each of the analog
inputs (INP, INM) to be externally biased around the
common-mode level of the internal circuitry (CM, pin
17). For a full-scale differential input, each of the
differential lines of the input signal (pins 19 and 20)
swings symmetrically between CM + 0.575 V and CM
– 0.575 V. This means that each input is driven with a
signal of up to CM ± 0.575 V, so that each input has a
maximum differential signal of 1.15 VPP for a total
differential input signal swing of 2.3 VPP. The maximum
swing is determined by the two reference voltages − the
top reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
The ADS5500 obtains optimum performance when the
analog inputs are driven differentially. The circuit shown
in Figure 6 shows one possible configuration using an
RF transformer.
R0
50W
Z0
50W
INP
1:1
R
50W
AC Signal
Source
ADS5500
INM
ADT1−1WT
CM
10W
1nF
0.1mF
Figure 6. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of
an RF transformer. Since the input signal must be
biased around the common-mode voltage of the
internal circuitry, the common-mode voltage (VCM) from
the ADS5500 is connected to the center tap of the
secondary winding. To ensure a steady low-noise VCM
reference, best performance is obtained when the CM
(pin 17) output is filtered to ground with 0.1−µF and
0.01-µF low-inductance capacitors.
Output VCM (pin 17) is designed to directly drive the
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 4 mA (2 mA per
input). Equation 1 describes the dependency of the
common-mode current and the sampling frequency:
4mA f s
125MSPS
(1)
Where: fS > 60 MSPS.
This equation designs the output capability and
impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer or to use a differential input/output amplifier
without a transformer to drive the input of the ADS5500.
Texas Instruments offers a wide selection of
single-ended operational amplifiers (including the
THS3201, THS3202, OPA847, and OPA695) that can
be selected, depending on the application. An RF gain
block amplifier, such as the TI THS9001, can also be
used with an RF transformer for very high input
frequency applications. The THS4503 is a
recommended differential input/output amplifier.
Table 4 lists the recommended amplifiers.
When using single-ended operational amplifiers (such
as the THS3201, THS3202, OPA847, or OPA695) to
provide gain, a three-amplifier circuit is recommended
with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the
secondary driving the two differential inputs of the
ADS5500. These three amplifier circuits minimize
even-order harmonics. For high frequency inputs, an
RF gain block amplifier can be used to drive a
transformer primary; in this case, the transformer
secondary connections can drive the input of the
ADS5500 directly (see Figure 6) or with the addition of
the filter circuit (see Figure 7).
Figure 7 shows how RIN and CIN can be placed to isolate
the signal source from the switching inputs of the ADC
and to implement a low-pass RC filter to limit the input
noise in the ADC. It is recommended that these
components be included in the ADS5500 circuit layout
when any of the amplifier circuits discussed previously
are used. The components allow fine tuning of the
circuit performance. Any mismatch between the
differential lines of the ADS5500 input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even-order
harmonics. In this case, special care should be taken to
keep as much electrical symmetry as possible between
both inputs.
Another possible configuration for lower-frequency
signals is the use of differential input/output amplifiers
that can simplify the driver circuit for applications
requiring dc coupling of the input. Flexible in their
configurations (see Figure 8), such amplifiers can be
used for single-ended-to-differential conversion signal
amplification.
25
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Table 4. Recommended Amplifiers to Drive Input of ADS5500
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
TYPE OF AMPLIFIER
DC to 20 MHz
THS4503 (1)
Differential in/out amplifier
No
DC to 50 MHz
OPA847 (1)
Operational amplifier
Yes
OPA695 (1)
Operational amplifier
Yes
THS3201 (1)
Operational amplifier
Yes
THS3202 (1)
Operational amplifier
Yes
THS9001 (1)
RF gain block
Yes
10 MHz to 120 MHz
Over 100 MHz
USE WITH TRANSFORMER?
(1) Potential EP devices
+5V -5V
RS
100W
VIN
0.1mF
RIN
1:1
OPA695
INP
RT
100W
1000pF
R1
400W
RIN
CIN
ADS5500
INM
CM
R2
57.5W
AV = 8V/V
(18dB)
10W
0.1mF
Figure 7. Converting Single-Ended Input Signal to Differential Signal Using an RF Transformer
RS
RG
RF
+5V
RT
+3.3V
10mF
0.1mF
R IN
INP
VOCM
R IN
ADS5500
14−Bit/125MSPS
INM
1mF
THS4503
10mF
CM
0.1mF
10W
-5V
RG
RF
0.1mF
Figure 8. Using THS4503 With ADS5500
POWER−SUPPLY SEQUENCE
The ADS5500 requires a power-up sequence where the
DRVDD supply must be at least 0.4 V by the time the
AVDD supply reaches 3 V. Powering up both supplies at
26
the same time works without any problem. If this
sequence is not followed, the device may stay in
power-down mode.
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
POWER DOWN
CLOCK INPUT
The device enters power down in one of two ways −
either by reducing the clock speed to between dc and
1 MHz, or by setting a bit through the serial
programming interface. Using the reduced clock speed,
the power down may be initiated for clock frequencies
below 10 MHz. For clock frequencies between 1 MHz
and 10 MHz, this can vary from device to device, but will
power down for clock speeds below 1 MHz.
The ADS5500 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5-kΩ
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17) (see Figure 10).
The device can be powered down by programming the
internal register (see Serial Programming Interface
section). The outputs become 3-stated and only the
internal reference is powered up to shorten the
power-up time. The power-down mode reduces power
dissipation to a minimum of 180 mW.
CM
CM
5kW
5kW
CLKP
CLKM
REFERENCE CIRCUIT
The ADS5500 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1−µF
decoupling capacitor in series with a 1-Ω resistor (see
Figure 9). In addition, an external 56.2-kΩ resistor
should be connected from IREF (pin 31) to AGND to set
the proper current for the operation of the ADC (see
Figure 9). No capacitor should be connected between
pin 31 and ground; only the 56.2-kΩ resistor should be
used.
1W
29
REFP
30
REFM
1mF
6pF
3pF
3pF
Figure 10. Clock Inputs
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01-µF capacitor, while CLKP is ac coupled with a
0.01-µF capacitor to the clock source (see Figure 11).
Square Wave
or Sine Wave
(3VPP)
0.01mF
CLKP
ADS5500
1W
CLKM
1mF
0.01mF
31
IREF
56kW
Figure 9. REFP, REFM, and IREF Connections for
Optimum Performance
Figure 11. AC-Coupled Single-Ended Clock Input
The ADS5500 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01-µF
capacitors (see Figure 12).
0.01mF
CLKP
Differential Square Wave
or Sine Wave
(3VPP)
ADS5500
0.01mF
CLKM
Figure 12. AC-Coupled Differential Clock Input
27
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 50%
duty cycle should be provided. Figure 13 shows the
performance variation of the ADC versus clock duty
cycle.
90
fS = 125MSPS
fIN = 20MHz
AC PERFORMANCE vs CLOCK AMPLITUDE
90
SFDR
SFDR
85
80
80
SNR (dBFS)
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
85
amplitudes without exceeding the supply rails and
absolute maximum ratings of the ADC clock input.
Figure 14 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, see the ADS5500EVM user’s guide
(SLWU010), available for download from www.ti.com.
75
SNR
70
75
SNR
70
65
60
65
fS = 125MSPS
fIN = 70MHz
55
60
30
35
40
45
50
55
60
65
70
Clock Duty Cycle (%)
50
0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude (V)
Figure 13. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter further
improves as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
28
Figure 14. AC Performance vs Clock Amplitude
INTERNAL DLL
In order to obtain the fastest sampling rates achievable
with the ADS5500, the device uses an internal digital
phase lock loop (DLL). Nevertheless, the limited
frequency range of operation of DLL degrades the
performance at clock frequencies below 60 MSPS. In
order to operate the device below 60 MSPS, the internal
DLL must be shut off using the DLL OFF mode
described in the Serial Interface Programming section.
The Typical Performance Curves show the
performance obtained in both modes of operation − DLL
ON (default) and DLL OFF. In either of the two modes,
the device enters power-down mode if no clock or a
slow clock is provided. The limit of the clock frequency
where the device functions properly is ensured to be
over 10 MHz.
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
OUTPUT INFORMATION
SERIAL PROGRAMMING INTERFACE
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
The ADS5500 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power up by applying a 2−µs (minimum) high pulse on
RESET (pin 35); this also resets the entire ADC and
sets the data outputs to low. This pin has a 200-kΩ
internal pullup resistor to AVDD. The programming is
done through a three-wire interface. The timing diagram
and serial register setting in the Serial Programing
Interface section describe the programming of this
register.
Two different output formats (straight offset binary or
twos complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to 3-state the outputs.
The output circuitry of the ADS5500 has being designed
to minimize the noise produced by the transients of the
data switching, and in particular its coupling to the ADC
analog circuitry. Output D4 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
rate described in the timing diagram of Figure 2, as long
as all outputs (including CLKOUT) have a similar load
as the one at D4 (pin 51). This circuit also reduces the
sensitivity of the output timing versus supply voltage or
temperature. External series resistors with the output
are not necessary.
Table 2 shows the different modes and the bit values to
be written on the register to enable them.
Note that some of these modes may modify the
standard operation of the device and possibly vary the
performance, with respect to the typical data shown in
this data sheet.
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
ADS5500MPAPEP
ACTIVE
HTQFP
PAP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5500MEP
ADS5500MPAPREP
ACTIVE
HTQFP
PAP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5500MEP
V62/05613-01XE
ACTIVE
HTQFP
PAP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5500MEP
V62/05613-02XE
ACTIVE
HTQFP
PAP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5500MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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