ADS5510IPAPRG4

Burr Brown Products from Texas Instruments ADS5510 SLAS499 – JANUARY 2007 11-Bit, 125-MSPS Analog-To-Digital Converter FEATURES • • • • • • • • • • • 11-bit Resolution 125-MSPS Sample Rate High SNR: 66.3 dBFS at 100 MHz fIN High SFDR: 81 dBc at 100 MHz fIN 2.3-VPP Differential Input Voltage Internal Voltage Reference 3.3-V Single-Supply Voltage Analog Power Dissipation: 578 mW Serial Programming Interface TQFP-64 PowerPAD™ Package Pin-Compatible With: – ADS5500 (14-Bit, 125 MSPS) – ADS5541 (14-Bit, 105 MSPS) – ADS5542 (14-Bit, 80 MSPS) – ADS5520 (12-Bit, 125 MSPS) – ADS5521 (12-Bit, 105 MSPS) – ADS5522 (12-Bit, 80 MSPS) • Recommended Operational Amplifiers: THS3201, THS3202, THS4503, THS4509, THS9001, OPA695, OPA847 APPLICATIONS • Wireless Communication – Communication Receivers – Base Station Infrastructure Test and Measurement Instrumentation Single and Multichannel Digital Receivers Communication Instrumentation – Radar – Infrared Video and Imaging Medical Equipment • • • • • DESCRIPTION The ADS5510 is a high-performance, 11 bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5510 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5510 is available in 64-pin TQFP PowerPAD package over the industrial temperature range. AVDD CLK+ CLK− DRVDD Timing Circuitry CLKOUT VIN+ VIN− S&H 11-Bit Pipeline ADC Core Digital Error Correction Output Control D0 . . . D10 OVR DFS CM Internal Reference Control Logic Serial Programming Register ADS5510 DRGND A GND SEN SDATA SCLK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS5510 www.ti.com SLAS499 – JANUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD HTQFP-64 (2) PowerPAD PACKAGE DESIGNATOR PAP SPECIFIED TEMPERATURE RANGE –40°C to 85°C PACKAGE MARKING ADS5510I ORDERING NUMBER ADS5510IPAP ADS5510IPAPR TRANSPORT MEDIA, QUANTITY Tray, 160 Tape and Reel, 1000 ADS5510 (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VSS Supply Voltage Analog input to AGND (2) (3) Logic input to DRGND Digital data output to DRGND Operating temperature range TJ Tstg Junction temperature Storage temperature range AVDD to AGND, DRVDD to DRGND AGND to DRGND –0.3 to 3.7 ±0.1 –0.3 to minimum (AVDD + 0.3, 3.6) –0.3 to DRVDD –0.3 to DRVDD –40 to 85 105 –65 to 150 V V V V V °C °C °C (1) (2) (3) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ω should be added in series with each of the analog input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle of the overshoot should be limited to less than 5% for inputs up to 3.9 V. The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a percentage. The total time of overshoot is the integrated time of all overshoot occurrences over the lifetime of the device. RECOMMENDED OPERATING CONDITIONS PARAMETER Supplies AVDD DRVDD Analog supply voltage Output driver supply voltage 3 3 3.3 3.3 3.6 3.6 V V MIN TYP MAX UNIT Analog input Differential input range VCM Input common-mode voltage (1) 1.45 2.3 1.55 1.65 VPP V Digital Output Maximum output load Clock Input ADCLK input sample rate (sine wave) 1/tC Clock amplitude, sine wave, differential Clock duty cycle TA Open free-air temperature range –40 DLL ON DLL OFF 60 2 1 3 50% 85 °C 125 80 MSPS VPP 10 pF (1) 2 Input common-mode should be connected to CM. Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 ELECTRICAL CHARACTERISTICS Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1 dBFS differential input, unless otherwise noted PARAMETER Resolution Analog Inputs Differential input range Differential input impedance Differential input capacitance Analog input common-mode current (per input) Analog input bandwidth Voltage overload recovery time Internal Reference Voltages V(REFM) V(REFP) Reference bottom voltage Reference top voltage Reference error VCM Common-mode voltage output –4% 0.95 2.1 ±0.9% 1.55 ±0.05 Tested fIN = 10 MHz fIN = 10 MHz -0.5 -1.5 -11 ∆offset error/∆AVDD from AVDD = 3 V to AVDD = 3.6 V -2 ±0.25 ±0.8 +2.5 0.01 0.25 ±0.45 0.01 fIN = 10 MHz fIN = 70 MHz SNR Signal-to-noise ratio fIN = 100 MHz fIN = 130 MHz fIN = 170 MHz fIN = 10 MHz fIN = 70 MHz SFDR Spurious-free dynamic range fIN = 100 MHz fIN = 130 MHz fIN = 170 MHz fIN = 10 MHz fIN = 70 MHz HD2 Second-harmonic fIN = 100 MHz fIN = 130 MHz fIN = 170 MHz 73 73 62.5 66.7 66.5 66.3 66 65.5 84 81 82 78 72 91 87 84 79 74 dBc dBc dBFS +2 0.5 1.5 +11 LSB LSB mV mV/°C mV/V %FS ∆%/°C 4% V V V Source impedance = 50 Ω See Figure 24 See Figure 24 2.3 6.6 4 300 750 4 VPP kΩ pF µA MHz Clock cycles CONDITIONS MIN TYP 11 MAX UNIT bits Dynamic DC Characteristics and Accuracy No missing codes DNL INL Differential nonlinearity error Integral nonlinearity error Offset error Offset temperature coefficient PSRR DC power-supply rejection ratio Gain error (1) Gain temperature coefficient Dynamic AC Characteristics (1) Gain error is specified by design and characterization; it is not tested in production. Submit Documentation Feedback 3 ADS5510 www.ti.com SLAS499 – JANUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1 dBFS differential input, unless otherwise noted PARAMETER fIN = 10 MHz fIN = 70 MHz HD3 Third-harmonic fIN = 100 MHz fIN = 130 MHz fIN = 170 MHz fIN = 10 MHz fIN = 70 MHz SINAD Signal-to-noise + distortion fIN = 100 MHz fIN = 130 MHz fIN = 170 MHz ENOB IMD PSRR ICC I(AVDD) I(DRVDD) Effective number of bits Two-tone intermodulation distortion AC power supply rejection ratio Total supply current Analog supply current Output buffer supply current Power dissipation Standby power fIN = 10 MHz f = 50.1 MHz, 46.1 MHz (-7 dBFS each tone) Supply noise frequency ≤ 100 MHz fIN = 10 MHz fIN = 10 MHz fIN = 10 MHz Analog only Output buffer power with 10-pF load on digital output to ground With Clocks running 10.0 62 CONDITIONS MIN 73 TYP 84 81 82 78 72 66.5 66.3 66 65.6 65 10.8 85 35 236 175 61 578 202 180 260 190 70 627 231 250 mW mW Bits dBFS dB mA mA mA dBFS dBc MAX UNIT Power Supply 4 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 DIGITAL CHARACTERISTICS Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted PARAMETER Digital Inputs VIH VIL IIH IIL High-level input voltage Low-level input voltage High-level input current Low-level input current Input current for RESET Input capacitance Digital Outputs VOL VOH Low-level output voltage High-level output voltage Output capacitance CLOAD = 10 pF CLOAD = 10 pF 2.4 0.3 3 3 0.4 V V pF –20 4 2.4 0.8 10 -10 V V µA µA µA pF CONDITIONS MIN TYP MAX UNIT Submit Documentation Feedback 5 ADS5510 www.ti.com SLAS499 – JANUARY 2007 TIMING CHARACTERISTICS (1) (2) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless otherwise noted PARAMETER Switching Specification tA tSETUP tHOLD tSTART tEND tJIT tr tf tPDI tr tf Aperture delay Aperture jitter (uncertainty) Data setup time Data hold time Input clock to output data valid start (4) (5) Input clock to output data valid end (4) (5) Output clock jitter Output clock rise time Output clock fall time Input clock to output clock delay Data rise time Data fall time Output enable(OE) to data output delay Input CLK falling edge to data sampling point Uncertainty in sampling instant Data valid (3) to 50% of CLKOUT rising edge 2.3 1.7 50% of CLKOUT rising edge to data becoming invalid (3) Input clock rising edge to data valid start delay Input clock rising edge to data valid end delay Uncertainty in CLKOUT rising edge, peak-to-peak Rise time of CLKOUT from 20% to 80% of DRVDD Fall time of CLKOUT from 80% to 20% of DRVDD Input clock rising edge, zero crossing, to output clock rising edge 50% Data rise time measured from 20% to 80% of DRVDD Data fall time measured from 80% to 20% of DRVDD Time required for outputs to have stable timings with regard to input clock (6) after OE is activated Time to valid data after coming out of software power down Time to valid data after stopping and restarting the clock Time for a sample to propagate to the ADC outputs 17.5 4.2 5.8 1 300 2.7 2 2 6.9 150 1.7 1.5 4.8 3.6 2.8 210 1.9 1.7 5.5 4.6 3.7 1000 1000 1000 Clock cycles Clock cycles 2.6 ns fs ns ns ns ns psPP ns ns ns ns ns Clock cycles DESCRIPTION MIN TYP MAX UNIT Wakeup time Latency (1) (2) (3) (4) (5) (6) Timing parameters are ensured by design and characterization, and not tested in production. See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies. Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW. See the Output Information section for details on using the input clock for data capture. These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid number for a falling edge CLKOUT polarity. Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect to input clock. 6 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Analog Input Signal Sample N N+1 N+2 N+3 N+4 N + 14 N + 15 N + 16 N + 17 tA Input Clock Output Clock tSTART tPDI tsu Data Out (D0−D10) N − 17 N − 16 N − 15 N − 14 N − 13 N−3 N−2 N−1 N tEND Data Invalid 17.5 Clock Cycles th A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. Figure 1. Timing Diagram RESET TIMING CHARACTERISTICS Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted PARAMETER Switching Specification t1 t2 t3 Power-on delay Reset pulse width Register write delay Power-up time Delay from power-on of AVDD and DRVDD to RESET pulse active Pulse width of active RESET signal Delay from RESET disable to SEN active Delay from power-up of AVDD and DRVDD to output stable 10 2 2 40 ms µs µs ms DESCRIPTION MIN TYP MAX UNIT Power Supply (AVDD, DRVDD) t1 . 10 ms t2 . 2 ms RESET (Pin 35) t3 . 2 ms SEN Active Figure 2. Reset Timing Diagram Submit Documentation Feedback 7 ADS5510 www.ti.com SLAS499 – JANUARY 2007 SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The ADS5510 has a three-wire serial interface. The ADS5510 latches serial data SDATA on the falling edge of serial clock SCLK when SEN is active. • Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge. • Minimum width of data stream for a valid loading is 16 clocks. • Data is loaded at every 16th SCLK falling edge while SEN is low. • In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. • Data can be loaded in multiples of 16-bit words within a single active SEN pulse. • The first 4-bit nibble is the address of the register while the last 12 bits are the register contents. SDATA A3 A2 A1 A0 D11 D10 D9 DATA D0 ADDRESS MSB Figure 3. DATA Communication is 2-Byte, MSB First tSLOADS tWSCLK tWSCLK SCLK tsu(D) SDATA MSB th(D) LSB 16 x M SEN tSLOADH tSCLK MSB LSB Figure 4. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics SYMBOL tSCLK tWSCLK tSLOADS tSLOADH tDS tDH (1) PARAMETER SCLK period SCLK duty cycle SEN to SCLK setup time SCLK to SEN hold time Data setup time Data hold time MIN (1) 50 25% 8 6 8 6 50% 75% ns ns ns ns TYP (1) MAX (1) UNIT ns Typ, min, and max values are characterized, but not production tested. 8 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Table 2. Serial Register Table A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DLL CTRL 1 1 1 1 0 0 1 1 0 0 0 0 TP 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PDN 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0 0 0 1 1 0 0 TP 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 D0 (1) DESCRIPTION Clock DLL Internal DLL is on; recommended for 60 MSPS to 125 MSPS clock speeds. Internal DLL is off; recommended for 2 MSPS to 80 MSPS clock speeds. Test Mode Normal mode of operation All outputs forced to 0 All outputs forced to 1 Each output bit toggles between 0 and 1. Power Down Normal mode of operation Device is put in power-down (low-current) mode. (2) (3) (1) (2) (3) The register contents default to the appropriate setting for normal operation up on RESET. The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section. While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D10. For example, when D0 is a 1, D1 in not assured to be a 0, and vice versa. Table 3. Data Format Select (DFS) Table DFS-PIN VOLTAGE (VDFS) V DFS t 4 12 7 12 2 12 AV DD AV DD AV DD DATA FORMAT Straight Binary Two's Complement Straight Binary Two's Complement CLOCK OUTPUT POLARITY Data valid on rising edge Data valid on rising edge Data valid on falling edge Data valid on falling edge 5 AV DD t V DFS t 12 8 AV DD t V DFS t 12 10 12 AV DD V DFS u Submit Documentation Feedback 9 ADS5510 www.ti.com SLAS499 – JANUARY 2007 PIN CONFIGURATION PAP PACKAGE HTQFP-64 (TOP VIEW) D10 (MSB) DRVDD DRVDD 49 48 DRGND 47 D0 (LSB) 46 NC 45 NC 44 NC 43 CLKOUT 42 DRGND 41 OE 40 DFS 39 AVDD 38 AGND 37 AVDD 36 AGND 35 RESET 34 AVDD 33 AVDD 17 CM 18 AGND 19 INP 20 INM 21 AGND 22 AVDD 23 AGND 24 AVDD 25 AGND 26 AVDD 27 AGND 28 AVDD 29 REFP 30 REFM 31 IREF 32 AGND DRGND DRGND 64 DRGND SCLK SDATA SEN AVDD AGND AVDD AGND AVDD 1 2 3 4 5 6 7 8 9 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ADS5510 PowerPAD CLKP 10 CLKM 11 AGND 12 AGND 13 AGND 14 AVDD 15 AGND 16 10 Submit Documentation Feedback DRGND OVR D9 D8 D7 D6 D5 D4 D3 D2 D1 ADS5510 www.ti.com SLAS499 – JANUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS (1) TERMINAL NAME AVDD NO. 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 6, 8, 12, 13, 14, 16, 18, 21, 23, 25, 27, 32, 36, 38 49, 58 1, 42, 48, 50, 57, 59 44, 45, 46 19 20 29 30 31 17 35 41 40 10 11 4 3 2 47, 51-56, 60-63 64 43 NO. OF PINS 12 I/O I DESCRIPTION Analog power supply AGND DRVDD DRGND NC INP INM REFP REFM IREF CM RESET OE DFS CLKP CLKM SEN SDATA SCLK D0 (LSB) to D10 (MSB) OVR CLKOUT (1) (2) (3) (4) 14 2 6 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 I I I — I I O O I O I I I I I I I I O O O Analog ground Output driver power supply Output driver ground Not connected Differential analog input (positive) Differential analog input (negative) Reference voltage (positive); 0.1-µF capacitor in series with a 1-Ω resistor to GND Reference voltage (negative); 0.1-µF capacitor in series with a 1-Ω resistor to GND Current set; 56-kΩ resistor to GND; do not connect capacitors Common-mode output voltage Reset (active high), 200-kΩ resistor to AVDD (2) Output enable (active high) Data format and clock out polarity select (3) (4) Data converter differential input clock (positive) Data converter differential input clock (negative) Serial interface chip select (4) Serial interface data (4) Serial interface clock (4) 11 bit parallel data output Over-range indicator bit CMOS clock out in sync with data PowerPAD is connected to analog ground. If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details. Table 3 defines the voltage levels for each mode selectable via the DFS pin. Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins must also run off the same supply voltage as DRVDD. Submit Documentation Feedback 11 ADS5510 www.ti.com SLAS499 – JANUARY 2007 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error does not account for variations in the internal reference voltages (see the Electrical Specifications section for limits on the variation of VREFP and VREFM). Offset Error The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference (TMAX – TMIN). Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first eight harmonics. P SNR + 10Log 10 S PN SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to Full-Scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10Log 10 PN ) PD SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Number of Bits (ENOB) The ENOB is a measure of a converter's performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 12 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first eight harmonics (PD). P THD + 10Log 10 S PD THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion (IMD3) IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to Full-Scale) when the power of the fundamental is extrapolated to the converter's full-scale range. DC Power Supply Rejection Ration (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. Reference Error The reference error is the variation of the actual reference voltage (VREFP - VREFM) from its ideal value. The reference error is typically given as a percentage. Voltage Overload Recovery Time The voltage overload recovery time is defined as the time required for the ADC to recover to within 1% of the full-scale range in response to an input voltage overload of 10% beyond the full-scale range. Submit Documentation Feedback 13 ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 125 MSPS, DLL On, and 3-V differential clock, unless otherwise noted SPECTRAL PERFORMANCE (FFT for 20 MHZ input signal) 0 -20 0 SPECTRAL PERFORMANCE (FFT for 40 MHZ input signal) SFDR = 80.21 dBc, SNR = 66.84 dBFS, SINAD = 66.47 dBFS Amplitude - dB -60 -80 -100 -120 -140 0 Amplitude - dB -40 SFDR = 83.8 dBc, SNR = 66.87 dBFS, SINAD = 66.67dBFS -20 -40 -60 -80 -100 -120 -140 10 20 30 40 50 60 0 10 20 30 40 50 60 f - Frequency - MHz f - Frequency - MHz Figure 5. SPECTRAL PERFORMANCE (FFT for 70 MHZ input signal) 0 -20 0 Figure 6. SPECTRAL PERFORMANCE (FFT for 100 MHZ input signal) SFDR = 80.8 dBc, SNR = 67.47 dBFS, SINAD = 66.16 dBFS Amplitude - dB -60 -80 -100 -120 -140 0 Amplitude - dB -40 SFDR = 80.98 dBc, SNR = 66.76 dBFS, SINAD = 66.46 dBFS -20 -40 -60 -80 -100 -120 -140 10 20 30 40 50 60 0 10 20 30 40 50 60 f - Frequency - MHz f - Frequency - MHz Figure 7. SPECTRAL PERFORMANCE (FFT for 150 MHZ input signal) 0 -20 0 Figure 8. SPECTRAL PERFORMANCE (FFT for 170 MHZ input signal) SFDR = 69.93 dBc, SNR = 65.58 dBFS, SINAD = 63.41dBFS Amplitude - dB -60 -80 -100 -120 -140 0 Amplitude - dB -40 SFDR = 78.62 dBc, SNR = 66.15 dBFS, SINAD = 65.58 dBFS -20 -40 -60 -80 -100 -120 -140 10 20 30 40 50 60 0 10 20 30 40 50 60 f - Frequency - MHz f - Frequency - MHz Figure 9. Figure 10. 14 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 125 MSPS, DLL On, and 3-V differential clock, unless otherwise noted SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 90 fIN1 = 50.1 MHz, -7 dBFS, fIN2 = 46.1 MHz, -7 dBFS, SFDR = -90 dBFS, 2-Tone IMD, -85 dBFS TWO-TONE INTERMODULATION 0 -20 86 82 Amplitude - dB -40 -60 -80 -100 -120 -140 0 SFDR - dBc 78 74 70 66 62 10 20 30 40 50 60 0 50 100 150 200 230 f - Frequency - MHz fIN - Input Frequency - MHz Figure 11. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 78 74 89 FIN = 70 MHz 86 DRVDD = 3.3 V Figure 12. AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE 70 69 68 67 SNR 77 74 3 66 65 3.1 3.2 3.3 3.4 3.5 3.6 AVDD - Supply Voltage - V SNR − dBFS SFDR - dBc 70 66 62 58 0 200 50 100 150 fIN − Input Frequency − MHz 230 83 80 Figure 13. AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE 89 86 fIN = 70 MHz AVDD = 3.3 V 70 69 86 Figure 14. AC PERFORMANCE vs TEMPERATURE 70 fIN = 70 MHz 83 69 68 67 SNR 66 65 85 SNR − dBFS SFDR − dBc 83 SFDR 80 SNR 77 74 3.0 3.1 3.2 3.3 3.4 3.5 3.6 DRVDD − Supply Voltage − V 68 67 66 65 80 77 74 71 −40 −15 10 35 o 50 TA − Free-Air Temperature − C Figure 15. Submit Documentation Feedback Figure 16. 15 SNR − dBFS SFDR − dBc SFDR SNR - dBFS SFDR ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 125 MSPS, DLL On, and 3-V differential clock, unless otherwise noted AC PERFORMANCE vs INPUT AMPLITUDE 105 95 fIN = 70 MHz SFDR (dBFS) AC PERFORMANCE vs CLOCK AMPLITUDE 71 70 69 76 69 SFDR 80 70 SFDR − dBc, dBFS 85 75 65 55 45 35 25 −50 −40 −30 −20 −10 0 SFDR (dBc) SNR (dBFS) SNR − dBFS SFDR - dBc 68 66 65 64 63 62 72 fIN = 70 MHz 68 67 SNR 68 64 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Clock Amplitude - VPP 66 65 1.6 Input Amplitude − dBFS Figure 17. AC PERFORMANCE vs CLOCK DUTY CYCLE 84 fIN = 10 MHz Figure 18. OUTPUT NOISE vs HISTOGRAM 80 76 Occurence − % 100 90 80 70 60 50 40 30 20 10 0 80 76 72 SNR 72 68 64 60 35 40 45 50 55 60 65 Input Clock Duty Cycle − % 68 64 SNR − dBFS SFDR − dBc SFDR 1025 1026 1027 1028 1023 1024 Output Code Figure 19. POWER DISSIPATION vs SAMPLE RATE 1 0.9 fIN = 70 MHz 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 100 110 120 130 Figure 20. Total Power - W Sampling Frequency - MSPS Figure 21. 16 Submit Documentation Feedback 1029 1030 SNR - dBFS ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, and 3-V differential clock, unless otherwise noted DLL ON for FS > 80 MSPS DLL OFF for FS ≤ 80 MSPS 125 120 fS - Sampling Frequency - MSPS 110 100 90 80 70 60 50 40 20 40 60 80 100 120 140 160 180 200 210 fIN - Input Frequency - MHz 72 74 76 78 80 82 84 86 88 90 SFDR - dBc Figure 22. SFDR Contour in dBc 125 120 fS - Sampling Frequency - MSPS 110 100 90 80 70 60 50 40 20 40 60 80 100 120 140 160 180 200 210 fIN - Input Frequency - MHz 64.5 65 65.5 SNR - dBFS 66 66.5 67 Figure 23. SNR Contour in dBFS Submit Documentation Feedback 17 ADS5510 www.ti.com SLAS499 – JANUARY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS5510 is a low-power, 11-bit, 125 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 17.5 clock cycles, after which the output data is available as a 11-bit parallel word, coded in either straight offset binary or binary two's complement format. INPUT CONFIGURATION The analog input for the ADS5510 consists of a differential sample-and-hold architecture implemented using the switched capacitor technique shown in Figure 24. S3a L1 R1a C1a INP CP1 CA S1a CP3 S2 R3 L2 R1b INM CP2 S1b C1b VINCM 1V CP4 L1, L2: 6 nH − 10 nH effective R1a, R1b: 5W − 8W C1a, C1b: 2.2 pF − 2.6 pF CP1, CP2: 2.5 pF − 3.5 pF CP3, CP4: 1.2 pF − 1.8 pF CA: 0.8 pF − 1.2 pF R3: 80 W − 120 W Swithches: S1a, S1b: On Resistance: 35 W − 50 W S2: On Resistance: 7.5 W − 15 W S3a, S3b: On Resistance: 40 W − 60 W All switches OFF Resistance: 10 GW S3b A. All Switches are ON in sampling phase which is approximately one half of a clock period. Figure 24. Analog Input Stage 18 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 This differential input topology produces a high level of ac-performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5510 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. This means that each input is driven with a signal of up to CM ± 0.575 V, so that each input has a maximum differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM, pin 30). The ADS5510 obtains optimum performance when the analog inputs are driven differentially. The circuit shown in Figure 25 illustrates one possible configuration using an RF transformer. R0 50Ω Z0 50Ω 1:1 AC Signal Source ADT1− 1WT 10Ω 0.1µF R 50Ω 25Ω 25Ω INP ADS5510 INM CM 1nF Figure 25. Transformer Input to Convert Single-Ended Signal to Differential Signal The single-ended signal is fed to the primary winding of an RF transformer. Placing a 25-Ω resistor in series with INP and INM is recommended to dampen ringing due to ADC kickback. Since the input signal must be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the ADS5510 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference, best performance is attained when the CM output (pin 17) is filtered to ground with a 10-Ω series resistor and parallel 0.1-µF and 0.001-µF low-inductance capacitors, as illustrated in Figure 24. Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware that the input structure of the ADC sinks a common-mode current in the order of 600 µA (300 µA per input). Equation 1 describes the dependency of the common-mode current and the sampling frequency: 600mA f S (in MSPS) 125 MSPS (1) Where: fS > 2 MSPS. This equation helps to design the output capability and impedance of the driving circuit accordingly. When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5510. Texas Instruments offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selected depending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also be used with an RF transformer for high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. Submit Documentation Feedback 19 ADS5510 www.ti.com SLAS499 – JANUARY 2007 Table 4. Recommended Amplifiers to Drive the Input of the ADS5510 INPUT SIGNAL FREQUENCY DC to 20 MHz DC to 50 MHz DC to 100 MHz 10 MHz to 120 MHz Over 100 MHz RECOMMENDED AMPLIFIER THS4503 OPA847 THS4509 OPA695 THS3201 THS3202 THS9001 TYPE OF AMPLIFIER Differential In/Out Amp Operational Amp Differential In/Out Amp Operational Amp Operational Amp Operational Amp RF Gain Block USE WITH TRANSFORMER? No Yes No Yes Yes Yes Yes When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5510. These three amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gain block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of the ADS5510 directly, as shown in Figure 25, or with the addition of the filter circuit shown in Figure 26. Figure 26 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5510 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines of the ADS5510 input produces a degradation in performance at high input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical symmetry as possible between both inputs. Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that can simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations (see Figure 27), such amplifiers can be used for single-ended-to-differential conversion signal amplification. +5V − 5V RS 100Ω OPA695 1000pF R1 400Ω AV = 8V/V (18dB) 0.1µF RIN INP RT 100Ω RIN CIN INM CM 10Ω ADS5510 VIN 1:1 R2 57.5Ω 0.1µF Figure 26. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer 20 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 RS RG +5V RF RT +3.3V 10m F 0.1mF RIN VOCM 1mF THS4503 10mF 0.1mF 10 W RG - 5V RF 0.1m F RIN INP ADS5510 11-Bit / 125MSPS INM CM Figure 27. Using the THS4503 with the ADS5510 POWER-SUPPLY SEQUENCE The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as shown in Figure 28. This helps to make the device more robust to power supply ramp-up timings. 28 2 kW AVDD 29 1W 1 mF REFP Figure 28. POWER-DOWN The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit throughout the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device. Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and only the internal reference remains on to reduce the power-up time. The power-down mode reduces power dissipation to approximately 180 mW. Submit Documentation Feedback 21 ADS5510 www.ti.com SLAS499 – JANUARY 2007 REFERENCE CIRCUIT The ADS5510 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-µF decoupling capacitor (the 1-Ω resistor shown in Figure 29 is optional). In addition, an external 56.2-kΩ resistor should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in Figure 29. No capacitor should be connected between pin 31 and ground; only the 56.2-kΩ resistor should be used. 1W 29 1 mF 1W 30 1 mF R EF M R EF P 31 56.2 kW IR EF Figure 29. REFP, REFM, and IREF Connections for Optimum Performance CLOCK INPUT The ADS5510 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 30. CM CM 5 kW 5 kW CLKM CLKP 6 pF 3 pF 3 pF Figure 30. Clock Inputs When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01-µF capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 31. 22 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 0.01µF CLKP ADS5510 CLKM 0.01µ F Square Wave or Sine Wave (3VPP) Figure 31. AC-Coupled, Single-Ended Clock Input The ADS5510 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF capacitors, as shown in Figure 32. 0.01µ F CLKP Differential Square Wave or Sine Wave (3VPP) ADS5510 0.01µ F CLKM Figure 32. AC-Coupled, Differential Clock Input For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. Figure 19 shows the performance variation of the ADC versus clock duty cycle. Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input. Figure 18 shows the performance variation of the device versus input clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com. INTERNAL DLL In order to obtain the fastest sampling rates achievable with the ADS5510, the device uses an internal digital delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance at clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must be shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz. OUTPUT INFORMATION The ADC provides 11 data outputs (D10 to D0, with D10 being the MSB and D0 the LSB), a data-ready signal (CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the full-scale limits. Two different output formats (straight offset binary or two's complement) and two different output clock polarities (latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active high) is provided to put the outputs into a high-impedance state. Submit Documentation Feedback 23 ADS5510 www.ti.com SLAS499 – JANUARY 2007 In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 0x7FF in straight offset binary output format and 0x3FF in two's complement output format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x400 in two's complement output format. These outputs to an overdrive signal are ensured through design and characterization. The output circuitry of the ADS5510, by design, minimizes the noise produced by the data switching transients, and, in particular, its coupling to the ADC analog circuitry. Output D1 (pin 51) senses the load capacitance and adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have nearly the same load as D1 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply voltage or temperature. Placing external resistors in series with the outputs is not recommended. The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximum sampling frequency. Table 5 and Table 6 show the setup, hold, input clock to output data delays, and rise and fall times for different sampling frequencies with the DLL on and off, respectively. Table 7 and Table 8 show the rise and fall times at additional sampling frequencies with DLL on and off, respectively. To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, td, that results in the desired setup or hold time. Use either Equation 2or Equation 3 to calculate the value of td. Desired setup time = td – tSTART Desired hold time = tEND – td Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON) fS (MSPS) 105 93 80 65 tSETUP (ns) MIN 2.4 3.2 2.8 3.8 TYP 3.1 4.6 3.7 4.6 MAX MIN 2.2 2.3 2.8 3.6 tHOLD (ns) TYP 2.6 3.7 3.3 4.1 0.5 –0.5 1.7 0.8 5.3 5.3 7.9 8.5 5.8 6.7 6.6 7.2 4.4 5.5 5.3 6.4 MAX tSTART (ns) MIN TYP 1.7 MAX 2.6 MIN 5.8 tEND (ns) TYP 7.3 MAX MIN tr (ns) TYP 4.4 MAX 5.1 MIN tf (ns) TYP 3.3 MAX 3.8 Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF) fS (MSPS) 80 65 40 20 10 2 tSETUP (ns) MIN 3.2 4.3 8.5 17 27 284 TYP 4.2 5.7 11 25.7 51 370 MAX MIN 1.8 2 2.6 2.5 4 8 tHOLD (ns) TYP 3 3 3.5 4.7 6.5 19 MAX tSTART (ns) MIN TYP 3.8 2.8 –1 –9.8 -30 185 MAX 5 4.5 1.5 2 -3 320 MIN 8.4 8.3 8.9 9.5 11.5 515 tEND (ns) TYP 11 11.8 14.5 21.6 31 576 50 82 75 150 MAX MIN tr (ns) TYP 5.8 6.6 7.5 7.5 MAX 6.6 7.2 8 8 MIN tf (ns) TYP 4.4 5.5 7.3 7.6 MAX 5.3 6.4 7.8 8 Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON) fS (MSPS) 105 80 65 CLKOUT, Rise Time tr (ns) MIN TYP 2 2.5 3.1 MAX 2.2 2.8 3.5 CLKOUT, Fall Time tf (ns) MIN TYP 1.7 2.1 2.6 MAX 1.8 2.3 2.9 MIN CLKOUT Jitter, Peak-to-Peak tJIT (ps) TYP 175 210 260 MAX 250 315 380 Input-to-Output Clock Delay tPDI (ns) MIN 4 3.7 3.5 TYP 4.7 4.3 4.1 MAX 5.5 5.1 4.8 24 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF) fS (MSPS) 80 65 40 20 10 2 31 52 36 65 2610 4400 CLKOUT, Rise Time tr (ns) MIN TYP 2.5 3.1 4.8 8.3 MAX 2.8 3.5 5.3 9.5 CLKOUT, Fall Time tf (ns) MIN TYP 2.1 2.6 4 7.6 MAX 2.3 2.9 4.4 8.2 MIN CLKOUT Jitter, Peak-to-Peak tJIT (ps) TYP 210 260 445 800 MAX 315 380 650 1200 Input-to-Output Clock Delay tPDI (ns) MIN 7.1 7.8 9.5 13 16 537 TYP 8 8.5 10.4 15.5 20.7 551 MAX 8.9 9.4 11.4 18 25.5 567 SERIAL PROGRAMMING INTERFACE The ADS5510 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2 µs (minimum) high pulse on RESET (pin 35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-kΩ internal pullup resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. Table 2 shows the different modes and the bit values to be written to the register to enable them. Note that some of these modes may modify the standard operation of the device and possibly vary the performance with respect to the typical data shown in this data sheet. Applying a RESET signal is must to set the internal registers to their default states for normal operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and it is necessary to write the default values to the internal registers through the serial programming interface. The registers must be written in the following order. Write 9000h (Address 9, Data 000) Write A000h (Address A, Data 000) Write B000h (Address B, Data 000) Write C000h (Address C, Data 000) Write D000h (Address D, Data 000) Write E000h (Address E, Data 804) Write 0000h (Address 0, Data 000) Write 1000h (Address 1, Data 000) Write F000h (Address F, Data 000) NOTE: This procedure is only required if a RESET pulse is not provided to the device. Submit Documentation Feedback 25 ADS5510 www.ti.com SLAS499 – JANUARY 2007 PowerPAD PACKAGE The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard repair procedures. The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of the IC. This provides a low thermal resistance path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heatsink. Assembly Process 1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm. 2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The small size prevents wicking of the solder through the holes. 3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the thermal pad area to provide an additional heat path. 4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). 5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground plane. The spoke pattern increases the thermal resistance to the ground plane. 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. 7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. For more detailed information regarding the PowerPAD package and its thermal properties, see either the application brief SLMA004B (PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD Thermally Enhanced Package). 26 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 PACKAGING INFORMATION Orderable Device ADS5510IPAP ADS5510IPAPG4 ADS5510IPAPR ADS5510IPAPRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type HTQFP HTQFP HTQFP HTQFP Package Drawing PAP PAP PAP PAP Pins Package Eco Plan (2) Qty 64 64 64 64 160 160 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR 1000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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