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ADS7042
SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
ADS7042 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC
1 Features
3 Description
•
The ADS7042 is a 12-bit, 1-MSPS, analog-to-digital
converter (ADC). The device supports a wide analog
input voltage range (1.65 V to 3.6 V) and includes a
capacitor-based, successive-approximation register
(SAR) ADC with an inherent sample-and-hold circuit.
The SPI-compatible serial interface is controlled by
the CS and SCLK signals. The input signal is
sampled with the CS falling edge and SCLK is used
for conversion and serial data output. The device
supports a wide digital supply range (1.65 V to 3.6 V),
enabling direct interface to a variety of host
controllers. The ADS7042 complies with the JESD87A standard for a normal DVDD range (1.65 V to
1.95 V).
1
•
•
•
•
•
•
•
•
Industry's First SAR ADC with Nanowatt Power
Consumption:
– 234 µW at 1 MSPS with 1.8-V AVDD
– 690 µW at 1 MSPS with 3-V AVDD
– 69 µW at 100 kSPS with 3-V AVDD
– Less than 1 µW at 1 kSPS with 3-V AVDD
Industry's Smallest SAR ADC:
– X2QFN-8 Package with 2.25-mm2 Footprint
1-MSPS Throughput with Zero Data Latency
Wide Operating Range:
– AVDD: 1.65 V to 3.6 V
– DVDD: 1.65 V to 3.6 V (Independent of AVDD)
– Temperature Range: –40°C to 125°C
Excellent Performance:
– 12-Bit Resolution with NMC
– ±1-LSB (Max) DNL and INL
– 70-dB SNR with 3-V AVDD
– –80-dB THD with 3-V AVDD
Unipolar Input Range: 0 V to AVDD
Integrated Offset Calibration
SPI™-Compatible Serial Interface: 16 MHz
JESD8-7A Compliant Digital I/O
The ADS7042 is available in 8-pin, miniature, leaded,
and X2QFN packages and is specified for operation
from –40°C to 125°C. Miniature form-factor and
extremely low-power consumption make this device
suitable for space-constrained, battery-powered
applications.
Device Information(1)
PART NAME
ADS7042
Low-Power Data Acquisition
Battery-Powered Handheld Equipment
Level Sensors
Ultrasonic Flow Meters
Motor Control
Wearable Fitness
Portable Medical Equipment
Hard Drives
Glucose Meters
BODY SIZE (NOM)
X2QFN (8)
1.50 mm × 1.50 mm
VSSOP (8)
2.30 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
2 Applications
•
•
•
•
•
•
•
•
•
PACKAGE
AVDD
AVDD used as
Reference for device
OPA_AVDD
R
+
VIN+
AVDD
AINP
+
±
Device
C
AINM
GND
OPA_AVSS
RUG (8)
1.
Actual Device Size
1.5 x 1.5 x 0.35(H) mm
5m
m
1.5
mm
NOTE: The ADS7042 is smaller than a
0805 (2012 metric) SMD component.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7042
SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Companion Products.............................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
1
1
1
2
4
5
6
7
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Timing Characteristics............................................. 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 16
9.1 Digital Voltage Levels ............................................. 16
10 Detailed Description ........................................... 17
10.1 Overview ............................................................... 17
10.2 Functional Block Diagram ..................................... 17
10.3 Feature Description............................................... 18
10.4 Device Functional Modes...................................... 22
11 Application and Implementation........................ 25
11.1 Application Information.......................................... 25
11.2 Typical Applications .............................................. 25
12 Power-Supply Recommendations ..................... 33
12.1 AVDD and DVDD Supply Recommendations....... 33
12.2 Estimating Digital Power Consumption................. 33
12.3 Optimizing Power Consumed by the Device ........ 33
13 Layout................................................................... 34
13.1 Layout Guidelines ................................................. 34
13.2 Layout Example .................................................... 34
14 Device and Documentation Support ................. 35
14.1
14.2
14.3
14.4
14.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
15 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2015) to Revision C
Page
•
Added Companion Products and Device Comparison sections ............................................................................................ 4
•
Updated Figure 1 ................................................................................................................................................................. 10
•
Changed Serial Interface section: changed last half of first paragraph, changed Figure 34 ............................................... 21
•
Changed Figure 37 .............................................................................................................................................................. 24
•
Added Community Resources section ................................................................................................................................ 35
Changes from Revision A (August 2014) to Revision B
Page
•
Added TI Design ..................................................................................................................................................................... 1
•
Changed Wide Operating Range Features bullet: changed the value of AVDD from 1.8 V to 1.65 V ................................. 1
•
Changed the wide analog input voltage range value to 1.65 V in first paragraph of Description section.............................. 1
•
Changed ESD Ratings table to latest standards ................................................................................................................... 7
•
Changed AVDD parameter minimum specification in Recommended Operating Conditions table to 1.65 V ....................... 7
•
Changed EO parameter uncalibrated test conditions in Electrical Characteristics table ........................................................ 8
•
Changed Maximum throughput rate parameter test conditions in Electrical Characteristics table ....................................... 8
•
Changed AVDD parameter minimum specification in Electrical Characteristics table........................................................... 9
•
Changed conditions for Timing Characteristics table: changed range of AVDD and added CLOAD condition ...................... 10
•
Changed t D_CKDO parameter in Timing Characteristics table .............................................................................................. 10
•
Added fSCLK minimum specification to Timing Characteristics table .................................................................................... 10
•
Changed titles of Figure 26 to Figure 29 .............................................................................................................................. 14
•
Changed Reference sub-section in Feature Description section ......................................................................................... 18
•
Changed range of second fCLK-CAL parameter description in Table 2 ................................................................................... 23
•
Changed range of second fCLK-CAL parameter description in Table 3 .................................................................................. 24
2
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SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
•
Changed Reference Circuit section in Application Information ............................................................................................ 27
•
Added last two sentences to AVDD and DVDD Supply Recommendations section .......................................................... 33
Changes from Original (June 2014) to Revision A
•
Page
Made changes to product preview data sheet........................................................................................................................ 1
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ADS7042
SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
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5 Companion Products
PART NUMBER
8-Channel, 24-Bit Analog-To-Digital Converter With Integrated ECG Front End
OPA835
Ultra Low Power, Rail to Rail Out, Negative Rail In, VFB Amplifier
OPA314
3MHz, Low-Power, Low-Noise, RRI/O, 1.8V CMOS Operational Amplifier
ADS1294
4-Channel, 24-Bit Analog-To-Digital Converter With Integrated ECG Front End
ADS1298R
4
NAME
ADS1298
8-Channel, 24-Bit Analog-To-Digital Converter w/Integrated Respiration Impedance and ECG Front End
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SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
6 Device Comparison
DEVICE
RESOLUTION (Bits)
ANALOG INPUT
THROUGHPUT (MSPS)
ADS7040
8
Single-ended
1
ADS7041
10
Single-ended
1
ADS7042
12
Single-ended
1
ADS7043
12
Pseudo-differential
1
ADS7044
12
Fully differential
1
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ADS7042
SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
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7 Pin Configuration and Functions
RUG Package
8-Pin X2QFN
Top View
DCU Package
8-Pin Leaded VSSOP
Top View
SDO
SCLK
1
7
2
6
3
5
4
CS
8
AINM
DVDD
1
8
GND
SCLK
2
7
AVDD
SDO
3
6
AINP
CS
4
5
AINM
AINP
AVDD
GND
DVDD
Pin Functions
PIN
NO.
NAME
RUG
DCU
I/O
AINM
8
5
Analog input
Analog signal input, negative
AINP
7
6
Analog input
Analog signal input, positive
AVDD
6
7
Supply
CS
1
4
Digital input
DVDD
4
1
Supply
Digital I/O supply voltage
GND
5
8
Supply
Ground for power supply, all analog and digital signals are referred to this pin
SCLK
3
2
Digital input
SDO
2
3
Digital output
6
DESCRIPTION
Analog power-supply input, also provides the reference voltage to the ADC
Chip-select signal, active low
Serial clock
Serial data out
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SBAS608C – JUNE 2014 – REVISED DECEMBER 2015
8 Specifications
8.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
AVDD to GND
–0.3
3.9
V
DVDD to GND
–0.3
3.9
V
AINP to GND
–0.3
AVDD + 0.3
V
AINM to GND
–0.3
0.3
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Storage temperature, Tstg
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
AVDD
Analog supply voltage range
1.65
3.6
UNIT
V
DVDD
Digital supply voltage range
1.65
3.6
V
TA
Operating free-air temperature
–40
125
°C
8.4 Thermal Information
ADS7042
THERMAL METRIC (1)
RUG (X2QFN)
DCU (VSSOP)
8 PINS
8 PINS
UNIT
235.8
°C/W
RθJA
Junction-to-ambient thermal resistance
177.5
RθJC(top)
Junction-to-case (top) thermal resistance
51.5
79.8
°C/W
RθJB
Junction-to-board thermal resistance
76.7
117.6
°C/W
ψJT
Junction-to-top characterization parameter
1.0
8.9
°C/W
ψJB
Junction-to-board characterization parameter
76.7
116.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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8.5 Electrical Characteristics
At TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, and VAINM = 0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input
voltage range
CS
0
AVDD
AINP to GND
–0.1
AVDD + 0.1
AINM to GND
–0.1
0.1
Sampling capacitance
V
15
pF
12
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
12
INL
Integral nonlinearity
DNL
Differential nonlinearity
EO
Offset error
Uncalibrated
dVOS/dT
EG
Calibrated
(3)
–1
±0.7
1
AVDD = 1.8 V
–2
±1
2
AVDD = 3 V
–0.99
±0.5
1
AVDD = 1.8 V
–0.99
±0.7
2
AVDD = 3 V
–3
±0.5
3
AVDD = 1.8 V
–4
±1
4
AVDD = 3 V
–0.1
±0.05
0.1
AVDD = 1.8 V
–0.2
±0.1
0.2
AVDD = 1.65 V to 3.6 V
LSB (2)
LSB
±12
Offset error drift with temperature
Gain error
Bits
AVDD = 3 V
5
Gain error drift with temperature
LSB
ppm/°C
2
%FS
ppm/°C
SAMPLING DYNAMICS
tACQ
Acquisition time
Maximum throughput rate
200
ns
16-MHz SCLK, AVDD = 1.65 V to 3.6 V
1
MHz
DYNAMIC CHARACTERISTICS
SNR
Signal-to-noise ratio (4)
THD
Total harmonic distortion (4) (5)
fIN = 2 kHz, AVDD = 3 V
69
fIN = 2 kHz, AVDD = 1.8 V
68
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
70
–80
68
69.5
dB
dB
SINAD
Signal-to-noise and distortion (4)
SFDR
Spurious-free dynamic range (4)
fIN = 2 kHz, AVDD = 3 V
80
dB
BW(fp)
Full-power bandwidth
At –3 dB, AVDD = 3 V
25
MHz
(1)
(2)
(3)
(4)
(5)
8
fIN = 2 kHz, AVDD = 1.8 V
67.5
dB
Ideal input span; does not include gain or offset error.
LSB means least significant bit.
Refer to the Offset Calibration section for more details.
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified..
Calculated on the first nine harmonics of the input frequency.
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Electrical Characteristics (continued)
At TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, and VAINM = 0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
High-level input voltage (6)
0.65 DVDD
DVDD + 0.3
V
VIL
Low-level input voltage (6)
–0.3
0.35 DVDD
V
0.8 DVDD
DVDD
At Isource = 2 mA
DVDD – 0.45
DVDD
At Isink = 500 µA
0
0.2 DVDD
At Isink = 2 mA
0
0.45
VOH
High-level output voltage (6)
VOL
Low-level output voltage (6)
At Isource = 500 µA
V
V
POWER-SUPPLY REQUIREMENTS
AVDD
Analog supply voltage
1.65
3
3.6
V
DVDD
Digital I/O supply voltage
1.65
3
3.6
V
At 1 MSPS with AVDD = 3 V
IAVDD
Analog supply current
230
At 100 kSPS with AVDD = 3 V
At 1 MSPS with AVDD = 1.8 V
23
At 1 MSPS with AVDD = 3 V
PD
Power dissipation
(6)
690
At 100 kSPS with AVDD = 3 V
At 1 MSPS with AVDD = 1.8 V
µA
130
69
µW
234
Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. See the Digital Voltage Levels section for
more details.
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8.6 Timing Characteristics
All specifications are at TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF,
unless otherwise specified.
MIN
TYP
MAX
UNIT
1
MSPS
TIMING SPECIFICATIONS
fTHROUGHPUT
Throughput
tCYCLE
Cycle time
tCONV
Conversion time
tDV_CSDO
tD_CKDO
tDZ_CSDO
1
µs
12.5 × tSCLK + tSU_CSCK
ns
Delay time: CS falling to data enable
10
ns
Delay time: SCLK falling to (next) data valid on DOUT,
AVDD = 1.8 V to 3.6 V
30
ns
Delay time: SCLK falling to (next) data valid on DOUT,
AVDD = 1.65 V to 1.8 V
50
ns
Delay time: CS rising to DOUT going to 3-state
5
ns
ns
TIMING REQUIREMENTS
tACQ
Acquisition time
200
fSCLK
SCLK frequency
0.016
tSCLK
SCLK period
62.5
tPH_CK
SCLK high time
tPL_CK
SCLK low time
tPH_CS
CS high time
60
ns
tSU_CSCK
Setup time: CS falling to SCLK falling
15
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
10
ns
16
MHz
0.45
0.55
tSCLK
0.45
0.55
tSCLK
ns
Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
tPH_CS
CS
tSU_CSCK
SCLK
1
2
tDV_CSDO
SDO
0
0
tPH_CK
3
4
5
tPL_CK
6
7
8
9
10
11
12
tD_CKDO
D11
D10
tD_CKCS
tSCLK
13
14
tDZ_CSDO
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data for Sample N
Figure 1. Timing Diagram
10
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8.7 Typical Characteristics
0
0
±20
±20
±40
±40
±60
±60
Amplitude (dB)
Amplitude (dB)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
±80
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Input Frequency (kHz)
SNR = 70.62 dB
0
500
100
C001
THD = –83.96 dB
fIN = 2 kHz
Number of samples = 32768
200
300
SNR = 70.22 dB
500
C002
THD = –81.58 dB
fIN = 250 kHz
Number of samples = 32768
Figure 3. Typical FFT
Figure 2. Typical FFT
73
73
- - -SNR
----SINAD
- - -SNR
----SINAD
72
72
SNR/SINAD (dB)
SNR/SINAD (dB)
400
Input Frequency (kHz)
71
70
69
71
70
69
68
68
±40
26
±7
59
92
Free-Air Temperature (oC)
125
0
50
100
150
200
Input Frequency (kHz)
C003
250
C004
fIN = 2 kHz
Figure 4. SNR and SINAD vs Temperature
Figure 5. SNR and SINAD vs Input Frequency
73
±75
Total Harmonic Distortion (dB)
SNR/SINAD (dB)
72
71
70
69
68
67
- - -SNR
----SINAD
66
±78
±81
±84
±87
±90
1.8
2.1
2.4
2.7
3
Reference Voltage (V)
3.3
3.6
±40
C005
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
±7
26
59
92
Free-Air Temperature (oC)
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Figure 7. THD vs Free-Air Temperature
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
±75
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
±75
±78
±81
±84
±87
±90
±78
±81
±84
±87
±90
0
50
100
150
200
Input Frequency (kHz)
250
1.8
Figure 8. THD vs Input Frequency
2.7
3
3.3
C010
Figure 9. THD vs Reference Voltage (AVDD)
91
87
83
79
75
91
87
83
79
75
±40
26
±7
59
92
Free-Air Temperature (oC)
125
0
50
100
150
200
250
Input Frequency (kHz)
C007
Figure 10. SFDR vs Free-Air Temperature
C009
Figure 11. SFDR vs Input Frequency
65000
91
52000
Number of Hits
95
87
83
79
39000
26000
13000
75
0
1.8
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
3.6
2046
2047
2048
2049
Code
C011
Mean code = 2048.04
Figure 12. SFDR vs Reference Voltage (AVDD)
12
3.6
95
Spurious-Free Dynamic Range (dB)
Spurious-Free Dynamic Range (dB)
2.4
Reference Voltage (V)
95
Spurious-Free Dynamic Range (dB)
2.1
C008
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2050
C012
Sigma = 0.27
Figure 13. DC Input Histogram
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
0
0
-1
-1
Calibrated
Calibrated
Offset (LSB)
Offset (LSB)
-2
-2
-3
-3
-4
-5
Uncalibrated
-4
-6
Uncalibrated
-5
-7
±40
26
±7
59
92
1.8
125
Free-Air Temperature (oC)
2.7
3
3.3
3.6
C014
Figure 15. Offset vs Reference Voltage (AVDD)
0.2
0.2
0.1
0.1
Gain (%FS)
Gain (%FS)
2.4
Reference Voltage (V)
Figure 14. Offset vs Free-Air Temperature
0
-0.1
0
-0.1
-0.2
-0.2
±40
26
±7
59
92
125
Free-Air Temperature (oC)
1.8
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
C015
Figure 16. Gain Error vs Free-Air Temperature
3.6
C016
Figure 17. Gain Error vs Reference Voltage (AVDD)
1
1
0.75
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2.1
C013
0.5
0.25
0
-0.25
-0.5
0.5
0
-0.5
-0.75
-1
-1
0
512
1024
1536
2048
2560
3072
Code
AVDD = 3 V
3584
4096
0
512
1024
1536
2048
2560
3072
3584
Code
C017
4096
C018
AVDD = 3 V
Figure 18. Typical DNL
Figure 19. Typical INL
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1
0.5
0
-0.5
1
0.5
0
-0.5
-1
-1.5
-1
-2
0
512
1024
1536
2048
2560
3072
3584
Code
0
4096
512
AVDD = 1.8 V
2560
3072
3584
4096
C020
Figure 21. Typical INL
2
0.5
Differential Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2048
AVDD = 1.8 V
Figure 20. Typical DNL
Maximum
0
Minimum
-0.5
-1
1
Maximum
0
Minimum
±1
±40
±7
26
59
92
Free-Air Temperature (oC)
1.8
125
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
C021
Figure 22. DNL vs Free-Air-Temperature
3.6
C022
Figure 23. DNL vs Reference Voltage (AVDD)
2
Integral Nonlinearity (LSB)
1
Integral Nonlinearity (LSB)
1536
Code
1
0.5
Maximum
0
Minimum
-0.5
-1
1
Maximum
0
Minimum
±1
±2
±40
±7
26
59
92
Free-Air Temperature (oC)
125
1.8
2.1
2.4
2.7
3
3.3
Reference Voltage (V)
C023
Figure 24. INL vs Free-Air-Temperature
14
1024
C019
3.6
C024
Figure 25. INL vs Reference Voltage (AVDD)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
230
240
Supply Current (µA)
Supply Current (µA)
220
210
200
190
180
180
120
60
0
±40
26
±7
59
92
Free-Air Temperature (oC)
125
0
200
400
600
800
1000
Throughput (Ksps)
C025
C026
fSample = 1 MSPS
Figure 27. AVDD Supply Current vs Throughput
300
150
260
120
IAVDD Static (nA)
Supply Current (µA)
Figure 26. AVDD Supply Current vs Free-Air Temperature
220
180
90
60
30
140
0
100
1.8
2.1
2.4
2.7
3
Supply Voltage (V)
3.3
3.6
±40
Figure 28. AVDD Supply Current vs AVDD Voltage
±7
26
59
92
Free-Air Temperature (oC)
C027
125
C028
Figure 29. AVDD Static Current vs Free-Air Temperature
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9 Parameter Measurement Information
9.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 30 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
-0.3V
VIL
DVDD = 1.65 V to 1.95 V
Figure 30. Digital Voltage Levels as per the JESD8-7A Standard
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10 Detailed Description
10.1 Overview
The ADS7042 is an ultralow-power, ultra-small analog-to-digital converter (ADC) that supports a wide analog
input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples
the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock
provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM
pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are
reconnected across the AINP and AINM pins and the ADS7042 enters acquisition phase.
The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up
or during normal operation; see the Offset Calibration section for more details.
The device also provides a simple serial interface to the host controller and operates over a wide range of digital
power supplies. The ADS7042 requires only a 16-MHz SCLK for supporting a throughput of 1 MSPS. The digital
interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram section
provides a block diagram of the device.
10.2 Functional Block Diagram
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
SCLK
Serial
Interface
AINM
SDO
SAR
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10.3 Feature Description
10.3.1 Reference
The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 31. TI recommends
decoupling the AVDD pin with a 1-µF, low equivalent series resistance (ESR) ceramic capacitor. The minimum
capacitor value required for AVDD is 200 nF. The AVDD pin functions as a switched capacitor load to the source
powering AVDD. The decoupling capacitor provides the instantaneous charge required by the internal circuit and
helps in maintaining a stable dc voltage on the AVDD pin. TI recommends powering the AVDD pin with a low
output impedance and low-noise regulator (such as the TPS79101).
1µF
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
SCLK
Serial
Interface
AINM
SDO
SAR
Figure 31. Reference for the Device
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Feature Description (continued)
10.3.2 Analog Input
The device supports single-ended analog inputs. The ADC samples the difference between AINP and AINM and
converts for this voltage. The device is capable of accepting a signal from –100 mV to 100 mV on the AINM input
and is useful in systems where the sensor or signal-conditioning block is far from the ADC. In such a scenario,
there can be a difference between the ground potential of the sensor or signal conditioner and the ADC ground.
In such cases, use separate wires to connect the ground of the sensor or signal conditioner to the AINM pin. The
AINP input is capable of accepting signals from 0 V to AVDD. Figure 32 represents the equivalent analog input
circuits for the sampling stage. The device has a low-pass filter followed by the sampling switch and sampling
capacitor. The sampling switch is represented by an Rs(typically 50 Ω) resistor in series with an ideal switch and
Cs (typically 15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD
and ground.
AVDD
50
Rs
AINP
CS
10 pF
AVDD
50
Rs
AINM
CS
Figure 32. Equivalent Input Circuit for the Sampling Stage
The analog input full-scale range (FSR) is equal to the reference voltage of the ADC. The reference voltage for
the device is equal to the analog supply voltage (AVDD). Thus, the device FSR can be determined by
Equation 1:
FSR = VREF = AVDD
(1)
10.3.3 ADC Transfer Function
The device output is in straight binary format. The device resolution for a single-ended input can be computed by
Equation 2:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD and
N = 12
(2)
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Feature Description (continued)
Figure 33 and Table 1 show the ideal transfer characteristics for the device.
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
VREF
2
1 LSB
VIN
V REF
2
VREF ± 1 LSB
1LSB
Single-Ended Analog Input
(AINP ± AINM)
Figure 33. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE (AINP – AINM)
20
CODE
DESCRIPTION
IDEAL OUTPUT CODE
≤1 LSB
NFSC
Negative full-scale code
000
1 LSB to 2 LSBs
NFSC + 1
—
001
(VREF / 2) to (VREF / 2) + 1 LSB
MC
Mid code
800
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs
MC + 1
—
801
≥ VREF – 1 LSB
PFSC
Positive full-scale code
FFF
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10.3.4 Serial Interface
The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO pin outputs the ADC conversion results. Figure 34 shows a detailed timing diagram for the serial interface.
A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is
available on the SDO pin with the first two bits set to 0, followed by 12 bits of the conversion result. The first zero
is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the
conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains
low after 14 SCLKs. A CS rising edge ends the frame and brings the serial data bus to 3-state. For acquisition of
the next sample, a minimum time of tACQ must be provided after the conversion of the current sample is
completed. For details on timing specifications, see the Timing Characteristics table.
The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains
low during the first serial transfer frame after power-up. For further details, refer to the Offset Calibration section.
Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
CS
SCLK
1
SDO
0
2
0
3
D11
4
5
6
7
8
9
10
11
12
D10
D9
D8
D7
D6
D5
D4
D3
D2
13
D1
14
D0
Data for Sample N
Figure 34. Serial Interface Timing Diagram
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10.4 Device Functional Modes
10.4.1 Offset Calibration
The ADS7042 includes a feature to calibrate the device internal offset. During offset calibration, the analog input
pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset
calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be
accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, TI
recommends calibrating the offset on power-up to bring the offset within the specified limits. If the operating
temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during normal
operation. Figure 35 shows the offset calibration process.
)
(4
cle
Po
rR
th
Device
Power Up
Ca
lib
r
SDatio
O no
= nP
0x o
00 w e
0 rU
p
Data Capture(1)
Calibration during Normal operation(2)
wi
e
am
Fr LKs
r
fe C
ns S 0
ra 1 6 0 0
l T n 0x
ria tha =
e
s O
t S les SD
rs
Fi
we
y
ec
Normal Operation
With Uncalibarted
offset
(3
)
Po
:
we
rR
Data Capture(1)
ec
yc
le
(4
)
Normal Operation
With Calibarted
offset
Calibration during Normal Operation(2)
(1)
See the Timing Characteristics section for timing specifications.
(2)
See the Offset Calibration During Normal Operation section for details.
(3)
See the Offset Calibration on Power-Up section for details.
(4)
The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up
state.
Figure 35. Offset Calibration
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Device Functional Modes (continued)
10.4.1.1 Offset Calibration on Power-Up
The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the
CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains
low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first
sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up,
the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 36
shows the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
MIN
fCLK-CAL
SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V
fCLK-CAL
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
tPOWERUP-CAL
Calibration time at power-up
tACQ
TYP
MAX
UNIT
16
MHz
12
MHz
15 tSCLK
ns
Acquisition time
200
ns
tPH_CS
CS high time
tACQ
ns
tSU_CSCK
Setup time: CS falling to SCLK falling
15
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
10
ns
Start
Power-up
Calibration
Sample
#1
tPH_CS
tPOWERUP-CAL
tACQ
CS
tD_CKCS
tSU_CSCK
SCLK(fCLK-CAL)
1
2
15
16
SDO
Figure 36. Offset Calibration on Power-Up Timing Diagram
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10.4.1.2 Offset Calibration During Normal Operation
Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in
one serial transfer frame. During the first 14 SCLKs, the device converts the sample acquired on the CS falling
edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling
edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 14th
SCLK falling edge and SDO goes to 3-state after CS goes high. If the device is provided with less than 32
SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset
calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output.
Figure 37 shows the timing diagram for offset calibration during normal operation.
Table 3. Offset Calibration During Normal Operation
MAX
UNIT
fCLK-CAL
SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V
MIN
TYP
16
MHz
fCLK-CAL
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
12
MHz
tCAL
Calibration time during normal operation
15 tSCLK
ns
tACQ
Acquisition time
200
ns
tPH_CS
CS high time
tACQ
ns
tSU_CSCK
Setup time: CS falling to SCLK falling
15
ns
tD_CKCS
Delay time: last SCLK falling to CS rising
10
ns
Sample
N+1
Sample
N
tPH_CS
tCONV
tCAL
tACQ
CS
tSU_CSCK
tD_CKCS
SCLK(fCLK-CAL)
1
2
3
4
13
SDO
0
0
D11
D10
D1
14
15
16
17
18
31
32
D0
Data for Sample N
Figure 37. Offset Calibration During Normal Operation Timing Diagram
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing the input driver circuit, reference driver circuit, and provides
some application circuits designed for the ADS7042.
11.2 Typical Applications
11.2.1 Single-Supply DAQ with the ADS7042
AVDD
AVDD
VIN+
OPA314
+
200
AVDD
AINP
+
±
Device
1.5 nF
AINM
GND
Input Driver
Device: 12-Bit, 1-MSPS,
Single-Ended Input
Figure 38. DAQ Circuit: Single-Supply DAQ
11.2.1.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7042
with SNR greater than 68 dB and THD less than –80 dB for input frequencies of 2.5 kHz at a throughput of
1 MSPS.
11.2.1.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an
antialiasing filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
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Typical Applications (continued)
11.2.1.2.1 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a rate greater than or equal to the
Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and
folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an external, antialiasing
filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An
antialiasing filter is designed as a low-pass RC filter, for which the 3-dB bandwidth is optimized for noise,
response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a highbandwidth filter is designed to allow accurately settling the signal at the ADC inputs during the small acquisition
time window. Figure 39 provides the equation for determining the bandwidth of the antialiasing filter.
AVDD
f
RFLT
1
3 dB
AVDD
AINP
CFLT
2S u R FLT u C FLT
Device
AINM
GND
Figure 39. Antialiasing Filter
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the
specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
15 pF. Thus, the value of CFLT is greater than 300 pF. Select a COG- or NPO-type capacitor because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
can require more bandwidth than others to drive similar filters.
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Typical Applications (continued)
11.2.1.2.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be high enough to settle
the input signal in the acquisition time of the ADC. Higher bandwidth reduces the closed-loop output
impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter
at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In
order to maintain the overall stability of the input driver circuit, the select the amplifier bandwidth as described
in Equation 3.
1
GBW t 4 u
2Πu RFLT u CFLT
where:
•
•
GBW = unity gain bandwidth
(3)
Noise: Noise contribution of the front-end amplifiers must be low enough to prevent any degradation in SNR
performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition
system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below
20% of the input-referred noise of the ADC. Noise from the input driver circuit is band limited by designing a
low cutoff frequency RC filter, as explained in Equation 4.
NG u
V 1 f _AMP_PP
6.6
2
Œ
e 2n_RMS u u f
2
3dB
1
VREF
d
u
u 10
5
2 2
SNR(dB)
20
where:
•
•
•
•
•
V1/f_AMP_PP is the peak-to-peak flicker noise in µVRMS,
en_RMS is the amplifier broadband noise,
f–3dB is the –3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to 1 in the buffer configuration.
(4)
Settling time: For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE
simulations before selecting the amplifier.
The OPA314 is selected for this application for its rail-to-rail input and output swing, low-noise (14 nV/√Hz), and
low-power (150 µA) performance to support a single-supply data acquisition circuit.
11.2.1.2.3 Reference Circuit
The analog supply voltage of the device is also used as a voltage reference for conversion. TI recommends
decoupling the AVDD pin with a 1-µF, low-ESR ceramic capacitor. The minimum capacitor value required for
AVDD is 200 nF.
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Typical Applications (continued)
11.2.1.3 Application Curve
Figure 40 shows the FFT plot for the ADS7042 with a 2.5-kHz input frequency used for the circuit in Figure 38.
0
Signal Power (dB)
±20
±40
±60
±80
±100
±120
±140
0
100
SNR = 69 dB
200
300
400
500
Frequency (kHz)
C033
THD = –80 dB
SINAD = 68.6 dB
Number of samples = 32768
Figure 40. Test Results for the ADS7042 and OPA314 for a 2.5-kHz Input
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Typical Applications (continued)
11.2.2 DAQ Circuit with the ADS7042 for Maximum SINAD
AVDD
OPA_AVDD
+
VIN+
OPA835
25
AVDD
AINP
+
±
Device
1.5 nF
AINM
GND
OPA_AVSS
Input Driver
Device: 12-Bit, 1-MSPS,
Single-Ended Input
Figure 41. ADS7042 DAQ Circuit: Maximum SINAD for Input Frequencies up to 250 kHz
11.2.2.1 Design Requirements
The goal of this application is to design a data acquisition circuit based on the ADS7042 with SINAD greater than
69.5 dB for input frequencies up to 250 kHz.
11.2.2.2 Detailed Design Procedure
To achieve a SINAD of 69.5 dB, the operational amplifier must have high bandwidth in order to settle the input
signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total
system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 41,
the OPA835 is selected for its high bandwidth (56 MHz) and low noise (9.3 nV/√Hz).
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation
results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition
Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).
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11.2.2.3 Application Curves
0
0
±20
±20
±40
±40
±60
±60
Amplitude (dB)
Amplitude (dB)
Figure 42 shows the FFT plot for the ADS7042 with a 2-kHz input frequency used for the circuit in Figure 41.
Figure 43 shows the FFT plot for the ADS7042 with a 250-kHz input frequency used for the circuit in Figure 41.
±80
±100
±120
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
Input Frequency (kHz)
SNR = 70.62 dB
400
500
0
100
THD = –83.96 dB
SINAD = 70.3 dB
Number of samples = 32768
200
300
Input Frequency (kHz)
C001
Figure 42. Test Results for the ADS7042 and OPA835 for a
2-kHz Input
30
±80
±100
SNR = 70.22 dB
400
500
C002
THD = –81.58 dB
SINAD = 69.8 dB
Number of samples = 32768
Figure 43. Test Results for the ADS7042 and OPA835 for a
250-kHz Input
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11.2.3 12-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
AVDD
Sensor
ROUT
AVDD
AINP
+
±
Device
CFLT
AINM
GND
Figure 44. Interfacing the Device Directly with Sensors
In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a
DAQ circuit can be designed without the input driver for the ADC . This type of a use case is of particular interest
for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications
that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and
chemical).
11.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
Table 4. Design Parameters
DESIGN PARAMETER
GOAL VALUE
Throughput
10 kSPS
SNR at 100 Hz
70 dB
THD at 100 Hz
75dB
SINAD at 100 Hz
69 dB
ENOB
11
Power
10 µW
11.2.3.2 Detailed Design Procedure
The ADS7042 can be directly interfaced with sensors at lower throughputs without the need of an amplifier
buffer. The analog input source drive must be capable of driving the switched capacitor load of a SAR ADC and
settling the analog input signal within the acquisition time of the SAR ADC. However, the output impedance of
the sensor must be taken into account when interfacing a SAR ADC directly with sensors. Drive the analog input
of the SAR ADC with a low impedance source. The input signal requires more acquisition time to settle to the
desired accuracy because of the higher output impedance of the sensor. The simplified circuit for a sensor as a
voltage source with output impedance (ROUT) is shown in Figure 44.
The acquisition time of a SAR ADC (such as the ADS7042) can be increased by reducing throughput in the
following ways:
1. Reducing the SCLK frequency to reduce the throughput, or
2. Keeping the SCLK fixed at the highest permissible value (that is, 16 MHz for the device) and increasing the
CS high time.
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Table 5 lists the acquisition time for the above two cases for a throughput of 100 kSPS. Clearly, case 2 provides
more acquisition time for the input signal to settle.
Table 5. Acquisition Time with Different SCLK Frequencies
CONVERSION TIME
(= 12.5 × tSCLK + tSU_CSCK)
ACQUISITION TIME
(= tcycle – tconv)
CASE
SCLK
tcycle
1
1.6 MHz
10 µs
7.8125 µs
2.1875 µs
2
16 MHz
10 µs
0.78125 µs
9.21875 µs
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation
results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition
Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).
11.2.3.3 Application Curve
When the output impedance of the sensor increases, the time required for the input signal to settle increases and
the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of
the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time
for the input signal to settle. Figure 45 provides the results for ENOB achieved from the ADS7042 for case 2 at
different throughputs with different input impedances at the device input.
12
Effective Number of Bits
25
11
and 1.5 nF
250
and 1.5 nF
600
800
10
9
0
200
400
Sampling Rate (kSPS)
1000
C029
Figure 45. ENOB (Effective Number of Bits) Achieved from the ADS7042 at Different Throughputs
Table 6 shows the results and performance summary for this 12-bit, 10-kSPS DAQ circuit application.
Table 6. Results and Performance Summary for 12-Bit, 10-kSPS DAQ Circuit for DC Sensor
Measurements
DESIGN PARAMETER
GOAL VALUE
ACHIEVED RESULT
Throughput
10 kSPS
10 kSPS
SNR at 100 Hz
70 dB
70.6 dB
THD at 100 Hz
75dB
83.5 dB
SINAD at 100 Hz
69dB
70.4 dB
32
ENOB
11
11.4
Power
10 µW
7 µW
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12 Power-Supply Recommendations
12.1 AVDD and DVDD Supply Recommendations
The ADS7042 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. The AVDD supply also defines the full-scale input range of the device. Always set the AVDD supply to
be greater than or equal to the maximum input signal to avoid saturation of codes. Decouple the AVDD and
DVDD pins individually with 1-µF ceramic decoupling capacitors, as shown in Figure 46. The minimum capacitor
value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both supplies are powered from the
same source, a minimum capacitor value of 220 nF is required for decoupling.
AVDD
AVDD
1 PF
GND
1 PF
DVDD
DVDD
Figure 46. Power-Supply Decoupling
12.2 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, load capacitance on the SDO
line, and the output code. The load capacitance on the SDO line is charged by the current from the SDO pin on
every rising edge of the data output and is discharged on every falling edge of the data output. The current
consumed by the device from the DVDD supply can be calculated by Equation 5:
IDVDD = C × V × f
where:
•
•
•
C = Load capacitance on the SDO line,
V = DVDD supply voltage, and
f = Number of transitions on the SDO output.
(5)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on the SDO change on every SCLK. SDO changing on
every SCLK results in an output code of AAAh or 555h. For an output code of AAAh or 555h at a 1-MSPS
throughput, the frequency of transitions on the SDO output is 6MHz.
For the current consumption to remain at the lowest possible value, keep the DVDD supply at the lowest
permissible value and keep the capacitance on the SDO line as low as possible.
12.3 Optimizing Power Consumed by the Device
•
•
•
•
Keep the analog supply voltage (AVDD) as close as possible to the analog input voltage. Set AVDD to be
greater than or equal to the analog input voltage of the device.
Keep the digital supply voltage (DVDD) at the lowest permissible value.
Reduce the load capacitance on the SDO output.
Run the device at the optimum throughput. Power consumption reduces with throughput.
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13 Layout
13.1 Layout Guidelines
Figure 47 shows a board layout example for the ADS7042. Use a ground plane underneath the device and
partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and
keep the analog input signals and the reference input signals away from noise sources. In Figure 47, the analog
input and reference signals are routed on the top and left side of the device and the digital connections are
routed on the bottom and right side of the device.
The power sources to the device must be clean and well-bypassed. Use 1-μF ceramic bypass capacitors in close
proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and
DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-impedance
paths. The AVDD supply voltage for the ADS7042 also functions as a reference for the device. Place the
decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins and connect CREF to the device
pins with thick copper tracks, as shown in Figure 47.
The fly-wheel RC filters are placed close to the device. Among ceramic surface-mount capacitors, COG (NPO)
ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic
capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
13.2 Layout Example
N
AI
GN
AVDD
D
CREF
CIN
CDVDD
DV
DD
P
SD
O
K
CS
L
SC
Figure 47. Example Layout
34
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14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
For related documentation see the following:
• OPA314 Data Sheet, SBOS563
• OPA835 Data Sheet, SLOS713
• TPS79101 Data Sheet, SLVS325
• TIPD168 Reference Guide, TIDU390
14.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.3 Trademarks
E2E is a trademark of Texas Instruments.
TINA is a trademark of Texas Instruments, Inc.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
14.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
14.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RUG0008A
X2QFN - 0.4 mm max height
SCALE 7.500
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
1.55
1.45
C
0.4 MAX
SEATING PLANE
0.05
0.00
0.08 C
SYMM
2X
0.35
0.25
2X
4
3
(0.15)
TYP
0.45
0.35
5
SYMM
2X
1
4X 0.5
2X
7
1
4X
8
PIN 1 ID
(45 X0.1)
6X
0.4
0.3
0.25
0.15
0.3
0.2
0.1
0.05
C A
C
B
4222060/A 05/14/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
(R0.05) TYP
4
SYMM
(1.35)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222060/A 05/14/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
4
SYMM
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE:25X
4222060/A 05/14/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS7042IDCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7042
ADS7042IDCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7042
ADS7042IRUGR
ACTIVE
X2QFN
RUG
8
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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