ADS7808
ADS
7808
SBAS018A – JANUARY 1992 – REVISED SEPTEMBER 2003
12-Bit 10µs Serial CMOS Sampling
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
●
●
●
●
●
●
●
●
The ADS7808 is a complete 12-bit sampling analog-to-digital
using state-of-the-art CMOS structures. It contains a 12-bit
capacitor-based SAR A/D with S/H, reference, clock, and a
serial data interface. Data can be output using the internal
clock, or can be synchronized to an external data clock. The
ADS7808 also provides an output synchronization pulse for
ease of use with standard DSP processors.
100kHz SAMPLING RATE
72dB SINAD WITH 45kHz INPUT
±1/2 LSB INL AND DNL
SIX SPECIFIED INPUT RANGES
SERIAL OUTPUT
SINGLE +5V SUPPLY OPERATION
PIN-COMPATIBLE WITH 16-BIT ADS7809
USES INTERNAL OR EXTERNAL
REFERENCE
● 100mW MAX POWER DISSIPATION
● 0.3" SO-20
● SIMPLE DSP INTERFACE
The ADS7808 is specified at a 100kHz sampling rate, and
specified over the full temperature range. Laser-trimmed
scaling resistors provide various input ranges including ±10V
and 0V to 5V, while an innovative design operates from a
single +5V supply, with power dissipation under 100mW.
The ADS7808 is available in a 0.3" SO-20, fully specified for
operation over the industrial –40°C to +85°C range.
CS
R/C
Power Down
Successive Approximation Register and Control Logic
Clock
20kΩ
CDAC
R1IN
10kΩ
BUSY
R2IN
Serial
20kΩ
5kΩ
Data
Comparator
R3IN
Data Clock
Out
Serial Data
CAP
Buffer
Internal
+2.5V Ref
4kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1992-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Inputs: R1IN .......................................................................... ±25V
R2IN .......................................................................... ±25V
R3IN .......................................................................... ±25V
CAP ..................................... VANA+0.3V to AGND2 –0.3V
REF ....................................... Indefinite Short to AGND2,
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND2 ................................. ±0.3V
VANA ...................................................................................................... 7V
VDIG to VANA ....................................................................................... +0.3
VDIG ....................................................................................................... 7V
Digital Inputs ............................................................. –0.3V to VDIG +0.3V
Maximum Junction Temperature .................................................. +165°C
Internal Power Dissipation ............................................................ 700mW
Lead Temperature (soldering, 10s) .............................................. +300°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
MINIMUM
SIGNAL-TOSPECIFIED
(NOISE + DISTORTION)
PACKAGE
TEMPERATURE
RATIO (DB)
PACKAGE-LEAD DESIGNATOR(1)
RANGE
ADS7808U
"
±0.9
"
70
"
SO-20
"
DW
"
–40°C to +85°C
"
ADS7808UB
"
±0.45
"
72
"
"
"
"
"
"
"
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS7808U
"
ADS7808U
ADS7808U/1K
Tube, 38
Tape and Reel, 1000
ADS7808UB
ADS7808UB
"
ADS7808UB/1K
Tube, 38
Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified.
ADS7808U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise(2)
Full Scale Error(3,4)
Full Scale Error Drift
Full Scale Error(3,4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Unipolar Zero Error(3)
Unipolar Zero Error Drift
Recovery to Rated Accuracy
after Power Down
Power Supply Sensitivity
(VDIG = VANA = VD)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Full-Power Bandwidth(6)
2
MIN
TYP
12
ANALOG INPUT
Voltage Ranges
Impedance
Capacitance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
ADS7808UB
MAX
MAX
UNITS
✻
Bits
±10V, 0V to 5V, etc. (See Table I)
See Table I
35
✻
5.7
Acquire and Convert
✻
8
10
±0.9
±0.9
±7
±2
±2
±2
1
±0.5
±5
±0.5
80
70
70
±0.45
±0.45
LSB(1)
LSB
90
–90
73
73
250
±0.25
±0.25
✻
±10
✻
±2
±5
±3
±3
✻
✻
✻
✻
✻
±0.5
+4.75V < VD < +5.25V
45kHz
45kHz
45kHz
45kHz
µs
µs
kHz
✻
✻
Specified
0.1
fIN =
fIN =
fIN =
fIN =
✻
✻
✻
100
Ext. 2.5000V Ref
Ext. 2.5000V Ref
Bipolar Ranges
Bipolar Ranges
0V to 10V Range
0V to 4V Range
0V to 5V Range
Unipolar Ranges
1µF Capacitor to CAP
pF
✻
✻
–80
72
72
✻
✻
✻
✻
✻
✻
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
mV
mV
ppm/°C
ms
LSB
dB(5)
dB
dB
dB
kHz
ADS7808
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SBAS018A
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified.
ADS7808U
PARAMETER
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer)
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
VIL
VIH(8)
IIL
IIH
DIGITAL OUTPUTS
Data Format
Data Coding
Pipeline Delay
Data Clock
Internal
(Output Only When
Transmitting Data)
External
(Can Run Continually)
VOL
VOH
Leakage Current
Output Capacitance
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Power Dissipation: PWRD LOW
PWRD HIGH
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (θJA)
SO
CONDITIONS
MIN
TYP
ADS7808UB
MAX
MIN
No Load
MAX
✻
✻
40
Sufficient to meet AC specs
2
150
FS Step
TYP
✻
✻
2.5
1
2.52
✻
✻
✻
✻
V
µA
2.3
2.5
2.7
✻
✻
✻
V
✻
µA
✻
✻
✻
✻
V
V
µA
µA
100
–0.3
+2.0
+0.8
VD +0.3V
±10
±10
VIL = 0V
VIH = 5V
✻
✻
Serial 12 bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
2.3
✻
EXT/INT HIGH
0.1
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
VOUT = 0V to VDIG
High-Z State
10
✻
+0.4
+4.75
+5
0.3
16
+5
+5.25
VDIG = VANA = 5V, fS = 100kHz
✻
±5
✻
15
15
pF
✻
V
mA
mA
✻
V
+5.25
✻
✻
✻
✻
✻
✻
✻
100
75
MHz
V
V
µA
✻
50
–40
–55
–65
MHz
✻
✻
+4
Must be ≤ VANA
+4.75
ns
ns
µs
ns
2.48
Ext. 2.5000V Ref
EXT/INT LOW
UNITS
+85
+125
+150
✻
✻
✻
✻
✻
✻
✻
°CW
mW
µW
°C
°C
°C
✻ Specifications same as ADS7808U.
NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of
–Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and
includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum VIH level for the DATACLK
signal is 3V.
ADS7808
SBAS018A
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3
PIN ASSIGNMENTS
PIN #
NAME
1
R1IN
2
AGND1
3
R2IN
DESCRIPTION
Analog Input. See Table I and Figure 4 for input range connections.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Analog Input. See Table I and Figure 4 for input range connections.
4
R3IN
Analog Input. See Table I and Figure 4 for input range connections.
5
CAP
Reference Buffer Capacitor. 2.2µF Tantalum to ground.
6
REF
Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,
bypass to ground with a 2.2µF Tantalum capacitor.
7
AGND2
Analog Ground.
8
SB/BTC
Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If
LOW, data will be output in a Binary Two’s complement format.
9
EXT/INT
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If
LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output
on DATACLK.
10
DGND
Digital Ground.
11
SYNC
Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a
pulse on SYNC synchronized to the external DATACLK.
12
DATACLK
13
DATA
14
TAG
Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12
DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.
15
R/C
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a
rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,
DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions.
Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock
mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If
EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the
level of the TAG input when the conversion was started.
16
CS
17
BUSY
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.
Chip Select. Internally OR’ed with R/C.
18
PWRD
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous
conversion are maintained in the output shift register.
19
VANA
Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
20
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA.
PIN CONFIGURATION
R1IN
1
AGND1
2
19 VANA
R2IN
3
18 PWRD
R3IN
4
17 BUSY
CAP
5
REF
6
15 R/C
AGND2
7
14 TAG
SB/BTC
8
13 DATA
EXT/INT
9
12 DATACLK
DGND 10
4
20 VDIG
ADS7808
ANALOG
INPUT
RANGE
CONNECT R1IN
VIA 200Ω
TO
±10V
±5V
±3.33
0V to 10V
0V to 5V
0V to 4V
VIN
AGND
VIN
AGND
AGND
VIN
CONNECT R2IN
VIA 100Ω
CONNECT R3IN
TO
TO
AGND
VIN
VIN
VIN
AGND
AGND
CAP
CAP
CAP
AGND
VIN
VIN
IMPEDANCE
22.9kΩ
13.3kΩ
10.7kΩ
13.3kΩ
10.0kΩ
10.7kΩ
16 CS
TABLE I. Input Range Connections. See Figure 4 for
complete information.
11 SYNC
ADS7808
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SBAS018A
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
t1
Convert Pulse Width
t2
BUSY Delay
65
ns
t3
BUSY LOW
8
µs
t4
BUSY Delay after
End of Conversion
220
ns
t5
Aperture Delay
40
ns
t6
Conversion Time
5.7
t7
Acquisition Time
t6 + t7
Throughput Time
40
4500
t1
CS, R/C
ns
t3
BUSY
t2
t4
t5
MODE Acquire
9
8
µs
2
µs
10
µs
t8
R/C LOW to DATACLK Delay
450
ns
t9
DATACLK Period
440
ns
t10
Data Valid to DATACLK
HIGH Delay
20
75
ns
t11
Data Valid after
DATACLK LOW Delay
100
125
ns
t12
External DATACLK Period
100
t13
External DATACLK HIGH
20
ns
t14
External DATACLK LOW
30
ns
t15
DATACLK HIGH
Setup Time
20
t16
R/C to CS
Setup Time
10
t17
SYNC Delay After
DATACLK HIGH
15
35
55
Convert
Acquire
t6
t7
FIGURE 1. Basic Conversion Timing.
ns
t12 + 5
ns
ns
ns
t18
Data Valid Delay
25
t19
CS to Rising Edge Delay
25
ns
t20
Data Available after CS LOW
4.5
µs
ns
TABLE II. Conversion and Data Timing TA = –40°C to +85°C.
t8
R/C
t9
1
DATACLK
2
3
11
12
Bit 9 Valid
Bit 1 Valid
LSB Valid
t11
t10
SDATA
MSB Valid
Bit 10 Valid
t2
t3
BUSY
FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.)
ADS7808
SBAS018A
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5
SPECIFIC FUNCTION
CS
R/C
Initiate Conversion and
Output Data Using
Internal Clock
1>0
0
1
0
Output
0
x
Initiates conversion “n”. Data from conversion “n–1”
clocked out on DATA synchronized to 12 clock
pulses output on DATACLK.
0
1>0
1
0
Output
0
x
Initiates conversion “n”. Data from conversion “n–1”
clocked out on DATA synchronized to 12 clock
pulses output on DATACLK.
1>0
0
1
1
Input
0
x
Initiates conversion “n”.
0
1>0
1
1
Input
0
x
Initiates conversion “n”.
1>0
1
1
1
Input
x
x
Outputs a pulse on SYNC followed by data from
conversion “n” clocked out synchronized to external
DATACLK.
1>0
1
0
1
Input
0
x
Outputs a pulse on SYNC followed by data from
conversion “n–1” clocked out synchronized to
external DATACLK.(1) Conversion “n” in process.
0
0>1
0
1
Input
0
x
Outputs a pulse on SYNC followed by data from
conversion “n–1” clocked out synchronized to
external DATACLK .(1) Conversion “n” in process.
Incorrect Conversions
0
0
0>1
x
x
0
x
CS or R/C must be HIGH or a new conversion will
be initiated without time for acquisition.
Power Down
x
x
x
x
x
0
x
Analog circuitry powered. Conversion can proceed.
x
x
x
x
x
1
x
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
x
x
x
x
x
x
0
Serial data is output in Binary Two’s Complement
format.
x
x
x
x
x
x
1
Serial data is output in Straight Binary format.
Initiate Conversion and
Output Data Using External
Clock
BUSY EXT/INT DATACLK PWRD
SB/BTC
Selecting Output Format
OPERATION
NOTE: (1) See Figure 3b for constraints on previous data valid during conversion.
Table III. Control Truth Table.
DIGITAL OUTPUT
BINARY TWO’S
COMPLEMENT
(SB/BTC LOW)
DESCRIPTION
Full-Scale Range
Least Significant Bit (LSB)
+Full Scale (FS – 1LSB)
Midscale
One LSB Below Midscale
–Full Scale
HEX
BINARY CODE
CODE
HEX
BINARY CODE
3.99902V
0111 1111 1111
7FF
1111 1111 1111
FFF
2V
0000 0000 0000
000
1000 0000 0000
800
1.99902V
1111 1111 1111
FFF
0111 1111 1111
7FF
0V
1000 0000 0000
800
0000 0000 0000
000
ANALOG INPUT
±10
±5
±3.33V
4.88mV
2.44mV
1.63mV
9.99512V 4.99756V 3.33171V
0V
0V
0V
–4.88mV
–2.44mV
–1.63mV
–10V
–5V
–3.333333V
0V to 5V 0V to 10V
1.22mV
2.44mV
4.99878V 9.99756V
2.5V
5V
2.49878V 4.99756V
0V
0V
STRAIGHT BINARY
(SB/BTC HIGH)
CODE
0V to 4V
0.98mV
Table IV. Output Codes and Ideal Input Voltages.
6
ADS7808
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SBAS018A
FIGURE 3a. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion.
ADS7808
SBAS018A
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7
TAG
DATA
SYNC
BUSY
R/C
CS
EXTERNAL
DATACLK
t16
t2
t1
0
t13
t16
t12
t14
t17
t15
1
t12
Tag 0
t18
2
Tag 1
Bit 11 (MSB)
3
Tag 2
Bit 10
4
Tag 11
Bit 1
13
Tag 12
Bit 0 (LSB)
14
Tag 13
Tag 0
Tag 1
Tag 14
t19
Tag 15
Tag 15
Tag 14
Tag 13
Tag 1
Tag 1
t15
t17
Tag 0
t12
t18
t20
Bit 11 (MSB)
Tag 12
Bit 0 (LSB)
Tag 0
t19
t1
t14
t12
TAG
DATA
SYNC
BUSY
R/C
CS
EXTERNAL
DATACLK
t16
t2
t13
FIGURE 3b. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH.) Read During Conversion (Previous
Conversion Results).
8
ADS7808
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SBAS018A
Input Range
With Trim
(Adjust offset first at 0V, then adjust gain)
Without Trim
200Ω
200Ω
R1IN
R1IN
AGND1
AGND1
100Ω
100Ω
VIN
R2IN
33.2kΩ
R3IN
0V – 10V
R2IN
VIN
33.2kΩ
R3IN
+5V
2.2µF
CAP
+
CAP
50kΩ
2.2µF
576kΩ
REF
2.2µF
+
+5V
REF
50kΩ
+
+
2.2µF
AGND2
AGND2
200Ω
200Ω
R1IN
R1IN
AGND1
AGND1
100Ω
100Ω
R2IN
33.2kΩ
0V – 5V
R3IN
VIN
R2IN
33.2kΩ
R3IN
VIN
+5V
CAP
CAP
+
+5V
2.2µF
REF
2.2µF
576kΩ
+
50kΩ
2.2µF
REF
50kΩ
+
2.2µF
AGND2
AGND2
200Ω
200Ω
VIN
VIN
R1IN
R1IN
AGND1
AGND1
100Ω
100Ω
0V – 4V
R2IN
R2IN
R3IN
R3IN
33.2kΩ
2.2µF
+
+5V
CAP
+
33.2kΩ
+5V
2.2µF
REF
+
2.2µF
576kΩ
50kΩ
CAP
REF
50kΩ
2.2µF
AGND2
+
+
AGND2
FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges.
ADS7808
SBAS018A
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9
Input Range
With Trim
(Adjust offset first at 0V, then adjust gain)
Without Trim
200Ω
200Ω
VIN
VIN
R1IN
R1IN
AGND1
AGND1
100Ω
100Ω
R2IN
±10V
R2IN
+5V
33.2kΩ
R3IN
33.2kΩ
R3IN
50kΩ
+5V
CAP
+
2.2µF
576kΩ
2.2µF
REF
2.2µF
CAP
+
REF
50kΩ
+
2.2µF
+
AGND2
AGND2
200Ω
200Ω
R1IN
R1IN
AGND1
AGND1
100Ω
100Ω
R2IN
VIN
33.2kΩ
R2IN
VIN
33.2kΩ
±5V
R3IN
2.2µF
+5V
CAP
+
REF
2.2µF
CAP
+5V
50kΩ
2.2µF
R3IN
+
576kΩ
REF
50kΩ
+
+
2.2µF
AGND2
AGND2
200Ω
200Ω
VIN
VIN
R1IN
100Ω
R1IN
AGND1
100Ω
AGND1
R2IN
R2IN
±3.33V
R3IN
33.2kΩ
R3IN
33.2kΩ
2.2µF
+5V
CAP
+
CAP
+5V
50kΩ
+
576kΩ
REF
2.2µF
+
REF
50kΩ
+
2.2µF
AGND2
2.2µF
AGND2
FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges.
10
ADS7808
www.ti.com
SBAS018A
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7808P
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
ADS7808PB
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
ADS7808U
NRND
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
ADS7808U
ADS7808U/1K
NRND
SOIC
DW
20
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
ADS7808U
ADS7808U/1KE4
NRND
SOIC
DW
20
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
ADS7808U
ADS7808UB
NRND
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
ADS7808U
B
ADS7808UBG4
NRND
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
ADS7808U
B
ADS7808UE4
NRND
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
ADS7808U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS7808U/1K
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7808U/1K
SOIC
DW
20
1000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS7808U
ACTIVE
SOIC
DW
20
25
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7808U
Samples
ADS7808U/1K
ACTIVE
SOIC
DW
20
1000
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7808U
Samples
ADS7808UB
ACTIVE
SOIC
DW
20
25
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
ADS7808U
B
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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