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ADS7810U

ADS7810U

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC28

  • 描述:

    IC 12 BIT A/D CONV 28 SOIC

  • 数据手册
  • 价格&库存
ADS7810U 数据手册
ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 12-Bit, 800kHz Sampling CMOS ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS7810 FEATURES 1 • • • • • • • • 2 DESCRIPTION 1.25ms Throughput Time Standard ±10V Input Range 69dB Min SINAD With 250kHz Input ±3 LSB Max INL and ±3 LSB Max DNL Internal Reference Complete With S/H, REF, CLOCK, ETC. Parallel Data w/Latches 28-PIN SOIC Package The ADS7810 is a complete 12-bit sampling analog-to-digital converter (A/D) using state-of-the-art CMOS structures. It contains a complete 12-bit capacitor-based SAR A/D with inherent S/H, reference, clock, interface for microprocessor use, and 3-state output drivers. The ADS7810 is specified at an 800kHz sampling rate, and ensured over the full temperature range. Laser-trimmed scaling resistors provide the industry-standard ±10V input range, while an innovative design allows operation from ±5V supplies. The 28-pin ADS7810 is available in a plastic SOIC fully specified for operation over the industrial –40°C to +70°C range. Successive Approximation Register and Control Logic Clock CDAC 2450W ±10V Input 625W Comparator Output Latches and 3-State Drivers BUSY 3-State Parallel Data Bus Cap 18kW Buffer 4.8kW 2.5V Ref Out/In 8.6kW Internal Ref 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992–2010, Texas Instruments Incorporated ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS7810 UNIT ±25 V AnalogREF +VANA +0.3 to AGND2 –0.3 V AnalogCAP Indefinite Short to AGND2 Momentary Short to +VANA V ±0.3 V +7 V +0.3 V +VDIG +7 V –VANA –7 V Analog inputs: VIN Ground voltage differences: DGND, AGND1, AGND2 +VANA +VDIG to +VANA Digital inputs –0.3 to +VDIG +0.3 V Maximum junction temperature +165 °C Internal power dissipation 825 mW (1) 2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS At TA = –40°C to +70°C, fS = 800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 16, unless otherwise specified. ADS7819UB (1) ADS7810U PARAMETER TEST CONDITIONS UNIT MIN TYP RESOLUTION MAX MIN TYP 12 MAX 12 Bits ANALOG INPUT Voltage range +In – (–In) Impedance Capacitance ±10 ±10 V 3.1 3.1 kΩ 5 5 pF THROUGHPUT SPEED Conversion cycle t3 + t4 Complete cycle Acquire and convert Throughput rate 1020 1020 1250 800 ns 1250 ns 800 kHz DC ACCURACY Integral linearity error ±3 ±2 LSB Differential linearity error ±3 ±3 LSB No missing codes Ensured Transition noise (2) 0.1 Full-scale error (3) (4) Ensured 0.1 ±1 Full-scale error drift ±12 Full-scale error (3) (4) Ext. 2.5000V Ref Full-scale error drift Ext. 2.5000V Ref ±12 ±1 ±12 ±8 Bipolar zero error drift +4.75V < VD < +5.25V –5.25V < –VANA < –4.75V % ppm/°C ±4 ±2 Power-supply sensitivity (+VDIG = +VANA = VD) % ppm/°C ±1 ±12 Bipolar zero error (3) LSB ±0.75 ±2 LSB ppm/°C ±5 ±5 LSB ±0.5 ±0.5 LSB AC ACCURACY 74 82 fIN = 250kHz Total harmonic distortion fIN = 250kHz Signal-to-(noise+distortion) fIN = 250kHz 67 71 69 71 Signal-to-noise fIN = 250kHz 66 71 70 71 dB 1.5 1.5 MHz Aperture delay 20 20 ns Aperture jitter 10 10 ps 200 200 ns 250 250 ns –80 Usable bandwidth (6) 77 dB (5) Spurious-free dynamic range –74 84 –82 –77 dB dB SAMPLING DYNAMICS Transient response Full-scale step Overvoltage recovery (7) REFERENCE Internal reference voltage 2.48 Internal reference dc source current (external load should be static) Internal reference drift External reference voltage range for specified linearity External reference current drain 2.3 2.5 2.52 2.48 2.5 100 100 8 8 2.5 Ext. 2.5000V Ref 2.7 2.3 100 2.5 2.52 V mA ppm/°C 2.7 V 100 mA V DIGITAL INPUTS Logic levels (1) (2) (3) (4) (5) (6) (7) VIL –0.3 +0.8 –0.3 +0.8 VIH +2.4 VD + 0.3 +2.4 VD + 0.3 V IIL VIL = 0V ±10 ±10 mA IIH VIH = 5V ±10 ±10 v Shaded cells indicate same specifications as the ADS7810U. Typical rms noise at worst-case transitions and temperatures. Measured with 50Ω in series with analog input. Adjustable to zero with external potentiometer. Full-scale error is the worst case of –Ful-Scale or +Full-Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. All specifications in dB are referred to a full-scale ±10V input. Usable bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. Recovers to specified performance after 2 x FS input over voltage. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 3 ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +70°C, fS = 800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 16, unless otherwise specified. ADS7819UB (1) ADS7810U PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX DIGITAL OUTPUTS Data format Data coding VOL ISINK = 1.6mA VOH ISOURCE = 500mA Parallel 12 bits Parallel 12 bits Binary twos complement Binary twos complement +0.4 +2.8 +0.4 V +2.8 V Leakage current High-Z state, VOUT = 0V to VDIG ±5 ±5 mA Output capacitance High-Z state 15 15 pF Bus access time 62 62 ns Bus relinquish time 83 83 ns +5 +5.25 V –5 –4.75 DIGITAL TIMING POWER SUPPLIES Specified performance Derated performance +VDIG = +VANA +4.75 –VANA –5.25 +5 +5.25 +4.75 –5 –4.75 –5.25 V +IDIG +16 +16 mA +IANA +16 +16 mA –IANA –13 –13 +VDIG = +VANA +4.5 –VANA Power dissipation –5.5 fS = 800kHz +5 +5.5 +4.5 –5 –4.5 –5.5 225 275 mA +5 +5.5 V –5 –4.5 V 225 275 mW TEMPERATURE RANGE Specified performance –40 +70 –40 +70 °C Derated performance –55 +125 –55 +125 °C Storage –65 +150 –65 +150 Thermal resistance (qJA) 4 °C Plastic DIP 75 75 °C/W SOIC 75 75 °C/W Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 TIMING INFORMATION t1 R/C t12 t2 t3 t5 t4 BUSY t6 Acquire MODE DATA BUS Convert Acquire t7 t8 Hi-Z State Data Valid Convert Data Valid Hi-Z State t10 t9 Figure 1. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) t11 t11 t11 t11 R/C t1 CS t3 t5 t4 BUSY t6 MODE Convert Acquire Acquire t7 t2 DATA BUS Hi-Z State Data Valid t13 Hi-Z State t9 Figure 2. Using CS to Control Conversion and Read Timing TIMING REQUIREMENTS (TMIN to TMAX) SYMBOL DESCRIPTION MIN TYP MAX 955 1095 ns 70 125 ns 950 1080 ns t1 Convert pulse width t2 Data valid delay after R/C low t3 BUSY delay from R/C low t4 BUSY low t5 BUSY delay after end of conversion 90 t6 Aperture delay 20 t7 Conversion time t8 Acquisition time t7, t8 Throughput time UNIT 40 ns 910 ns ns 1020 ns 200 230 ns 1110 1250 ns t9 Bus relinquish time 10 50 83 ns t10 BUSY delay after data valid 20 65 120 ns t11 R/C to CS setup time 10 t12 Time between conversions t13 Bus access time ns 1250 10 ns 25 62 Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ns 5 ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com PIN CONFIGURATION DW PACKAGE SOIC-28 (TOP VIEW) (1) VIN 1 28 +VANA AGND1 2 27 +VDIG REF 3 26 -VANA CAP 4 25 BUSY AGND2 5 24 CS D11 (MSB) 6 23 R/C D10 7 22 DGND D9 8 21 +VDIG D8 9 20 +VANA D7 10 19 NC D6 11 18 D0 (LSB) D5 12 17 D1 D4 13 16 D2 DGND 14 15 D3 (1) Not internally connected. PIN ASSIGNMENTS PIN NO. 6 NAME DIGITAL I/O DESCRIPTION 1 VIN 2 AGND1 Analog input. Connect via 50Ω to analog input. Full-scale input range is ±10V. 3 REF Reference input/output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both cases, decouple to ground with a 0.1mF ceramic capacitor. 4 CAP Reference buffer output. 10mF tantalum capacitor to ground. Nominally +2V. 5 AGND2 6 D11 (MSB) O Data bit 11. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 7 D10 O Data bit 10. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 8 D9 O Data bit 9. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 9 D8 O Data bit 8. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 10 D7 O Data bit 7. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 11 D6 O Data bit 6. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 12 D5 O Data bit 5. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 13 D4 O Data bit 4. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 14 DGND 15 D3 Analog ground. Used internally as ground reference point. Minimal current flow. Analog ground. Digital ground. O Data bit 3. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 PIN ASSIGNMENTS (continued) PIN NO. NAME DIGITAL I/O 16 D2 O Data bit 2. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 17 D1 O Data bit 1. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 18 D0 (LSB) O Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in progress. 19 NC 20 +VANA Analog positive supply input. Nominally +5V. Connect directly to pins 21, 27, and 28. 21 +VDIG Digital supply input. Nominally +5V. Connect directly to pins 20, 27, and 28. 22 DGND Digital ground. 23 R/C I Read/Convert input. With CS low, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. With CS low and no conversion in progress, a rising edge on R/C enables the output data bits. 24 CS I Chip select. With R/C low, a falling edge on CS will initiate a conversion. With R/C high and no conversion in progress, a falling edge on CS will enable the output data bits. 25 BUSY O Busy output. Falls when a conversion is started, and remains low until the conversion is completed and the data are latched into the output register. With CS low and R/C high, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. 26 –VANA Analog negative supply input. Nominally –5V. Decouple to ground with 0.1mF ceramic and 10vF tantalum capacitors. 27 +VDIG Digital supply input. Nominally +5V. Connect directly to pins 20, 21, and 28. 28 +VANA Analog positive supply input. Nominally +5V. Connect directly to pins 20, 21, and 27, and decouple to ground with 0.1mF ceramic and 10mF tantalum capacitors. DESCRIPTION Not internally connected. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 7 ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistors as shown in Figure 16, unless otherwise specified. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 502kHz, –0.5dB) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 252kHz, –0.5dB) -60 -80 -60 -80 -100 -100 -120 -120 0 100 200 300 400 0 100 400 Figure 4. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1002kHz, –0.5dB) FREQUENCY SPECTRUM (4096 Point f1IN = 232kHz, –6.5dB; f2IN = 272kHz, –6.5dB) 0 0 -20 -20 -40 -40 -60 -80 -60 -80 -100 -120 -120 0 100 200 300 400 0 100 Frequency (kHz) 200 300 400 Frequency (kHz) Figure 5. Figure 6. SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY (fIN = –0.5dB) AC PARAMETERS vs TEMPERATURE (fIN = 250kHz, –0.5dB) 100 80 95 60 50 40 30 20 10 -100 -95 SFDR 90 -90 85 -85 80 -80 THD SNR 75 -75 -70 70 SINAD -65 65 -60 60 1k 10k 100k 1M 10M THD (dB) SFDR, SNR, and SINAD (dB) 90 70 SINAD (dB) 300 Figure 3. -100 -50 Input Signal Frequency (Hz) -25 0 25 50 75 100 Temperature (°C) Figure 7. 8 200 Frequency (kHz) Amplitude (dB) Amplitude (dB) Frequency (kHz) Figure 8. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistors as shown in Figure 16, unless otherwise specified. CODE TRANSITION NOISE Conversions Yielding Expected Code (%) 12-Bit LSBs 1 0.5 0 -0.5 All Codes INL -1 0 512 1024 1536 2048 2560 3072 3584 4096 Decimal Code 12-Bit LSBs 1 0.5 0 -0.5 100 75 50 25 0 All Codes DNL -1 0 512 1024 0 1536 2048 2560 3072 3584 0.25 0.5 0.75 1 Analog Input Voltage: Expected Code Center (LSBs) 4096 Decimal Code Figure 9. Figure 10. Offset Error 2.515 Internal Reference (V) LSB From Ideal Percent From Ideal 0.2 0.1 0 -0.1 -0.2 INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.520 +FS Error 2.510 2.505 THD (dB) 0.2 0.1 0 -0.1 -0.2 Percent From Ideal DC PARAMETERS vs TEMPERATURE 2 1 0 -1 -2 2.500 2.495 2.490 2.485 2.480 -FS Error -75 -50 -50 -25 0 25 75 50 100 125 -25 0 25 50 75 100 Temperature (°C) 150 Temperature (°C) Figure 11. Figure 12. CONVERSION TIME (t7) vs TEMPERATURE 1200 Conversion Time (ns) 1150 1100 1050 1000 950 900 850 800 750 -50 -25 0 25 50 75 100 Temperature (°C) Figure 13. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 9 ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION BASIC OPERATION Figure 14 shows a basic circuit to operate the ADS7810. Taking R/C (pin 23) low for a minimum of 40ns will initiate a conversion. BUSY (pin 25) will go low and stay low until the conversion is completed and the output registers are updated. Data will be output in binary twos complement with the MSB on D11 (pin 6). BUSY going high can be used to latch the data. All convert commands will be ignored while BUSY is low. The ADS7810 will begin tracking the input signal at the end of the conversion. Allowing 1.25ms between convert commands assures accurate acquisition of a new signal. STARTING A CONVERSION The ADS7810 will begin tracking the input signal at the end of the conversion. Allowing 1.25ms between convert commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY states, and Figure 1 and Figure 2 for timing parameters. CS and R/C are internally OR’d and level triggered. There is not a requirement which input goes low first when initiating a conversion. If it is critical that CS or R/C initiate the conversion, be sure the less critical input is low at least 10ns prior to the initiating input. To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. Note that the parallel output will be active whenever R/C is HIGH and no conversion is in progress. See the Reading Data section and refer to Table 1 for control line functions for ‘read’ and ‘convert’ modes. The combination of CS (pin 24) and R/C (pin 23) low for a minimum of 40ns puts the sample/hold of the ADS7810 in the hold state and starts a conversion. BUSY (pin 25) will go low and stay low until the conversion is completed and the internal output register has been updated. All new convert commands during BUSY low will be ignored. 0.1mF 10mF + + 50W 1 28 2 27 3 26 4 25 5 24 D11 (MSB) 6 23 D10 7 ±10V 0.1mF 10mF + 0.1mF 10mF + +5V -5V + BUSY Convert Pulse 22 ADS7810 D9 8 21 D8 9 20 D7 10 19 D6 11 18 D0 (LSB) D5 12 17 D1 D4 13 16 D2 14 15 D3 40ns min NC Figure 14. Basic Operation 10 Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 READING DATA INPUT RANGES The ADS7810 outputs full parallel data in binary twos complement data format. The parallel output will be active when R/C (pin 23) is high, CS (pin 24) is low, and no conversion is in progress. Any other combination will 3-state the parallel output. Valid conversion data can be read in a full parallel, 12-bit word on D11-D0 (pins 6-13 and 15- 18). Refer to Table 2 for ideal output codes. The ADS7810 offers a standard ±10V input range. Figure 15 and Figure 16 show the necessary circuit connections for the ADS7810 with and without external trim. Offset and full-scale error (1) specifications are tested and ensured with the 50Ω resistor shown in Figure 16. This external resistor makes it possible to trim the offset ±50mV using a trim pot or trim DAC. This resistor may be left out if the offset and gain errors will be corrected in software or if they are negligible in regards to the particular application. See the Calibration section of the data sheet for details. After the conversion is completed and the output registers have been updated, BUSY (pin 25) will go high. Valid data from the most recent conversion will be available on D11-D0 (pins 6-13 and 15-18). BUSY going high can be used to latch the data. Refer to Timing Requirements as well as Figure 1 and Figure 2. NOTE: For the best performance, the external data bus connected to D11-D0 should not be active during a conversion. The switching noise of the external asynchronous data signals can cause digital feedthrough degrading the converter performance. The number of control lines can be reduced by tying CS low while using R/C to initiate conversions and activate the output mode of the converter. See Figure 1. The nominal input impedance of 3.125kW results from the combination of the internal resistor network shown on the front page of the product data sheet and external 50Ω resistor. The input resistor divider network provides inherent overvoltage protection ensured to at least ±25V. The 50Ω, 1% resistor does not compromise the accuracy or drift of the converter. It has little influence relative to the internal resistors, and tighter tolerances are not required. NOTE: The values shown for the internal resistors are for reference only. The exact values can vary by ±30%. This is true of all resistors internal to the ADS7810. Each resistive divider is trimmed so that the proper division is achieved. (1) Full-scale error includes offset and gain errors measured at both +FS and –FS. 50W VIN VIN +5V R1 5kW P1 5kW 50W VIN VIN AGND1 R2 604kW AGND1 5V REF Ð5V REF P2 5kW 0.1mF 10mF 0.1mF CAP + CAP 10mF AGND2 + AGND2 Note: Use 1% metal film resistors. Trim offset at 0V first, then trim gain at 10V. Figure 15. Circuit Diagram with External Hardware Trim Figure 16. Circuit Diagram without External Hardware Trim Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 11 ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com Table 1. Control Line Functions for ‘Read’ and ‘Convert’ CS R/C BUSY 1 X X None. Databus in Hi-Z state. OPERATION ↓ 0 1 Initiates conversion. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion. Databus enters Hi-Z state. 0 1 ↑ Conversion completed. Valid data from the most recent conversion on the databus. ↓ 1 1 Enables databus with valid data from the most recent conversion. ↓ 1 0 Conversion in progress. Databus in Hi-Z state, enabled when the conversion is completed. 0 ↑ 0 Conversion in progress. Databus in Hi-Z state, enabled when the conversion is completed. 0 0 ↑ Conversion completed. Valid data from the most recent conversion in the output register, but output pins D11-D0 are 3-stated. X X 0 New convert commands ignored. Conversion in progress. Table 2. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full-Scale Range ±10V BINARY TWOS COMPLEMENT Least Significant Bit (LSB) 4.88mV BINARY CODE HEX CODE +Full-Scale (10V – 1LSB) 9.995V 0111 1111 1111 7FF Midscale 0V 0000 0000 0000 000 One LSB below Midscale –4.88mV 1111 1111 1111 FFF –Full-Scale –10V 1000 0000 0000 800 CALIBRATION Software Calibration The ADS7810 can be trimmed in hardware or software. The offset should be trimmed before the gain since the offset directly affects the gain. To calibrate the offset and gain of the ADS7810, no external resistors are required. See the No Calibration section for details on the effects of the external resistor. Hardware Calibration No Calibration To calibrate the offset and gain of the ADS7810, install the proper resistors and potentiometers as shown in Figure 15. The calibration range is ±50mV for bipolar zero and ±120mV for full scale. Potentiometer P1 and resistor R1 form the offset adjust circuit and P2 and R2 the gain adjust circuit. The exact values are not critical. R1 and R2 should not be made any larger than the value shown. They can easily be made smaller to provide increased adjustment range. Reducing these below 15% of the indicated values could begin to adversely affect the operation of the converter. P1 and P2 can also be made larger to reduce power dissipation. However, larger resistances will push the useful adjustment range to the edges of the potentiometer. P1 should probably not exceed 20kΩ and P2 100kΩ in order to maintain reasonable sensitivity. 12 See Figure 16 for circuit connections. Note that the actual voltage dropped across the 50Ω resistor is nearly two orders of magnitude lower than the voltage dropped across the internal resistor divider network. This should be taken into consideration when choosing the accuracy and drift specifications of the external resistors. In most applications, 1% metal-film resistors will be sufficient. The external 50Ω resistor shown in Figure 16 may not be necessary in some applications. This resistor provides trim capability for the offset and compensates for a slight gain adjustment internal to the ADS7810. Not using the 50Ω resistor will cause a small gain error but will have no effect on the inherent offset error. Figure 17 shows typical transfer function characteristics with and without the 50Ω resistor in the circuit. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 REFERENCE limit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The internal reference should not be used to sink or source currents greater than 100mA. In addition, all external loads should be static. The ADS7810 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 3, the internal reference can be bypassed. The reference voltage at REF is buffered internally and output on CAP (pin 4). The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full-scale range and the LSB size of the converter which can improve the SNR. REF REF (pin 3) is an input for an external reference or the output for the internal 2.5V reference. A 0.1mF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low pass filter to band Digital Output +Full-Scale -10.0V -9.84V 9.84V 10.0V Analog Input Typical Transfer Function with 50W Resistor Typical Transfer Function without 50W Resistor -Full-Scale Figure 17. Comparison of the ADS7810 Transfer Function with and without the 50Ω Series Resistor on VIN Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 13 ADS7810 SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 www.ti.com CAP CAP (pin 4) is the output of the internal reference buffer. A 10mF tantalum capacitor should be placed as close to the CAP as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the buffer. Using a capacitor any smaller than 1mF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 10mF will have little effect on improving performance. The voltage on the CAP pin is approximately 2V when using the internal reference, or 80% of an externally supplied reference. LAYOUT POWER The ADS7810 uses the majority of its power for analog and static circuitry, and it should be considered as an analog component. For optimum performance, tie the analog and digital +5V power pins to the same +5V power supply and tie the analog and digital grounds together. For best performance, the ±5V supplies can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If ±12V or ±15V supplies are present, simple regulators can be used. The +5V power for the A/D should be separate from the +5V used for the system’s digital logic. Connecting +VDIG (pin 27) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. GROUNDING Three ground pins are present on the ADS7810. DGND (pin 22) is the digital supply ground. AGND2 (pin 5) is the analog supply ground. AGND1 (pin 2) is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the ADS should be tied to the analog ground plane, separated from the system digital logic ground, to achieve optimum performance. 14 Both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The resistive front end of the ADS7810 attenuates this charge and reduces its magnitude significantly—reducing the burden on the external input amplifier or buffer. However, keep in mind that maintaining signal integrity at voltage swings of ±10V and frequencies of several hundred kilohertz is extremely challenging. In addition, the external input amplifier must drive the ADS7810 mainly during its sample period—roughly 200ns. This will require a highspeed, precision amplifier which can swing to greater than ±10V. For signals where the predominant frequencies are below 200kHz, the OPA671 operational amplifier should be adequate for most applications. In some cases or where input frequencies are higher, a composite configuration of the OPA671 and BUF634 (in its wide bandwidth mode) may be the best choice. See the BUF634 data sheet for more information. The resistive front end of the ADS7810 also provides an ensured ±25V over voltage protection. In most cases, this eliminates the need for external input protection circuitry. INTERMEDIATE LATCHES The ADS7810 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversions, the 3-state outputs can be used to isolate the A/D from other peripherals on the same bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7810 has an internal LSB size of 610mV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 ADS7810 www.ti.com SBAS014A – MARCH 1992 – REVISED SEPTEMBER 2010 REVISION HISTORY Changes from Original (March, 1998) to Revision A Page • Updated document format to meet current standards .......................................................................................................... 1 • Updated Features list item indicating max INL and DNL specifications ............................................................................... 1 • Changed indicated temperature range in Description section .............................................................................................. 1 • Updated Ordering Information table ..................................................................................................................................... 2 • Changed temperature range for Electrical Characteristics measurement conditions ........................................................... 3 • Changed ADS7810U integral linearity error to ±3 LSB ........................................................................................................ 3 • Changed ADS7810UB integral linearity error to ±3 LSB ...................................................................................................... 3 • Changed differential linearity error for both ADS7810U and ADS7810UB to ±3 LSB .......................................................... 3 • Changed ADS7810U full-scale error to ±3 LSB ................................................................................................................... 3 • Changed ADS7810UB full-scale error to ±3 LSB ................................................................................................................. 3 • Changed ADS7810U full-scale error with ext.2.5V Ref to ±1 LSB ....................................................................................... 3 • Changed ADS7810UB full-scale error with ext.2.5V Ref to ±1 LSB ..................................................................................... 3 • Changed temperature range for Electrical Characteristics measurement conditions ........................................................... 4 • Changed specified temperature range to –40°C to +70°C ................................................................................................... 4 Submit Documentation Feedback Copyright © 1992–2010, Texas Instruments Incorporated Product Folder Link(s): ADS7810 15 PACKAGE OPTION ADDENDUM www.ti.com 15-Jun-2019 PACKAGING INFORMATION Orderable Device Status (1) ADS7810U LIFEBUY Package Type Package Pins Package Drawing Qty SOIC DW 28 20 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 85 ADS7810U B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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