ADS7862Y/2KG4

ADS ADS7862 786 ® 2 SBAS101B – JANUARY 1998 – REVISED AUGUST 2005 Dual 500kHz, 12-Bit, 2 + 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● The ADS7862 is a dual 12-bit, 500kHz analog-to-digital converter (A/D) with 4 fully differential input channels grouped into two pairs for high speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the A/D converter. This provides excellent common-mode rejection of 80dB at 50kHz, which is important in high noise environments. The ADS7862 offers parallel interface and control inputs to minimize software overhead. The output data for each channel is available as a 12-bit word. The ADS7862 is offered in an TQFP-32 package and is fully specified over the –40°C to +85°C operating range. 4 INPUT CHANNELS FULLY DIFFERENTIAL INPUTS 2µs TOTAL THROUGHPUT PER CHANNEL GUARANTEED NO MISSING CODES PARALLEL INTERFACE 1MHz EFFECTIVE SAMPLING RATE LOW POWER: 40mW APPLICATIONS ● MOTOR CONTROL ● MULTI-AXIS POSITIONING SYSTEMS ● 3-PHASE POWER CONTROL CH A0+ SAR CH A0– S/H Amp COMP Interface CDAC A0 CLOCK CH A1+ CH A1– CS Conversion and Control MUX RD BUSY REFIN CONVST Internal 2.5V Reference REFOUT Output Registers CH B0+ S/H Amp CH B0– Data Output 12 COMP CDAC CH B1+ CH B1– MUX SAR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1998-2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ORDERING INFORMATION(1) PRODUCT MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM GAIN ERROR (%) ±2 " ADS7862Y ADS7862Y ADS7862YB ADS7862YB PACKAGE PACKAGE DESIGNATOR SPECIFICATION TEMPERATURE RANGE ±0.75 TQFP-32 PBS –40°C to +85°C " " " " ±1 ±0.5 TQFP-32 PBS –40°C to +85°C " " " " " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS7862Y/250 ADS7862Y/2K5 ADS7862YB/250 ADS7862YB/2K5 Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTIONS Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V) REFIN ............................. –0.3V to (+VD + 0.3V) Digital Inputs to DGND .......................................... –0.3V to (+VD + 0.3V) Ground Voltage Differences: AGND, DGND ................................... ±0.3V +VD to AGND ......................... –0.3V to +6V Power Dissipation .......................................................................... 325mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C PIN NAME DESCRIPTION Reference Input 1 REFIN 2 REFOUT 3 AGND 4 +VA 5 DB11 Data Bit 11, MSB 6 DB10 Data Bit 10 7 DB9 Data Bit 9 8 DB8 Data Bit 8 9 DB7 Data Bit 7 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. 10 DB6 Data Bit 6 11 DB5 Data Bit 5 12 DB4 Data Bit 4 13 DB3 Data Bit 3 ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 14 DB2 Data Bit 2 15 DB1 Data Bit 1 16 DB0 17 BUSY 18 CONVST 19 CLOCK ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION CH A0+ CH A0– CH A1+ CH A1– CH B0– CH B0+ CH B1– CH B1+ Top View 32 31 30 29 28 27 26 25 REFIN 1 24 +VD REFOUT 2 23 DGND AGND 3 22 A0 Chip Select Synchronization pulse for the parallel output. During a Read operation, the first falling edge selects the A register and the second edge selects the B register, A0, then controls whether input 0 or input 1 is read. 22 A0 On the falling edge of Convert Start, when A0 is LOW Channel A0 and Channel B0 are converted and when it is HIGH, Channel A1 and Channel B1 are converted. During a Read operation, the first falling edge selects the A register and the second edge selects the B of RD register, A0, then controls whether input 0 or input 1 is read. Digital Ground. Connect directly to analog ground (pin 3). 21 RD 20 CS 23 DGND DB10 6 19 CLOCK 24 +VD DB9 7 18 CONVST 25 CH B1+ DB8 8 17 BUSY ADS7862 16 DB0 15 DB1 14 DB2 13 DB3 DB4 DB5 DB6 DB7 2 CS 5 12 Convert Start An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. The CLOCK pin controls the sampling rate by the equation: CLOCK 16 • fSAMPLE. RD 4 11 Data Bit 0, LSB HIGH when a conversion is in progress. 21 +VA 10 Analog Ground Analog Power Supply, +5VDC. Connect directly to digital power supply (pin 24). Decouple to analog ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor. 20 DB11 9 +2.5V Reference Output. Connect directly to REFIN (pin 1) when using internal reference. Digital Power Supply, +5VDC Non-Inverting Input Channel B1 26 CH B1– Inverting Input Channel B1 27 CH B0+ Non-Inverting Input Channel B0 28 CH B0– Inverting Input Channel B0 29 CH A1– Inverting Input Channel A1 30 CH A1+ Non-Inverting Input Channel A1 31 CH A0– Inverting Input Channel A0 32 CH A0+ Non-Inverting Input Channel A0 ADS7862 www.ti.com SBAS101B ELECTRICAL CHARACTERISTICS All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. ADS7862Y PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Input Voltage Range-Bipolar Absolute Input Range VCENTER = Internal VREF at 2.5V +IN –IN –VREF –0.3 –0.3 ✻ Referenced to REFIN Referenced to REFIN ±0.15 Referenced to REFIN ±0.15 At DC VIN = ±1.25VPP at 50kHz 80 80 120 ±0.5 ±2 1 ±0.5 ✻ ±0.5 ±0.5 ±3 3 ±0.75 2 ±0.75 2 ±0.1 ±0.1 ✻ ✻ ✻ ✻ ±2 ±2.5VPP ±2.5VPP ±2.5VPP ±2.5VPP at at at at 100kHz 100kHz 100kHz 100kHz 3.5 100 50 40 ✻ ✻ ✻ ✻ 75 71 –78 ✻ ✻ ✻ 1.2 2.5 ±25 50 2 0.005 65 2.5 0.05 5 2.525 ✻ 2.6 1 ✻ +VDD + 0.3 0.8 ✻ ✻ ✻ ✻ V V V pF µA ±1 ✻ ±1 ±2 2 ±0.5 1 ±0.5 1 ✻ 3.0 –0.3 3.5 0.4 0.2 8 Binary Two’s Complement ✻ 4.75 ✻ 5 5 25 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ Bits LSB LSB LSB LSB LSB % of FSR LSB % of FSR LSB dB dB µVRMS LSB µs µs kHz ns ps ps MHz ✻ ✻ ✻ dB dB dB dB V ppm/°C µVPP mA mV/µA dB V µA pF ✻ CMOS IIH = +5µA IIL = +5µA IOH = –500µA IOL = 500µA Bits ✻ –80 2.475 ✻ ✻ 500 = = = = UNITS ✻ ✻ 1.75 0.25 VIN VIN VIN VIN MAX ✻ ±0.75 0.5 ±0.75 ±0.75 VOLTAGE REFERENCE Internal Internal Drift Internal Noise Internal Source Current Internal Load Rejection Internal PSRR External Voltage Range Input Current Input Capacitance POWER SUPPLY REQUIREMENTS Power Supply Voltage, +V Quiescent Current, +VA Power Dissipation TYP ✻ ✻ 12 SAMPLING DYNAMICS Conversion Time per A/D Acquisition Time Throughput Rate Aperture Delay Aperture Delay Matching Aperture Jitter Small-Signal Bandwidth DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL External Clock Data Format +VREF VCC + 0.3 VCC + 0.3 15 ±1 CLK = GND Noise Power Supply Rejection Ratio DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range Channel-to-Channel Isolation MIN 12 Input Capacitance Input Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Integral Linearity Match Differential Linearity Bipolar Offset Error Bipolar Offset Error Match Positive Gain Error Positive Gain Error Match Negative Gain Error Negative Gain Error Match Common-Mode Rejection Ratio ADS7862YB MAX 5.25 8 40 ✻ ✻ ✻ ✻ V V V V MHz ✻ ✻ ✻ V mA mW ✻ ✻ ✻ ✻ ✻ Specifications same as ADS7862Y. ADS7862 SBAS101B www.ti.com 3 CH B1– 26 CH B1+ 25 CH B0+ 27 CH B0– 28 CH A1– 29 AGND 4 +VA 5 6 7 DB9 CONVST 18 8 DB8 BUSY 17 DGND 23 A0 22 Address Select RD 21 Read Input DB11 CS 20 Chip Select DB10 CLOCK 19 Clock Input Conversion Start Busy Output 16 DB0 15 DB1 14 DB2 ADS7862Y 9 4 CH A1+ 30 REFOUT 3 13 DB3 0.1µF 2 12 DB4 + +VD 24 11 DB5 10µF REFIN DB7 + 1 10 DB6 +5V Analog Supply CH A0– 31 CH A0+ 32 BASIC OPERATION ADS7862 www.ti.com SBAS101B TYPICAL PERFORMANCE CHARACTERISTICS At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 199.9kHz, –0.5dB) 0 0 –20 –20 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 99.9kHz, –0.5dB) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 62.5 125 187.5 250 0 62.5 125 Frequency (kHz) 187.5 250 Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 76 0.25 0.2 SNR Delta from +25°C (dB) SNR and SINAD (dB) 74 72 SINAD 70 68 0.15 SINAD 0.1 0.05 0 –0.05 SNR –0.1 66 –0.15 64 –0.25 –40 –0.2 1k 10k 100k 1M CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE CHANGE IN POSITIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Four Channels) 0.65 SFDR 0.25 0.25 0.05 0.05 –0.15 –0.15 –0.35 –0.35 THD –0.55 –0.55 –0.75 –0.75 –40 25 85 Temperature (°C) Change in Positive Gain Match (LSB) 0.45 0.45 0.6 THD Delta from +25°C (dB) SFDR Delta from +25°C (dB) 85 Temperature (°C) 0.65 0.5 0.4 0.3 0.2 0.1 0 –40 25 85 150 Temperature (°C) ADS7862 SBAS101B 25 Input Frequency (Hz) www.ti.com 5 TYPICAL PERFORMANCE CHARACTERISTICS (Cont.) At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. CHANGE IN REFERENCE VOLTAGE vs TEMPERATURE 2.51 0.2 0.18 0.16 Change in Reference (V) Change in Negative Gain Match (LSB) CHANGE IN NEGATIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Four Channels) 0.14 0.12 0.1 0.08 0.06 0.04 2.505 2.5 2.495 2.49 0.02 0 –40 25 85 2.485 –40 150 CHANGE IN BIPOLAR ZERO vs TEMPERATURE CHANGE IN BPZ MATCH vs TEMPERATURE Change in Bipolar Zero Match (LSB) Change in Bipolar Zero (LSB) B Channel 0.25 0 –0.25 A Channel –0.5 –0.75 –40 25 85 0.75 0.5 0.25 0 –40 150 25 85 150 Temperature (°C) Temperature (°C) INTEGRAL LINEARITY ERROR vs CODE CHANGE IN CMRR vs TEMPERATURE 1 86 0.8 85 Typical of All Four Channels 0.6 84 0.4 83 ILE (LSB) Change in CMRR (dB) 150 1 0.75 82 81 0.2 0 –0.2 –0.4 80 –0.6 79 78 –40 –0.8 –5 25 55 –1 800 85 000 7FF Hex BTC Code Temperature (°C) 6 85 Temperature (°C) Temperature (°C) 0.5 25 ADS7862 www.ti.com SBAS101B TYPICAL PERFORMANCE CHARACTERISTICS (Cont.) At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs TEMPERATURE 1 0.6 Typical of All Four Channels 0.75 0.4 Change in ILE (LSB) DLE (LSB) 0.5 0.25 0 –0.25 –0.5 –1 800 000 Negative ILE 25 85 DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE INTEGRAL LINEARITY ERROR MATCH vs CODE CHANNEL A0/CHANNEL A1 (Same Converter, Different Channels) 150 0.25 0.2 0.15 0.4 0.1 0.2 ILE (LSB) DLE Error (LSB) –0.4 Temperature (°C) 0.6 0 –0.2 –0.8 –40 0 –0.05 –0.15 –0.2 25 85 –0.25 800 150 000 7FF Temperature (°C) Hex BTC Code INTEGRAL LINEARITY ERROR MATCH vs CODE CHANNEL A0/CHANNEL B1 (Different Converter, Different Channels) INTEGRAL LINEARITY ERROR MATCH vs TEMPERATURE CHANNEL A0/CHANNEL B0 (Different Converter, Different Channels) 0.25 0.19 Change in ILE Match (LSB) 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 –0.25 800 0.05 –0.1 Negative DLE –0.6 ILE (LSB) –0.2 Hex BTC Code Positive DLE 000 0.18 0.17 0.16 0.15 0.14 0.13 0.12 –40 7FF 25 85 150 Temperature (°C) Hex BTC Code ADS7862 SBAS101B 0 –0.8 –40 7FF 0.8 –0.4 0.2 –0.6 –0.75 Positive ILE www.ti.com 7 INTRODUCTION The ADS7862 is a high speed, low power, dual 12-bit A/D converter that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual 2µs successive approximation A/Ds, two differential sample-and-hold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins and a high speed parallel interface. There are four analog inputs that are grouped into two channels (A and B) selected by the A0 input (A0 LOW selects Channels A0 and B0, while A0 HIGH selects Channels A1 and B1). Each A/D converter has two inputs (A0 and A1 and B0 and B1) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input voltage in the range of –VREF to +VREF, centered around the internal +2.5V reference. The part will also accept bipolar input ranges when a level shift circuit is used at the front end (see Figure 7). A conversion is initiated on the ADS7862 by bringing the CONVST pin LOW for a minimum of 15ns. CONVST LOW places both sample-and-hold amplifiers in the hold state simultaneously and the conversion process is started on both channels. The BUSY output will then go HIGH and remain HIGH for the duration of the conversion cycle. Depending on the status of the A0 pin, the data will either reflect a conversion of Channel 0 (A0 LOW) or Channel 1 (A0 HIGH). The data can be read from the parallel output bus following the conversion by bringing both RD and CS LOW. Conversion time for the ADS7862 is 1.75µs when an 8MHz external clock is used. The corresponding acquisition time is 0.25µs. To achieve maximum output rate (500kHz), the read function can be performed immediately at the start of the next conversion. REFERENCE Under normal operation, the REFOUT pin (pin 2) should be directly connected to the REFIN pin (pin 1) to provide an internal +2.5V reference to the ADS7862. The ADS7862 can operate, however, with an external reference in the range of 1.2V to 2.6V for a corresponding full-scale range of 2.4V to 5.2V. The internal reference of the ADS7862 is double-buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to pin 2 (the internal reference can typically source 2mA of current—load capacitance should not exceed 100pF). If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of both CDACs during conversion. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS7862: single-ended or differential (see Figures 1 and 2). When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode +VREF) and the (common-mode –VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 3). When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or: (+IN) – (–IN). The peak-to-peak amplitude of each input is ±1/2VREF around this common voltage. However, since the inputs are 180° out of phase, the peak-to-peak amplitude of the differential voltage is +VREF to –VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 4). NOTE: This mode of operation is described in more detail in the Timing and Control section of this data sheet. SAMPLE-AND-HOLD SECTION The sample-and-hold amplifiers on the ADS7862 allow the A/Ds to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the sample-and-hold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the A/D even when the A/D is operated at its maximum throughput rate of 500kHz. The typical small-signal bandwidth of the sampleand-hold amplifiers is 40MHz. Typical aperture delay time or the time it takes for the ADS7862 to switch from the sample to the hold mode following the CONVST pulse is 3.5ns. The average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). These specifications reflect the ability of the ADS7862 to capture AC input signals accurately at the exact same moment in time. 8 –VREF to +VREF peak-to-peak ADS7862 Common Voltage Single-Ended Input VREF peak-to-peak Common Voltage ADS7862 VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS7862 Single-Ended or Differential. ADS7862 www.ti.com SBAS101B +IN CM +VREF +VREF CM Voltage –IN = CM Voltage –VREF t CM –VREF CM +1/2VREF Single-Ended Inputs +IN +VREF CM Voltage –VREF CM –1/2VREF –IN t Differential Inputs (IN+) + (IN–) NOTES: Common-Mode Voltage (Differential Mode) = Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS7862 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. FIGURE 2. Using the ADS7862 in the Single-Ended and Differential Input Modes. 5 5 VCC = 5V 4.7 VCC = 5V 4.1 4 4 3 Common Voltage Range (V) Common Voltage Range (V) 4.05 2.7 Single-Ended Input 2.3 2 1 0.9 0 Differential Input 2 0.90 1 0.3 0 –1 1.0 3 –1 1.2 1.5 2.0 2.5 2.6 3.0 1.0 VREF (V) 1.2 1.5 2.0 2.5 2.6 3.0 VREF (V) FIGURE 3. Single-Ended Input: Common-Mode Voltage Range vs VREF. FIGURE 4. Differential Input: Common-Mode Voltage Range vs VREF. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Otherwise, this may result in offset error, which will change with both temperature and input voltage. capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (15pF) to a 12-bit settling level within 2 clock cycles. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. The input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS7862 charges the internal capacitor array during the sampling period. After this Care must be taken regarding the absolute analog input voltage. The +IN input should always remain within the range of GND – 300mV to VDD + 0.3V. ADS7862 SBAS101B www.ti.com 9 TRANSITION NOISE Figure 5 shows a histogram plot for the ADS7862 following 8,000 conversions of a DC input. The DC input was set at output code 2046. All but one of the conversions had an output code result of 2046 (one of the conversions resulted in an output of 2047). The histogram reveals the excellent noise performance of the ADS7862. 1.4V 3kΩ DATA Test Point 100pF CLOAD 8000 Number of Conversions 7000 VOH DATA 6000 VOL 5000 tR tF 4000 Voltage Waveforms for DATA Rise and Fall Times tR, and tF. 3000 2000 FIGURE 6. Test Circuits for Timing Specifications. 1000 0 2044 2045 2046 2047 2048 Code (decimal) R1 FIGURE 5. Histogram of 8,000 Conversions of a DC Input. BIPOLAR INPUTS The differential inputs of the ADS7862 were designed to accept bipolar inputs (–VREF and +VREF) around the internal reference voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring a single amplifier and four external resistors, the ADS7862 can be configured to except bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges can be interfaced to the ADS7862 using the resistor values shown in Figure 7. TIMING AND CONTROL The ADS7862 uses an external clock (CLOCK, pin 19) which controls the conversion rate of the CDAC. With an 8MHz external clock, the A/D sampling rate is 500kHz which corresponds to a 2µs maximum throughput time. 4kΩ OPA132 20kΩ Bipolar Input +IN –IN ADS7862 R2 REFOUT (pin 2) 2.5V BIPOLAR INPUT R1 R2 ±10V ±5V ±2.5V 1kΩ 2kΩ 4kΩ 5kΩ 10kΩ 20kΩ FIGURE 7. Level Shift Circuit for Bipolar Input Ranges. Three timing diagrams are used to explain the operation of the ADS7862. Figure 8 shows the timing relationship between the CLOCK, CONVST (pin 18) and the conversion tCKP tCKH tCKL CLOCK t3 CONVST CONVERSION MODE SAMPLE HOLD CONVERT NOTE: The ADS7862 will switch from the sample to the hold mode the instant CONVST goes LOW regardless of the state of the external clock. The conversion process is initiated with the first rising edge of the external clock following CONVST going LOW. FIGURE 8. Conversion Mode. 10 ADS7862 www.ti.com SBAS101B mode. Figure 9, in conjunction with Table I, shows the basic read/write functions of the ADS7862 and highlights all of the timing specifications. Figure 10 shows a more detailed description of initiating a conversion using CONVST. Figure 11 illustrates three consecutive conversions and, with the accompanying text, describes all of the read and write capabilities of the ADS7862. first followed by Channel 1. Channel 1 can be converted prior to Channel 0 if the user wishes by simply starting the conversion process with the A0 pin at logic HIGH (Channel 1) followed by logic LOW (Channel 0). TIMING SPECIFICATIONS SYMBOL DESCRIPTION Full-Scale Input Span Least Significant Bit (LSB) ANALOG INPUT –VREF to +VREF (1) DIGITAL OUTPUT BINARY TWO’S COMPLEMENT (–VREF to +VREF)/4096 (2) +Full Scale Midscale Midscale – 1 LSB BINARY CODE HEX CODE 4.99878V 0111 1111 1111 7FF 2.5V 0000 0000 0000 000 2.49878V 1111 1111 1111 FFF 0V 1000 0000 0000 800 –Full Scale tCONV tACQ tCKP tCKL tCKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 tF tR NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corresponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference. TABLE I. Ideal Input Voltages and Output Codes. The Figure 11 timing diagram can be divided into three sections: (a) initiating a conversion (n – 2), (b) starting a second conversion (n – 1) while reading the data output from the previous conversion (n – 2), and (c) starting a third conversion (n) while reading both previous conversions (n – 2 and n – 1). In this sequence, Channel 0 is converted CLOCK 1 2 3 4 5 14 tCONV CONVST t12 16 MIN 1 2 3 4 5 TYP 125 40 40 0 0 15 30 16 10 MAX UNITS 1.75 0.25 5000 µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 20 40 250 20 20 30 10 5 13 20 14 25 30 15 16 tACQ t13 t3 BUSY 15 DESCRIPTION Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH CS to RD Setup Time CS to RD Hold Time CONVST LOW RD Pulse Width RD to Valid Data (Bus Access) RD to HI-Z Delay (Bus Relinquish) Time Between Conversion Reads Address Setup Time CONVST HIGH Address Hold Time CONVST to BUSY Propagation Delay CONVST LOW Prior to CLOCK Rising Edge CONVST LOW After CLOCK Rising Edge Data Fall Time Data Rise Time t9 t11 Conversion n Conversion n + 1 t10 A0 t8 CS t1 t2 t7 RD t4 t5 DATA CHA1 t6 CHB1 CHA0 Conversion n – 1 Results CHB0 Conversion n Results FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle. ADS7862 SBAS101B www.ti.com 11 tCKP 125ns CLOCK Cycle 1 Cycle 2 10ns 10ns 5ns A CONVST 5ns B C NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock (Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge. FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion. SECTION A SECTION B 1 16 SECTION C 1 16 1 CLOCK CONVST min 250ns min 250ns A0 = 0 Conversion of Ch0 A0 = 1 Conversion of Ch1 A0 = 0 Conversion of Ch0 A0 Selects Between Ch0 and Ch1 at Output A0 RD 1st RD After CONVST ChA at Output 2nd RD After CONVST ChB at Output CS 4 Output-Register CS Needed Only During Reading Data of Ch0 Still Stored Low Data Level Tri-state of Output High Data Level Output Active DATA ChA0 ChB0 BUSY TIME 0 2µ 3µ ChB0 Conversion of Ch0 Conversion of Ch1 Conversion of Ch0 1µ ChA1 ChB1 ChA0 4µ 5µ Time (seconds) FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality. 12 ADS7862 www.ti.com SBAS101B SECTION A Conversions are initiated by bringing the CONVST pin (pin 18) LOW for a minimum of 5ns (after the 5ns minimum requirement has been met, the CONVST pin can be brought HIGH). The ADS7862 will switch from the sample to the hold mode on the falling edge of the CONVST command. Following the first rising edge of the external clock after a CONVST LOW, the ADS7862 will begin conversion (this first rising edge of the external clock represents the start of clock cycle one; the ADS7862 requires sixteen cycles to complete a conversion). The input channel is also latched in at this point in time. The A0 input (pin 22) must be selected 250ns prior to the CONVST pin going LOW so that the correct address will be selected prior to conversion. The BUSY output will go HIGH immediately following CONVST going LOW. BUSY will stay HIGH through the conversion process and return LOW when the conversion has ended. After CONVST has remained LOW for the minimum time, the ADS7862 will switch from the hold mode to the conversion mode synchronous to the next rising edge of the external clock and conversion ‘n – 2’ will begin. Both RD (pin 21) and CS (pin 20) can be HIGH during and before a conversion. However, they must both be LOW to enable the output bus and read data out. output data should not be read 125ns prior to the falling edge of CONVST and 10ns after the falling edge. Any other combination of CS and RD will tri-state the parallel output. Valid conversion data can be read on pins 5 through 16 (MSB–LSB). Refer to Table I for ideal output codes. SECTION B The CONVST pin is switched from HIGH to LOW a second time to initiate conversion ‘n – 1’. Again, the address must be selected 250ns prior to CONVST going LOW to ensure that the new address is selected for conversion. Both the RD and CS pins are brought LOW in order to enable the parallel output bus with the ‘n – 2’ conversion results of Channel A0. While continuing to hold CS LOW, RD is held LOW for a minimum of 30ns which enables the output bus with the Channel A0 results of conversion ‘n – 2’. The RD pin is toggled from HIGH to LOW a second time in order to enable the output bus with the Channel B0 results of conversion ‘n – 2’. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. This error can change if the external event changes in time with respect to the CLOCK input. SECTION C CONVST is brought LOW for a third time to initiate conversion ‘n’ (Channel 0). While the conversion is in process, the results for both conversions ‘n – 2’ and ‘n – 1’ can be read. The address pin is brought HIGH while CS and RD are brought LOW which enables the output bus with the Channel A1 results of conversion ‘n – 1’. The RD pin is toggled from HIGH to LOW for a second time in Section C and the ‘n – 1’ conversion results for Channel B1 appear at the output bus. The address pin (A0) is then brought LOW and the read process repeats itself with the most recent conversion results for Channel 0 (n – 2) appearing at the output bus. READING DATA The ADS7862 outputs full parallel data in Binary Two’s Complement data output format. The parallel output will be active when CS (pin 20) and RD (pin 21) are both LOW. The In applications where multiple devices are present on the data bus, care should be taken to ensure that the signal applied to RD (pin 21) is toggled only when the target device is properly chip-selected. Toggling the RD pin will advance the internal read pointer regardless of the state of the chip select, causing the output data to appear channel-swapped. If multiple devices share a single read enable from the host processor, the signal may be ORed with an address-decoded chip select to ensure channel data integrity. For more information, refer to Application Report SBAA138, Reading Data from the ADS7862, available for download from the TI website at www.ti.com. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7862 circuitry. This is particularly true if the CLOCK input is approaching the maximum throughput rate. With this in mind, power to the ADS7862 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. On average, the ADS7862 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A bypass capacitor is not necessary when using the internal reference (tie pin 1 directly to pin 2). The AGND and DGND pins should be connected to a clean ground point. In all cases, this should be the ‘analog’ ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. ADS7862 SBAS101B www.ti.com 13 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS7862Y/250 ACTIVE TQFP PBS 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 7862Y ADS7862Y/2K ACTIVE TQFP PBS 32 2000 RoHS & Green NIPDAU Level-3-260C-168 HR 7862Y ADS7862YB/250 ACTIVE TQFP PBS 32 250 RoHS & Green Call TI Level-3-260C-168 HR 7862Y B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of