ADS800E/1K

ADS800 A DS 800 U SBAS035B – FEBRUARY 1995 – REVISED FEBRUARY 2005 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● The ADS800 is a low-power, monolithic 12-bit, 40MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 12-bit quantizer, wideband track-and-hold, reference, and three-state outputs. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals. LOW POWER: 390mW INTERNAL REFERENCE WIDEBAND TRACK-AND-HOLD: 65MHz SINGLE +5V SUPPLY APPLICATIONS The ADS800 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications, test instrumentation, and video applications. ● ● ● ● ● ● IF AND BASEBAND DIGITIZATION DIGITAL COMMUNICATIONS ULTRASOUND IMAGING GAMMA CAMERAS TEST INSTRUMENTATION CCD IMAGING Copiers Scanners Cameras ● VIDEO DIGITIZING This high-performance A/D converter is specified over temperature for AC and DC performance at a 40MHz sampling rate. The ADS800 is available in an SO-28 package. CLK MSBI OE Error Correction Logic 3-State Outputs Timing Circuitry IN Pipeline A/D Converter T/H IN 12-Bit Digital Data +3.25V REFT CM REFB +1.25V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1995-2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input .............................................................. 0V to (+VS + 300mV) Logic Input ................................................................ 0V to (+VS + 300mV) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Top Reference Voltage (REFT) .................................. +3.4V Max External Bottom Reference Voltage (REFB) .............................. +1.1V Min This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may permanently damage the device. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR ADS800U SO-28 DW SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY –40°C to +85°C ADS800U ADS800U Rails, 28 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS800U PARAMETER Resolution Specified Temperature Range Operating Temperature Range ANALOG INPUT Differential Full-Scale Input Range Common-Mode Voltage Analog Input Bandwidth (–3dB) Small-Signal Full-Power Input Impedance DIGITAL INPUT Logic Family Convert Command CONDITIONS f = 12MHz (–1dBFS input) MAX UNITS 0 –40 +70 +85 Bits °C °C Both Inputs, 180° Out-of-Phase +1.25 +3.25 V –20dBFS(1) Input 0dBFS Input +25°C +25°C fS = 2.5MHz +25°C Full ∆ +VS = ±5% ∆ +VS = ±5% +2.25 V 400 65 1.25 || 4 MHz MHz MΩ || pF TTL/HCT Compatible CMOS Falling Edge Start Conversion ±0.4 ±0.6 ±95 0.01 ±2.6 0.02 +25°C Full +25°C 10k ±1.5 ±2.5 0.15 ±3.5 0.15 tH = 13ns(3) tH = 13ns(3) ±0.6 ±0.8 ±0.4 ±0.5 Tested ±1.9 +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full 65 60 58 55 72 66 61 61 % % ppm/°C %FSR/% % %FSR/% 40M Sample/s Convert Cycle ±1.0 LSB LSB LSB LSB LSB LSB 6.5 f = 12MHz No Missing Codes Integral Linearity Error at f = 500kHz Spurious-Free Dynamic Range (SFDR) f = 500kHz (–1dBFS input) TYP TAMBIENT TAMBIENT CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz MIN 12 ACCURACY(2) Gain Error Gain Drift Power-Supply Rejection of Gain Input Offset Error Power-Supply Rejection of Offset TEMP ±1.0 dBFS dBFS dBFS dBFS NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits. 2 ADS800 www.ti.com SBAS035B ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. ADS800U PARAMETER CONDITIONS DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(4) f = 4.4MHz and 4.5MHz (–7dBFS each tone) f = 12MHz (–1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) f = 12MHz (–1dBFS input) OUTPUTS Logic Family Logic Coding Logic Levels NTSC or PAL NTSC or PAL 1.5x Full-Scale Input Logic “LO”, CL = 15pF max Logic “HI”, CL = 15pF max 3-State Enable Time 3-State Disable Time POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Consumption MIN +25°C Full Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) Differential Gain Error Differential Phase Error Aperture Delay Time Aperture Jitter Over-Voltage Recovery Time(5) TEMP MAX UNITS –63 –62 dBc dBc +25°C Full +25°C Full 61 57 61 56 64 63 62 62 dB dB dB dB +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C 59 54 56 51 63 64 58 57 0.5 0.1 2 7 2 dB dB dB dB % degrees ns ps rms ns TTL/HCT Compatible CMOS SOB or BTC 0 0.4 V Logic Selectable Full Full +2.5 Full Operating Operating Operating Operating Operating TYP Full +25°C Full +25°C Full Thermal Resistance, θJA SO-28 +4.75 +VS V 20 2 40 10 ns ns +5.0 78 78 390 390 +5.25 93 97 465 485 V mA mA mW mW 75 °C/W NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits. ADS800 SBAS035B www.ti.com 3 PIN CONFIGURATION PIN DESCRIPTIONS Top View SO GND 1 28 GND B1 2 27 IN B2 3 26 IN B3 4 25 GND B4 5 24 +VS B5 6 23 REFT B6 7 22 CM ADS800 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 GND +VS CLK +VS OE 19 MSBI 20 21 +VS REFB B7 8 21 REFB B8 9 20 +VS B9 10 19 MSBI B10 11 18 OE B11 12 17 +VS B12 13 16 CLK 22 CM GND 14 15 +VS 23 REFT 24 25 26 27 28 +VS GND IN IN GND DESCRIPTION Ground Bit 1, Most Significant Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12, Least Significant Bit Ground +5V Power Supply Convert Clock Input, 50% Duty Cycle +5V Power Supply HI: High Impedance State. LO or Floating: Normal Operation. Internal pull-down resistors. Most Significant Bit Inversion, HI: MSB inverted for complementary output. LO or Floating: Straight output. Internal pull-down resistors. +5V Power Supply Bottom Reference Bypass. For external bypassing of internal +1.25V reference. Common-Mode Voltage. It is derived by (REFT + REFB)/2. Top Reference Bypass. For external bypassing of internal +3.25V reference. +5V Power Supply Ground Input Complementary Input Ground TIMING DIAGRAM tCONV tL Convert Clock tD tH DATA LATENCY (6.5 Clock Cycles) Hold Hold Hold Hold Hold Hold Track “N + 1” Track “N + 2” Track “N + 3” Track “N + 4” Track “N + 5” Track “N + 6” Track (1) Track Internal Track-and-Hold Hold “N” t2 Output Data Data Valid N–8 Data Valid N–7 Data Valid N–6 N–5 N–4 N–3 N–2 N–1 N t1 Data Invalid SYMBOL tCONV tL tH tD t1 t2 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 25 12 12(2) TYP MAX UNITS 100µs ns ns ns ns ns ns 12.5 12.5 2 3.9 12.5 NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates. (2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns and fIN < 2MHz. 4 ADS800 www.ti.com SBAS035B TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 fIN = 500kHz –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) 0 –60 –80 –100 fIN = 1MHz –60 –80 –100 –120 –120 0 5 10 15 20 0 5 Frequency (MHz) 10 15 SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 12MHz –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) fIN = 5MHz –60 –80 –100 –60 –80 –100 –120 –120 0 5 10 15 20 0 5 Frequency (MHz) 15 20 2-TONE INTERMODULATION 0 fIN = 1MHz fS = 10MHz –20 10 Frequency (MHz) SPECTRAL PERFORMANCE 0 f1 = 12.5MHz f2 = 12.0MHz –20 –40 Amplitude (dB) Amplitude (dB) 20 Frequency (MHz) –60 –80 –100 –40 –60 –80 –100 –120 –120 0 1 2 3 4 5 0 Frequency (MHz) 10 15 20 Frequency (MHz) ADS800 SBAS035B 5 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 2.0 2.0 fIN = 12MHz fIN = 500kHz 1.0 DLE (LSB) DLE (LSB) 1.0 0 –1.0 0 –1.0 –2.0 –2.0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Code Code SWEPT POWER SFDR DYNAMIC PERFORMANCE vs INPUT FREQUENCY 100 80 fIN = 12MHz 75 80 70 SFDR (dBFS) SFDR, SNR (dB) SFDR 65 60 60 40 SNR 20 55 50 0 0.1 1 10 –50 100 –40 –30 –20 SWEPT POWER SNR 10 4.0 fIN = 500kHz fIN = 12MHz 60 2.0 ILE (LSB) SNR (dB) 0 INTEGRAL LINEARITY ERROR 80 40 20 0 –2.0 0 –50 –40 –30 –20 –10 0 –4.0 10 0 Input Amplitude (dBm) 6 –10 Input Amplitude (dBm) Frequency (MHz) 1024 2048 3072 4096 Code ADS800 www.ti.com SBAS035B TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. DYNAMIC PERFORMANCE vs DIFFERENTIAL FULL-SCALE INPUT RANGE DYNAMIC PERFORMANCE vs SINGLE-ENDED FULL-SCALE INPUT RANGE 75 65 fIN = 12MHz SFDR (fIN = 500kHz) SNR 60 Dynamic Range (dB) Dynamic Range (dB) 70 55 SFDR 50 SFDR (fIN = 12MHz) 65 SNR (fIN = 500kHz) 60 SNR (fIN = 12MHz) 55 NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V. NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V. 50 45 1 2 3 4 Single-Ended Full-Scale Range (Vp-p) 2 3 4 Differential Full-Scale Input Range (Vp-p) 5 SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs TEMPERATURE SIGNAL-TO-NOISE RATIO vs TEMPERATURE 80 90 70 fIN = 500kHz fIN = 500kHz SNR (dB) SFDR (dBFS) 80 70 60 fIN = 12MHz 50 60 fIN = 12MHz 40 50 –25 0 25 50 –25 75 0 25 50 75 Temperature (°C) Temperature (°C) SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 70 85 fIN = 500kHz 80 IQ (mA) SINAD (dB) 65 60 75 fIN = 12MHz 55 50 70 –25 0 25 50 75 –25 ADS800 SBAS035B 0 25 50 75 Temperature (°C) Temperature (°C) www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. POWER DISSIPATION vs TEMPERATURE GAIN ERROR vs TEMPERATURE 0.75 425 Gain (%FSR) Power (mW) 0.25 400 375 –0.25 –0.75 –1.25 350 –25 0 25 50 75 –25 0 Temperature (°C) 50 75 TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH OFFSET ERROR vs TEMPERATURE 1 Track-Mode Input Response (dB) –2.25 Offset (%FSR) 25 Temperature (°C) –2.5 0 –1 –2 –3 –4 –5 –2.75 –25 0 25 50 75 10k 100k Ambient Temperature (°C) 1M 10M 100M 1G Frequency (Hz) OUTPUT NOISE HISTOGRAM (NO SIGNAL) 800k Counts 600k 400k 200k 0.0 N–2 N–1 N N+1 N+2 Code 8 ADS800 www.ti.com SBAS035B THEORY OF OPERATION Op Amp Bias The ADS800 is a high-speed, sampling A/D converter with pipelining. It uses a fully differential architecture and digital error correction to ensure 12-bit resolution. The differential track-and-hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping 2-phase signal, φ1 and φ2. At the sampling time, the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time, the charge redistributes between CI and CH, completing one track-and-hold cycle. The differential output is a held DC representation of the analog input at the sample time. The track-and-hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. φ1 IN IN IN φ2 φ1 φ2 OUT φ1 OUT φ1 CI φ2 CH φ1 φ1 Input Clock (50%) Op Amp Bias VCM Internal Non-Overlapping Clock φ1 φ2 φ1 FIGURE 1. Input Track-and-Hold Configuration with Timing Signals. Digital Delay Input T/H 2-Bit Flash STAGE 1 φ1 CH CI The pipelined quantizer architecture has 11 stages with each stage containing a 2-bit quantizer and a 2-bit Digital-toAnalog Converter (DAC), as shown in Figure 2. Each 2-bit quantizer stage converts on the edge of the sub-clock, which is twice the frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time- IN VCM 2-Bit DAC + Σ – x2 B1 (MSB) Digital Delay B2 STAGE 2 B3 2-Bit DAC Digital Error Correction 2-Bit Flash + Σ – x2 B4 B5 B6 B7 B8 B9 B10 Digital Delay B11 B12 (LSB) 2-Bit Flash STAGE 10 2-Bit DAC + Σ – x2 STAGE 11 2-Bit Flash Digital Delay FIGURE 2. Pipeline A/D Converter Architecture. ADS800 SBAS035B www.ti.com 9 align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique gives the ADS800 excellent differential linearity and ensures no missing codes at the 12-bit level. Since there are two pipeline stages per external clock cycle, there is a 6.5 clock cycle data latency from the start convert signal to the valid output data. The output data is available in Straight Offset Binary (SOB) or Binary Two’s Complement (BTC) format. • For most applications, the clock duty should be set to 50%. However, for applications requiring no missing codes, a slight skew in the duty cycle will improve DNL performance for conversion rates > 35MHz and input frequencies < 2MHz (see Timing Diagram) in the SO package. For the best performance in the SSOP package, the clock should be skewed under all input frequencies with conversion rates > 35MHz. A possible method for skewing the 50% duty cycle source is shown in Figure 4. ADS800 +3.25V 23 REFT 0.1µF 2kΩ +2.25V 22 RV = 217Ω, typical 0.1µF CLKIN 21 CLKOUT IC2 FIGURE 4. Clock Skew Circuit. DIGITAL OUTPUT DATA The 12-bit output data is provided at CMOS logic levels. The standard output coding is Straight Offset Binary (SOB) where a full-scale input signal corresponds to all “1’s” at the output, as shown in Table 1. This condition is met with pin 19 “LO” or Floating due to an internal pull-down resistor. By applying a logic “HI” voltage to this pin, a Binary Two’s Complement (BTC) output will be provided where the most significant bit is inverted. The digital outputs of the ADS800 can be set to a high-impedance state by driving OE (pin 18) with a logic “HI”. Normal operation is achieved with pin 18 “LO” or Floating due to internal pull-down resistors. This function is provided for testability purposes and is not meant to drive digital buses directly or be dynamically changed during the conversion process. OUTPUT CODE 2kΩ REFB 0.1µF 0.1µF IC1 To Internal Comparators CM IC1, IC2 = ACT04 RV 2kΩ THE ANALOG INPUT AND INTERNAL REFERENCE The analog input of the ADS800 can be configured in various ways and driven with different circuits, depending on the nature of the signal and the level of performance desired. The ADS800 has an internal reference that sets the full-scale input range of the A/D converter. The differential input range has each input centered around the common-mode of +2.25V, with each of the two inputs having a full-scale range of +1.25V to +3.25V. Since each input is 2Vp-p and 180° outof-phase with the other, a 4V differential input signal to the quantizer results. As shown in Figure 3, the positive full-scale reference (REFT) and the negative full-scale (REFB) are brought out for external bypassing. In addition, the commonmode voltage (CM) may be used as a reference to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this reference node. For more information regarding external references, singleended input, and ADS800 drive circuits, refer to the applications section. VDD VDD DIFFERENTIAL INPUT(1) +1.25V FIGURE 3. Internal Reference Structure. CLOCK REQUIREMENTS The CLK pin accepts a CMOS level clock input. Both the rising and falling edges of the externally applied clock control the various interstage conversions in the pipeline. Therefore, the clock signal’s jitter, rise-and-fall times, and duty cycle can affect conversion performance. • Low clock jitter is critical to SNR performance in frequency-domain signal environments. +FS (IN = +3.25V, IN = +1.25V) +FS – 1LSB +FS – 2LSB +3/4 Full-Scale +1/2 Full-Scale +1/4 Full-Scale +1LSB Bipolar Zero (IN = IN = +2.25V) –1LSB –1/4 Full-Scale –1/2 Full-Scale –3/4 Full-Scale –FS + 1LSB –FS (IN = +1.25V, IN = +3.25V) SOB PIN 19 FLOATING or LO BTC PIN 19 HI 111111111111 111111111111 111111111110 111000000000 110000000000 101000000000 100000000001 100000000000 011111111111 011000000000 010000000000 001000000000 000000000001 000000000000 011111111111 011111111111 011111111110 011000000000 010000000000 001000000000 000000000001 000000000000 111111111111 111000000000 110000000000 101000000000 100000000001 100000000000 NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V. TABLE I. Coding Table for the ADS800. • Clock rise-and-fall times should be as short as possible (< 2ns for best performance). 10 ADS800 www.ti.com SBAS035B APPLICATIONS product performance. The input capacitors, CIN, and the input resistors, RIN, create a high-pass filter with the lower corner frequency at fC = 1/(2pRINCIN). The corner frequency can be reduced by either increasing the value of RIN or CIN. If the circuit operates with a 50Ω or 75Ω impedance level, the resistors are fixed and only the value of the capacitor can be increased. Usually, AC-coupling capacitors are electrolytic or tantalum capacitors with values of 1µF or higher. It should be noted that these large capacitors become inductive with increased input frequency, which could lead to signal amplitude errors or oscillation. To maintain a low AC-coupling impedance throughout the signal band, a small value (e.g. 1µF) ceramic capacitor could be added in parallel with the polarized capacitor. DRIVING THE ADS800 The ADS800 has a differential input with a common-mode of +2.25V. For AC-coupled applications, the simplest way to create this differential input is to drive the primary winding of a transformer with a single-ended input. A differential output is created on the secondary if the center tap is tied to the common-mode voltage of +2.25V, as per Figure 5. This transformer-coupled input arrangement provides good highfrequency AC performance. It is important to select a transformer that gives low distortion and does not exhibit core saturation at full-scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the Common-Mode (CM) output in this instance. In general, it is advisable to keep the current draw from the CM output pin below 0.5µA to avoid nonlinearity in the internal reference ladder. A FET input operational amplifier such as the OPA130 can provide a buffered reference for driving external circuitry. The analog IN and IN inputs should be bypassed with 22pF capacitors to minimize track-and-hold glitches and to improve high input frequency performance. Capacitors CSH1 and CSH2 are used to minimize current glitches resulting from the switching in the input track-andhold stage and to improve signal-to-noise performance. These capacitors can also be used to establish a low-pass filter and effectively reduce the noise bandwidth. In order to create a real pole, resistors RSER1 and RSER2 were added in series with each input. The cutoff frequency of the filter is determined by fC = 1/(2pRSER • (CSH + CADC)) where RSER is the resistor in series with the input, CSH is the external capacitor from the input to ground, and CADC is the internal input capacitance of the A/D converter (typically 4pF). Figure 6 illustrates another possible low-cost interface circuit which utilizes resistors and capacitors in place of a transformer. Depending on the signal bandwidth, the component values should be carefully selected in order to maintain the Resistors R1 and R2 are used to derive the necessary common-mode voltage from the buffered top and bottom references. The total load of the resistor string should be selected so that the current does not exceed 1mA. Although the circuit in Figure 6 uses two resistors of equal value so that the common-mode voltage is centered between the top and bottom reference (+2.25V), it is not necessary to do so. In all cases the center point, VCM, should be bypassed to ground in order to provide a low-impedance AC ground. 22 CM 0.1µF 26 IN AC Input Signal 22pF Mini-Circuits TT1-6-KK81 or equivalent ADS800 27 IN If the signal needs to be DC coupled to the input of the ADS800, an operational amplifier input circuit is required. In the differential input mode, any single-ended signal must be modified to create a differential signal. This can be accomplished by 22pF FIGURE 5. AC-Coupled Single-Ended to Differential Drive Circuit Using a Transformer. C1 0.1µF CIN 0.1µF RSER1(1) 49.9Ω R1 (6kΩ) +3.25V Top Reference IN RIN1 25Ω RIN2 25Ω CIN 0.1µF CSH1 22pF R3 1kΩ C2 0.1µF RSER2(1) 49.9Ω ADS8xx VCM R2 (6kΩ) IN CSH2 22pF +1.25V Bottom Reference C3 0.1µF NOTE: (1) Indicates optional component. FIGURE 6. AC-Coupled Differential Input Circuit. ADS800 SBAS035B www.ti.com 11 using two operational amplifiers, one in the noninverting mode for the input and the other amplifier in the inverting mode for the complementary input. The low distortion circuit in Figure 7 will provide the necessary input shifting required for signals centered around ground. It also employs a diode for output level shifting to ensure a low distortion +3.25V output swing. Other amplifiers can be used in place of the OPA842s if the lowest distortion is not necessary. If output level shifting circuits are not used, care must be taken to select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier. age, as shown in Figure 8. This configuration will result in increased even-order harmonics, especially at higher input frequencies. However, this tradeoff may be quite acceptable for time-domain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case. EXTERNAL REFERENCES AND ADJUSTMENT OF FULL-SCALE RANGE The internal reference buffers are limited to approximately 1mA of output current. As a result, these internal +1.25V and +3.25V references may be overridden by external references that have at least 18mA (at room temperature) of output drive capability. In this instance, the common-mode voltage will be The ADS800 can also be configured with a single-ended input full-scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference volt- +5V 604Ω +5V 301Ω BAS16(1) Optional High Impedance Input Amplifier 301Ω 301Ω 27 IN OPA842 2.49kΩ 0.1µF +5V(2) 22pF 0.1µF –5V 604Ω DC-Coupled Input Signal +5V OPA842 604Ω 49.9Ω OPA130 +5V –5V 24.9Ω ADS800 2.49kΩ +2.25V 22 CM +5V 301Ω BAS16(1) Input Level Shift Buffer 301Ω 26 IN OPA842 22pF 0.1µF –5V 604Ω NOTES: (1) A Philips BAS16 diode or equivalent may be used. (2) Supply bypassing not shown. 301Ω FIGURE 7. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit. 22 CM 0.1µF ADS800 Single-Ended Input Signal 26 IN 27 IN 22pF Full Scale = +0.25V to +4.25V with internal references. FIGURE 8. Single-Ended Input Connection. 12 ADS800 www.ti.com SBAS035B The circuit in Figure 10 works completely on a single +5V supply. As a reference element, it uses the micro-power reference REF1004-2.5, which is set to a quiescent current of 0.1mA. Amplifier A2 is configured as a follower to buffer the +1.25V generated from the resistor divider. To provide the necessary current drive, a pull-down resistor, RP, is added. set halfway between the two references. This feature can be used to adjust the gain error, improve gain drift, or to change the full-scale input range of the ADS800. Changing the fullscale range to a lower value has the benefit of easing the swing requirements of external input drive amplifiers. The external references can vary as long as the value of the external top reference (REFTEXT) is less than or equal to +3.4V, the value of the external bottom reference (REFBEXT) is greater than or equal to +1.1V, and the difference between the external references are greater than or equal to 1.5V. Amplifier A1 is configured as an adjustable gain stage, with a range of approximately 1 to 1.32. The pull-up resistor again relieves the op amp from providing the full current drive. The value of the pull-up/down resistors is not critical and can be varied to optimize power consumption. The need for pull-up, pull-down resistors depends only on the drive capability of the selected drive amplifiers and thus can be omitted. For the differential configuration, the full-scale input range will be set to the external reference values that are selected. For the single-ended mode, the input range is 2 • (REFTEXT – REFBEXT), with the common-mode being centered at (REFTEXT + REFBEXT)/2. Refer to the typical characteristics for “Expected Performance vs Full-Scale Input Range”. –541 +5V 0.1µF +VS CLK Ext Clk 0.1µF R1 50Ω +VS OE MSBI 0.1µF +VS REFB CM REFT 0.1µF 0.1µF 0.1µF 0.1µF AC Input Signal +VS GND IN R2 50Ω IN 22pF Mini-Circuits TT1-6-KK81 or equivalent (1) 22pF GND 15 14 16 13 17 12 GND 11 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 LSB 1 19 18 11 19 10 20 9 21 8 23 24 25 26 27 28 7 6 5 4 3 2 1 G+ –541 ADS800 22 Dir MSB 11 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 GND 1 19 Dir G+ NOTE: (1) All capacitors should be located as close to the pins as the manufacturing process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended. FIGURE 9. ADS800 Interface Schematic with AC-Coupling and External Buffers. ADS800 SBAS035B www.ti.com 13 +5V RP 220Ω A1 1/2 OPA2234 +5V Top Reference +2.5V to +3.25V 2kΩ 10kΩ 6.2kΩ 10kΩ REF1004 +2.5V 10kΩ(1) A2 1/2 OPA2234 0.1µF +1.25V 10kΩ Bottom Reference RP 220Ω 10kΩ(1) NOTE: (1) Use parts alternatively for adjustment capability. FIGURE 10. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp. PC BOARD LAYOUT AND BYPASSING A well-designed, clean PC board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high-frequency circuits. Multilayer PC boards are recommended for best performance but if carefully designed, a two-sided PC board with large, heavy ground planes can give excellent results. It is recommended that the analog and digital ground pins of the ADS800 be connected directly to the analog ground plane. In our experience, this gives the most consistent results. The A/D converter power-supply commons should be tied together at the analog ground plane. Power supplies should be bypassed with 0.1µF ceramic capacitors as close to the pin as possible. DYNAMIC PERFORMANCE DEFINITIONS 1. The ADS800 is a high performance converter and careful attention to test techniques is necessary to achieve accurate results. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using data windowing functions. A low jitter signal generator such as the HP8644A for the test signal, phase-locked with a low jitter Signal-to-Noise-and-Distortion Ratio (SINAD): 10 log 2. Sinewave Signal Power Noise + Harmonic Power (first 15 harmonics) Signal-to-Noise Ratio (SNR): 10 log 3. DYNAMIC PERFORMANCE TESTING 14 HP8022A pulse generator for the A/D converter clock, gives excellent results. Low-pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low distortion of the ADS800. Using a signal amplitude slightly lower than fullscale will allow a small amount of “headroom” so that noise or DC offset voltage will not over-range the A/D converter and cause clipping on signal peaks. Sinewave Signal Power Noise Power Intermodulation Distortion (IMD): 10 log Highest IMD Pr oduct Power ( to 5th − order ) Sinewave Signal Power IMD is referenced to the larger of the test signals, f1 or f2. Five “bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is not included in these calculations as it is of little importance in dynamic signal processing applications. ADS800 www.ti.com SBAS035B PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS800U LIFEBUY SOIC DW 28 20 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS800U ADS800U/1K LIFEBUY SOIC DW 28 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS800U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of