ADS8322Y/2KG4

ADS8322 www.ti.com SBAS215A – JULY 2001 – REVISED JANUARY 2010 16-Bit, 500kHz, MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8322 FEATURES 1 • • • • • • 2 DESCRIPTION HIGH-SPEED PARALLEL INTERFACE 500kHz SAMPLING RATE LOW POWER: 85mW at 500kHz INTERNAL 2.5V REFERENCE UNIPOLAR INPUT RANGE TQFP-32 PACKAGE The ADS8322 is a 16-bit, 500kHz analog-to-digital (A/D) converter with an internal 2.5V reference. The device includes a 16-bit capacitor-based successive approximation register (SAR) A/D converter with inherent sample-and-hold. The ADS8322 offers a full 16-bit interface, or an 8-bit option where data are read using two read cycles and eight pins. The ADS8322 is available in a TQFP-32 package and is ensured over the industrial –40°C to +85°C temperature range. APPLICATIONS • • • • CT SCANNERS HIGH-SPEED DATA ACQUISITION TEST AND INSTRUMENTATION MEDICAL EQUIPMENT white space here white space here white space here white space here white space here BYTE SAR ADS8322 Output Latches and 3-State Drivers Parallel Data Output +IN CDAC -IN S/H Amp CLOCK Comparator REFIN REFOUT Internal +2.5V Ref Conversion and Control Logic CONVST CS RD BUSY 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2010, Texas Instruments Incorporated ADS8322 SBAS215A – JULY 2001 – REVISED JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ADS8322Y ADS8322YB (1) ±8 ±6 NO MISSING CODES ERROR (LSB) 14 15 PACKAGELEAD TQFP-32 TQFP-32 PACKAGE DESIGNATOR PBS PBS SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +85°C –40°C to +85°C TRANSPORT MEDIA, QUANTITY Tape and reel, 250 Tape and reel, 2000 Tape and reel, 250 Tape and reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS8322 UNIT VA + 0.1 V –IN to GND +0.5 V VA to GND –0.3 to +7 V Digital input voltage to GND –0.3 to (VA + 0.3) V VOUT to GND +IN to GND –0.3 to (VA + 0.3) V Operating temperature range –40 to +105 °C Storage temperature range –65 to +150 °C +150 °C Junction temperature (TJ max) Power dissipation (TJ max – TA)/θJA θJA thermal impedance (1) 2 240 °C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 ADS8322 www.ti.com SBAS215A – JULY 2001 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS: +VA = +5V At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified. ADS8322YB (1) ADS8322Y PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT RESOLUTION Resolution 16 16 Bits ANALOG INPUTS Full-scale input span (2) Absolute input range +IN – (–IN) 0 +2VREF 0 +2VREF V +IN –0.1 VA + 0.1 –0.1 VA + 0.1 V –IN –0.1 +0.5 –0.1 +0.5 V Capacitance 25 25 pF Leakage current ±1 ±1 nA SYSTEM PERFORMANCE No missing codes 14 Integral linearity error 15 ±4 ±8 Bits ±3 ±6 LSBs (3) Offset error ±1.0 ±2 ±0.5 ±1.0 mV Gain error (4) ±0.25 ±0.50 ±0.22 ±0.25 %FSR Common-mode rejection ratio At dc Noise Power-supply rejection ratio At FFFFh output code 70 70 dB 60 60 μVRMS ±3 ±3 LSBs SAMPLING DYNAMICS Conversion time 1.6 Acquisition time 350 1.6 μs 500 kHz 350 Throughput rate ns 500 Aperture delay 50 50 Aperture jitter 20 20 ns ps Small-signal bandwidth 30 30 MHz Step response 100 100 ns DYNAMIC CHARACTERISTICS Total harmonic distortion (5) VIN = 5VPP at 100kHz –90 –93 dB SINAD VIN = 5VPP at 100kHz 81 83 dB Spurious free dynamic range VIN = 5VPP at 100kHz 94 96 dB REFERENCE OUTPUT Voltage Source current Drift Line regulation IOUT = 0 2.475 2.50 Static load 2.525 2.48 2.50 10 2.52 V 10 μA IOUT = 0 20 20 ppm/°C 4.75V ≤ VCC ≤ 5.25V 0.6 0.6 mV REFERENCE INPUT Range Resistance (6) (1) (2) (3) (4) (5) (6) 1.5 To internal reference voltage 2.55 10 1.5 2.55 10 V kΩ Shaded cells indicate different specifications from ADS8322Y. Ideal input span; does not include gain or offset error. LSB means least significant bit, with VREF equal to +2.5V; 1LSB = 76μV. Measured relative to an ideal, full-scale input [+In – (–In)] of 4.9999V. Thus, gain error includes the error of the internal voltage reference. Calculated on the first nine harmonics of the input frequency. Can vary ±30%. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 3 ADS8322 SBAS215A – JULY 2001 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: +VA = +5V (continued) At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified. ADS8322YB (1) ADS8322Y PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS CMOS Logic levels: VIH IIH ≤ +5μA 3.0 +VA 3.0 +VA V VIL IIL ≤ +5μA –0.3 0.8 –0.3 0.8 V VOH IOH = 2 TTL Loads 4.0 VOL IOH = 2 TTL Loads 4.0 V 0.4 Data format Straight binary 0.4 V V Straight binary POWER-SUPPLY REQUIREMENTS Power-supply voltage +VA 4.75 5 5.25 4.75 5 5.25 +VD 4.75 5 5.25 4.75 5 5.25 V Supply current fSAMPLE = 500kHz 17 25 17 25 mA Power dissipation fSAMPLE = 500kHz 85 125 85 125 mW +85 °C TEMPERATURE RANGE Specified temperature range –40 +85 –40 DEVICE INFORMATION 4 REFOUT REFIN NC NC +VA AGND +IN -IN PBS PACKAGE TQFP-32 (TOP VIEW) 32 31 30 29 28 27 26 25 DB13 3 22 RD DB12 4 21 CONVST DB11 5 20 CLOCK DB10 6 19 DGND DB9 7 18 +VD DB8 8 17 BUSY 9 10 11 12 13 14 15 16 DB0 BYTE DB1 23 DB2 2 DB3 DB14 DB4 CS DB5 24 DB6 1 DB7 DB15 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 ADS8322 www.ti.com SBAS215A – JULY 2001 – REVISED JANUARY 2010 PIN ASSIGNMENTS TERMINAL NO NAME 1 DB15 Data Bit 15 (MSB) DESCRIPTION 2 DB14 Data Bit 14 3 DB13 Data Bit 13 4 DB12 Data Bit 12 5 DB11 Data Bit 11 6 DB10 Data Bit 10 7 DB9 Data Bit 9 8 DB8 Data Bit 8 9 DB7 Data Bit 7 10 DB6 Data Bit 6 11 DB5 Data Bit 5 12 DB4 Data Bit 4 13 DB3 Data Bit 3 14 DB2 Data Bit 2 15 DB1 Data Bit 1 16 DB0 Data Bit 0 (LSB) 17 BUSY 18 VD+ 19 DGND Digital Ground 20 CLOCK An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. 21 CONVST High when a conversion is in progress. Digital Power Supply, +5VDC. Convert Start 22 RD 23 BYTE Synchronization pulse for the parallel output. 24 CS Chip Select 25 –IN Inverting Input Channel 26 +IN Noninverting Input Channel 27 AGND 28 +VA Analog Power Supply, +5VDC. 29 NC No connection 30 NC No connection 31 REFIN 32 REFOUT Selects eight most significant bits (low) or eight least significant bits (high). Data valid on pins 9-16. Analog Ground Reference Input. When using the internal 2.5V reference, tie this pin directly to REFOUT. Reference Output. A 0.1μF capacitor should be connected to this pin when the internal reference is used. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 5 ADS8322 SBAS215A – JULY 2001 – REVISED JANUARY 2010 www.ti.com TIMING INFORMATION t1 t3 t2 CLOCK 2 1 Acquisition 3 4 5 17 18 19 Conversion Acquisition tCONV tACQ 20 1 2 3 4 17 18 19 20 t5 t4 CONVST t6 t9 t10 BUSY t7 t11 BYTE t8 t12 CS t13 t18 t14 t15 RD t16 t17 t19 DB15-D8 Bits 15-8 Bits 15-8 FF DB7-D0 Bits 7-0 Bits 7-0 Bits 15-8 TIMING CHARACTERISTICS (1) (2) All specifications typical at –40°C to +85°C, +VD = +5V. ADS8322 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.6 μs tCONV Conversion Time tAQC Acquisition Time 350 ns t1 CLOCK Period 100 ns t2 CLOCK High Time 40 ns t3 CLOCK Low Time 40 ns t4 CONVST Low to Clock High 10 ns t5 CLOCK High to CONVST High 5 ns t6 CONVST Low Time 20 t7 CONVST Low to BUSY High t8 CS Low to CONVST Low 0 ns t9 CONVST High 20 ns t10 CLOCK Low to CONVST Low 0 t11 CLOCK High to BUSY Low t12 CS High 0 ns t13 CS Low to RD Low 0 ns t14 RD High to CS High 0 ns t15 RD Low Time 50 ns t16 RD Low to Data Valid 40 ns t17 Data Hold from RD High 5 ns t18 BYTE Change to RD Low (3) 0 ns t19 RD High Time 20 ns (1) (2) (3) 6 ns 25 ns ns 25 ns All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) /2. See timing diagram, above. BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BUSY is 1, bits 15 through 8 appear on DB7-DB0. RD may remain low between changes in BYTE. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 ADS8322 www.ti.com SBAS215A – JULY 2001 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 100.1kHz, –0.2dB) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 0 90 SNR, SINAD (dB) Amplitude (dB) -30 -60 -90 85 SNR 80 SINAD -120 -150 75 0 20 40 60 80 100 120 140 160 Frequency (Hz) 1 180 200 10 Figure 1. 0.30 95 -95 0.20 SFDR -90 THD Deltas (LSB) -100 THD (dB) SFDR IL+ vs TEMPERATURE 100 0.10 85 -85 80 -80 -0.10 -75 -0.20 75 1 10 100 250 0 -40 -20 0 Frequency (kHz) 20 40 60 80 100 Temperature (°C) Figure 3. Figure 4. IL– vs TEMPERATURE DL+ vs TEMPERATURE 1.0 0.2 0.5 Deltas (LSB) 0 Deltas (LSB) 250 Figure 2. SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTIONvs INPUT FREQUENCY 90 100 Frequency (kHz) -0.2 -0.4 0 -0.5 -1.0 -1.5 -0.6 – -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 7 ADS8322 SBAS215A – JULY 2001 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, +VA = +5V, VREF = +2.5V, fSAMPLE = 500kHz, and fCLK = 20 • fSAMPLE, unless otherwise specified. DL– vs TEMPERATURE OFFSET ERROR vs TEMPERATURE 0.05 2.5 2.0 0 Deltas (LSB) Deltas (LSB) 1.5 -0.05 -0.10 -0.15 1.0 0.5 0 -0.5 -0.20 -1.0 -0.25 -1.5 -40 0 -20 20 40 60 80 100 -40 -20 0 20 40 60 80 100 60 80 100 Temperature (°C) Temperature (°C) Figure 7. Figure 8. GAIN ERROR vs TEMPERATURE VREF vs TEMPERATURE 8 2.0 1.0 6 0 Deltas (mV) Deltas (LSB) -1.0 4 2 -2.0 -3.0 -4.0 -5.0 0 -6.0 -7.0 -2 -40 -20 0 20 40 60 80 -8.0 -40 100 Temperature (°C) IQ vs TEMPERATURE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE INL (LSB) 0.4 0 DNL (LSB) Deltas (mA) 40 Figure 10. -0.4 0 20 40 60 80 100 4 3 2 1 0 -1 -2 -3 -4 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Temperature (°C) Decimal Code Figure 11. 8 20 Figure 9. 0.8 -20 0 Temperature (°C) 1.2 -0.8 -40 -20 Figure 12. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 ADS8322 www.ti.com SBAS215A – JULY 2001 – REVISED JANUARY 2010 THEORY OF OPERATION The ADS8322 is a high-speed successive approximation register (SAR) A/D converter with an internal 2.5V bandgap reference. The architecture is based on capacitive redistribution, which inherently includes a sample-and-hold function. The basic operating circuit for the ADS8322 is shown in Figure 13. times are at least 40ns and the clock period is at least 100ns. The minimum clock frequency is governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8322. The analog input is provided to two input pins, +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The ADS8322 requires an external clock to run the conversion process. The clock can be run continuously or it can be gated to conserve power between conversions. This clock can vary between 25kHz (1.25kHz throughput) and 10MHz (500kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW +5V Analog Supply 10mF + 0.1mF + 0.1mF Analog Input 32 31 30 29 28 27 26 25 REFOUT REFIN NC NC +VA AGND +IN -IN - CS 24 1 DB15 2 DB14 BYTE 23 3 DB13 RD 22 4 DB12 CONVST 21 Chip Select Read Input Conversion Start ADS8322 +VD 18 8 DB8 BUSY 17 DB0 DB9 DB1 7 DB2 DGND 19 DB3 DB10 DB4 6 DB5 CLOCK 20 DB6 DB11 DB7 5 9 10 11 12 13 14 15 16 Clock Input Busy Output Figure 13. Typical Circuit Configuration Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 9 ADS8322 SBAS215A – JULY 2001 – REVISED JANUARY 2010 www.ti.com REFERENCE Under normal operation, the REFOUT pin should be directly connected to the REFIN pin to provide an internal +2.5V reference to the ADS8322. The ADS8322 can operate, however, with an external reference in the range of 1.5V to 2.6V for a corresponding full-scale range of 3.0V to 5.2V. The internal reference of the ADS8322 is double-buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to the REFOUT pin (the internal reference can typically source and sink 10μA of current). If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the CDAC capacitors during conversion. ANALOG INPUT When the converter enters the Hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.1V and 0.5V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.1V to +VA + 0.1V. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8322 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to a 16-bit settling level within the acquisition time (400ns) of the device. When the converter goes into Hold mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –IN input should not drop below GND – 100mV or exceed GND + 0.5V. The +IN input should always remain within the range of GND – 100mV to VA + 100mV. Outside of these ranges, the converter linearity may not meet specifications. To minimize noise, low-bandwidth input signals with low-pass filters should be used. DIGITAL INTERFACE The ADS8322 uses an external clock (CLOCK) which controls the conversion rate of the CDAC. With a 10MHz external clock, the A/D converter sampling rate is 500kHz, which corresponds to a 2μs maximum throughput time. Conversions are initiated by bringing the CONVST pin low for a minimum of 20ns (after the 20ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8322 switches from Sample-to-Hold mode on the falling edge of the CONVST command. Following the first rising edge of the external clock after a CONVST low, the ADS8322 begins conversion (this first rising edge of the external clock represents the start of clock cycle one; the ADS8322 requires 16 rising clock edges to complete a conversion). The BUSY output goes high immediately following CONVST going low. BUSY stays high through the conversion process and returns low when the conversion has ended. Both RD and CS can be high during and before a conversion (although CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. READING DATA The ADS8322 outputs full parallel data in Straight Binary format, as shown in Table 1. The parallel output is active when CS and RD are both LOW. The output data should not be read 125ns before the falling edge of CONVST and 10ns after the falling edge. Any other combination of CS and RD will 3-state the parallel output. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE DIGITAL OUTPUT STRAIGHT BINARY Full-Scale Range 2 • VREF Least Significant Bit (LSB) 2• VREF/65535 BINARY CODE +Full Scale 2VREF – 1 LSB 1111 1111 1111 1111 FFFF Midscale VREF 1000 0000 0000 0000 8000 Midscale – LSB VREF – 1 LSB 0111 1111 1111 1111 7FFF Zero 0 0000 0000 0000 0000 0000 HEX CODE TIMING AND CONTROL See the timing diagram and the Timing Characteristics section for detailed information on timing signals and the respective requirements for each. 10 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 ADS8322 www.ti.com SBAS215A – JULY 2001 – REVISED JANUARY 2010 BYTE AVERAGING The output data appear as a full 16-bit word on DB15- DB0 (MSB-LSB), if BYTE is low. The result may also be read on an 8-bit bus by using only DB7-DB0. In this case two reads are necessary. The first read proceeds as before, leaving BYTE low and reading the eight least significant bits on DB7-DB0, then bringing BYTE high. When BYTE is high, the upper eight bits (D15-D8) appear on DB7-DB0. The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results reduces the transition noise by 1/2 to ±0.25 LSBs. Averaging should only be used for input signals with frequencies near dc. NOISE Figure 14 shows the transition noise of the ADS8322. A low-level dc input was applied to the analog input pins and the converter was put through 8,192 conversions. The digital output of the A/D converter varies in output code due to the internal noise of the ADS8322. This characteristic is true for all 16-bit SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped, with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions respectively represent the 68.3%, 95.5%, and 99.7% of all codes. The transition noise can be calculated by dividing the number of codes measured by six; this yields the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1,000 conversions. The ADS8322, with five output codes for the ±3σ distribution, yields a < ±0.8LSB transition noise at 5V operation. Remember that to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50μV. 5052 818 0014 300 0015 0016 0017 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8322 circuitry. This consideration is particularly true if the CLOCK input is approaching the maximum throughput rate. As the ADS8322 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just before latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, or nearby digital logic or high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. These errors can change if the external event changes in time with respect to the CLOCK input. 1968 54 For ac signals, a digital filter can be used to low-pass filter and decimate the output codes. This configuration works in a similar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves by 3dB. 0018 Code Figure 14. Histogram of 8,192 Conversions of a Low-Level DC Input On average, the ADS8322 draws very little current from an external reference, as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 11 ADS8322 SBAS215A – JULY 2001 – REVISED JANUARY 2010 www.ti.com The AGND and DGND pins should be connected to a clean ground point. In all cases, this point should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. As with the GND connections, VDD should be connected to a +5V power supply plane, or trace, that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8322 should be clean and well-bypassed. A 0.1μF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1μF to 10μF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. In some situations, additional bypassing may be required, such as a 100μF electrolytic capacitor, or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the +5V supply, removing the high-frequency noise. white space here REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July, 2001) to Revision A Page • Updated document format to current standards ................................................................................................................... 1 • Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2 • Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 3 • Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 6 • Added Figure 12, Linearity Error and Differential Linearity Error vs Code ........................................................................... 8 12 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8322 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS8322Y/250 ACTIVE TQFP PBS 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 B22Y ADS8322Y/2K ACTIVE TQFP PBS 32 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 B22Y ADS8322YB/250 ACTIVE TQFP PBS 32 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 B22Y B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of