ADS8343
ADS8
343
SBAS183C – JANUARY 2001 – REVISED APRIL 2003
16-Bit, 4-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● BIPOLAR INPUT RANGE
The ADS8343 is a 4-channel, 16-bit sampling Analog-toDigital (A/D) converter with a synchronous serial interface.
Typical power dissipation is 8mW at a 100kHz throughput
rate and a +5V supply. The reference voltage (VREF) can be
varied between 500mV and VCC/2, providing a corresponding
input voltage range of ±VREF. The device includes a shutdown mode which reduces power dissipation to under 15µW.
The ADS8343 is ensured down to 2.7V operation.
● PIN-FOR-PIN COMPATIBLE WITH THE
ADS7841 AND ADS8341
● SINGLE SUPPLY: 2.7V to 5V
● 4-CHANNEL SINGLE-ENDED OR
2-CHANNEL DIFFERENTIAL INPUT
● UP TO 100kHz CONVERSION RATE
Low power, high speed, and an onboard multiplexer make
the ADS8343 ideal for battery-operated systems such as
personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also
provides low-cost isolation for remote data acquisition. The
ADS8343 is available in an SSOP-16 package and is ensured over the –40°C to +85°C temperature range.
● 86dB SINAD
● SERIAL INTERFACE
● SSOP-16 PACKAGE
APPLICATIONS
●
●
●
●
●
DATA ACQUISITION
TEST AND MEASUREMENT
INDUSTRIAL PROCESS CONTROL
PERSONAL DIGITAL ASSISTANTS
BATTERY-POWERED SYSTEMS
SAR
DCLK
CS
CH0
CH1
CH2
Comparator
Four
Channel
Multiplexer
Serial
Interface
and
Control
CDAC
CH3
SHDN
DIN
DOUT
BUSY
COM
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO
MISSING
CODES
ERROR (LSB)
ADS8343E
8
"
"
ADS8343EB
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
14
SSOP-16
DBQ
–40°C to +85°C
ADS8343E
Rails, 100
"
"
"
"
ADS8343E/2K5
Tape and Reel, 2500
6
15
SSOP-16
DBQ
–40°C to +85°C
ADS8343EB
Rails, 100
"
"
"
"
"
ADS8343EB/2K5
Tape and Reel, 2500
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATIONS
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Top View
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
SSOP
+VCC
1
16
DCLK
CH0
2
15
CS
CH1
3
14
DIN
CH2
4
13
BUSY
12
DOUT
ADS8343
CH3
5
COM
6
11
GND
SHDN
7
10
GND
VREF
8
9
+VCC
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PIN DESCRIPTIONS
2
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+VCC
CH0
CH1
CH2
CH3
COM
SHDN
VREF
+VCC
GND
GND
DOUT
BUSY
DIN
CS
DCLK
Power Supply, 2.7V to 5V
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Common reference for analog inputs. This pin is typically connected to VREF.
Shutdown. When LOW, the device enters a very low power shutdown mode.
Voltage Reference Input. See Electrical Characteristic Table for ranges.
Power Supply, 2.7V to 5V
Ground
Ground
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH.
Busy Output. This output is high impedance when CS is HIGH.
Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. Maximum input clock frequency
equals 2.4MHz to achieve 100kHz sampling rate.
ADS8343
www.ti.com
SBAS183C
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +85°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8343E
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Positive Input-Negative Input
Positive Input
Negative Input
POWER-SUPPLY REQUIREMENTS
+VCC
Quiescent Current
✻
✻
✻
1.0
20
3
+4.75V < VCC < 5.25V
±8
±2
8.0
±0.05
4.0
✻
✻
✻
✻
=
=
=
=
5Vp-p
5Vp-p
5Vp-p
5Vp-p
at
at
at
at
0.024
0
2.4
2.4
0.5
✻
✻
Specified Performance
4.75
100
3
7.5
–40
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
MHz
MHz
MHz
✻
✻
V
GΩ
µA
µA
µA
✻
5.5
+0.8
1.5
150
Bits
LSB
mV
LSB(1)
%
LSB
µVrms
LSB(1)
dB
dB
dB
dB
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
0.4
Binary Two’s Complement
Power Dissipation
±6
±1
✻
±0.024
✻
✻
✻
✻
CMOS
3.0
–0.3
3.5
V
V
V
pF
µA
✻
✻
✻
✻
+VCC/2
5
40
2.5
0.001
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
✻
✻
✻
✻
–95
86
97
100
DCLK Static
Bits
✻
✻
✻
✻
500
30
100
2.4
10kHz
10kHz
10kHz
50kHz
✻
✻
100
VIN
VIN
VIN
VIN
UNITS
✻
16
4.5
SHDN = VDD
MAX
15
2.3
fSAMPLE = 10kHz
Power-Down Mode(3, 4), CS = +VCC
TEMPERATURE RANGE
Specified Performance
TYP
✻
✻
14
fSAMPLE = 12.5kHz
DCLK Static
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
+VREF
+VCC + 0.2
+VCC + 0.2
–VREF
–0.2
–0.2
Data Transfer Only
REFERENCE INPUT
Range
Resistance
Input Current
MIN
25
±1
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External Clock Frequency
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
MAX
16
Capacitance
Leakage Current
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Bipolar Error
Bipolar Error Match
Gain Error
Gain Error Match
Noise
Power-Supply Rejection
ADS8343EB
5.25
2.0
✻
✻
✻
✻
✻
V
mA
µA
µA
mW
✻
°C
✻
3
10
+85
✻
V
V
V
V
✻ Same specifications as ADS8343E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.
ADS8343
SBAS183C
www.ti.com
3
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8343E
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External Clock Frequency
MAX
MIN
TYP
16
Positive Input-Negative Input
Positive Input
Negative Input
+VREF
+VCC + 0.2
+VCC + 0.2
–VREF
–0.2
–0.2
Capacitance
Leakage Current
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Bipolar Error
Bipolar Error Match
Gain Error
Gain Error Match
Noise
Power-Supply Rejection
ADS8343EB
✻
✻
✻
14
1.0
20
3
±12
±1
4.0
±0.05
4.0
✻
✻
✻
✻
BITS
✻
✻
✻
V
V
V
pF
µA
±8
±0.5
✻
±0.0024
✻
✻
16
✻
4.5
✻
100
✻
✻
✻
✻
500
30
100
2.4
When Used with Internal Clock
Data Transfer Only
✻
15
1.2
SHDN = VDD
UNITS
✻
✻
25
±1
+2.7 < VCC < +3.3V
MAX
0.024
0.024
0
2.4
2.0
2.4
✻
✻
✻
✻
✻
✻
Bits
LSB
mV
LSB
% of FSR
LSB
µVrms
LSB(1)
Clk Cycles
Clk Cycles
kHz
ns
ns
ps
MHz
MHz
MHz
MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
REFERENCE INPUT
Range
Resistance
Input Current
VIN = 2.5Vp-p at 1kHz
VIN = 2.5Vp-p at 1kHz
VIN = 2.5Vp-p at 1kHz
VIN = 2.5Vp-p at 10kHz
0.5
DCLK Static
POWER-SUPPLY REQUIREMENTS
+VCC
Quiescent Current
✻
40
3
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
+VCC • 0.7
–0.3
+VCC • 0.8
Specified Performance
2.7
✻
✻
✻
3.2
–40
✻
✻
✻
✻
✻
0.4
Binary Two’s Complement
Power Dissipation
✻
V
GΩ
µA
µA
µA
✻
5.5
+0.8
1.2
105
dB
dB
dB
dB
✻
✻
✻
✻
✻
CMOS
fSAMPLE = 10kHz
Power-Down Mode(3, 4), CS = +VCC
TEMPERATURE RANGE
Specified Performance
+VCC/2
5
13
2.5
0.001
fSAMPLE = 12.5kHz
DCLK Static
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
✻
✻
✻
✻
–94
81
98
100
3.6
1.85
✻
✻
3
5
+85
✻
✻
✻
V
V
V
V
✻
✻
V
mA
µA
µA
mW
✻
°C
✻ Same specifications as ADS8343E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +1.25V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.
4
ADS8343
www.ti.com
SBAS183C
TYPICAL CHARACTERISTICS: +5V
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
0
10
20
30
40
50
0
10
20
30
40
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
100
50
110
–110
80
100
–100
90
–90
THD(1)
80
–80
SINAD
70
70
60
–70
NOTE: (1) First nine harmonics of the input frequency.
60
1
10
100
1
10
Frequency (kHz)
Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
0.1
15.0
fIN = 4.956kHz, –0.2dB
Delta from 25°C (dB)
14.5
Effective Number of Bits
–60
100
14.0
13.5
13.0
12.5
0
–0.1
–0.2
12.0
11.5
–0.3
11.0
1
10
100
Frequency (kHz)
–25
0
25
50
75
100
Temperature (°C)
ADS8343
SBAS183C
–50
www.ti.com
5
THD (dB)
SFDR (dB)
SNR and SINAD (dB)
SFDR
SNR
90
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs CODE
4
2
3
1
2
DLE (LSBs)
ILE (LSBs)
INTEGRAL LINEARITY ERROR vs CODE
3
0
–1
1
0
–2
–1
–3
–2
–4
8000H
0000H
C000H
4000H
–3
8000H
7FFFH
0000H
C000H
Output Code
SUPPLY CURRENT vs TEMPERATURE
Delta from 25°C (LSBs)
Supply Current (mA)
1
1.5
1.4
1.3
1.2
0
–1
–2
–3
–4
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
CHANGE IN GAIN vs TEMPERATURE
WORST-CASE CHANNEL-TO-CHANNEL
BPZ MATCH vs TEMPERATURE
100
4.5
BPZ Match (LSBs)
1.0
Delta from 25°C (LSBs)
7FFFH
CHANGE IN BPZ vs TEMPERATURE
1.6
0.5
0
–0.5
4.0
3.5
3.0
–50
–25
0
25
50
75
–50
100
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
6
4000H
Output Code
ADS8343
www.ti.com
SBAS183C
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
COMMON-MODE REJECTION vs FREQUENCY
0.4
100
0.3
90
CMRR (dB)
Gain Match (LSBs)
WORST CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
0.2
0.1
80
70
0
60
VCM = 2Vp-p Sinewave
Centered Around VREF
–0.1
50
–50
–25
0
25
50
75
100
0.1
1
Temperature (°C)
10
100
Frequency (kHz)
TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
–60
–80
–100
–120
–80
–100
–120
–140
–140
0
10
20
30
40
50
0
10
20
30
40
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
95
100
50
–100
90
SNR
85
–90
SFDR
SFDR (dB)
SNR and SINAD (dB)
–60
75
SINAD
80
–80
70
THD(1)
–70
65
60
–60
NOTE: (1) First nine harmonics of the input frequency.
55
500
1
10
100
Frequency (kHz)
10
100
Frequency (kHz)
ADS8343
SBAS183C
–50
1
www.ti.com
7
THD (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
0.4
14.0
fIN = 4.956kHz, –0.2dB
0.2
13.0
Delta from 25°C (dB)
Effective Number of Bits
13.5
12.5
12.0
11.5
11.0
10.5
10.0
0
–0.2
–0.4
–0.6
9.5
–0.8
9.0
1
10
–50
100
–25
0
Frequency (kHz)
4
2
3
DLE (LSBs)
ILE (LSBs)
3
1
0
–1
75
100
2
1
0
–1
–2
–2
–3
8000H
0000H
C000H
4000H
–3
8000H
7FFFH
0000H
C000H
Output Code
4000H
7FFFH
Output Code
SUPPLY CURRENT vs TEMPERATURE
CHANGE IN BPZ vs TEMPERATURE
1.0
Delta from 25°C (LSBs)
1.2
Supply Current (mA)
50
DIFFERENTIAL LINEARITY ERROR vs CODE
INTEGRAL LINEARITY ERROR vs CODE
1.1
1.0
0.9
0.5
0
–0.5
–1.0
–50
–25
0
25
50
75
100
–50
Temperature (°C)
8
25
Temperature (°C)
–25
0
25
50
75
100
Temperature (°C)
ADS8343
www.ti.com
SBAS183C
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
WORST-CASE CHANNEL-TO-CHANNEL
BPZ MATCH vs TEMPERATURE
CHANGE IN GAIN vs TEMPERATURE
1.5
BPZ Match (LSBs)
Delta from 25°C (LSBs)
0.5
0
–0.5
–1.0
1.0
0.5
0
–50
–25
0
25
50
75
–50
100
–25
0
50
75
100
COMMON-MODE REJECTION vs FREQUENCY
0.16
80
0.15
70
CMRR (dB)
Gain Match (LSBs)
WORST-CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
0.14
0.13
60
50
VCM = 1Vp-p Sinewave
Centered Around VREF
0.12
–50
–25
0
25
50
75
40
100
0.1
Temperature (°C)
1
10
100
Frequency (kHz)
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs +VSS
140
1.4
External Clock Disabled
fSAMPLE = 100kHz
Supply Current (mA)
120
Supply Current (mA)
25
Temperature (°C)
Temperature (°C)
100
80
60
40
1.3
1.2
1.1
20
0
1.0
–50
–25
0
25
50
75
100
2.5
Temperature (°C)
3.5
4.0
4.5
5.0
+VSS (V)
ADS8343
SBAS183C
3.0
www.ti.com
9
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
SUPPLY CURRENT vs SAMPLING FREQUENCY
1.4
fCLK = 2.4MHz
Supply Current (mA)
1.2
1.0
VSS = 5.0V
0.8
0.6
VSS = 2.7V
0.4
0.2
Power-Down After Conversion Mode.
External Clock Gated HIGH After Conversion.
0
10
20
30
40
50
60
70
80
90
100
Sampling Frequency (kHz)
THEORY OF OPERATION
The ADS8343 is a classic Successive Approximation Register
(SAR) A/D converter. The architecture is based on capacitive
redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µm CMOS process.
The basic operation of the ADS8343 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 500mV and
+VCC/2. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS8343.
The analog input to the converter is differential and is
provided via a 4-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which is
generally VREF) or differentially by using two of the four input
channels (CH0-CH3). The particular configuration is selectable via the digital interface.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8343: single-ended or differential, as shown in Figure 2.
ADS8343
+
1µF
to
10µF
CHX
ADS8343
±VREF(1)
+2.7V to +5V
COM
0.1µF
1
+VCC
DCLK 16
2
CH0
CS 15
3
CH1
DIN 14
4
CH2
BUSY 13
5
CH3
DOUT 12
6
COM
GND 11
7
SHDN
GND 10
8
VREF
+VCC
Common-Mode
Voltage
(typically VREF)
Serial/Conversion
Clock
Chip Select
Single-Ended Input
Single-ended
or differential
analog inputs.
VREF
Serial Data In
±
Serial Data Out
Common-Mode
Voltage
1µF
10
2
(1)
± VREF
2
CHX+
ADS8343
CHX–
Differential Input
9
FIGURE 1. Basic Operation of the ADS8343.
VREF(1)
NOTE: (1) Relative to common-mode voltage.
FIGURE 2. Methods of Driving the ADS8343—Single-Ended
or Differential.
ADS8343
www.ti.com
SBAS183C
When the input is single-ended, the COM input is held at a
fixed voltage. The CHX input swings around the same
voltage and the peak-to-peak amplitude is 2 • VREF. The
value of VREF determines the range over which the common
voltage may vary, as shown in Figure 3.
5
VCC = 5V
4.9
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8343 charges the internal capacitor array during the sample period. After this
capacitance has been fully charged, there is no further input
current.
Common Voltage Range (V)
4
Single-Ended Input
3
2.8
2.1
2
In each case, care should be taken to ensure that the output
impedance of the sources driving the CHX and COM inputs
are matched. If this is not observed, the two inputs could
have different settling times. This may result in offset error,
gain error, and linearity error which change with both temperature and input voltage. If the impedance cannot be
matched, the errors can be lessened by giving the ADS8343
additional acquisition time.
Care must be taken regarding the absolute analog input
voltage. Outside of these ranges, the converter’s linearity
may not meet specifications. Please refer to the electrical
characteristics table for min/max ratings.
1
0.1
0
REFERENCE INPUT
–1
0.5
1.0
1.5
2.0
2.5
VREF (V)
FIGURE 3. Single-Ended Input—Common Voltage Range vs VREF.
When the input is differential, the amplitude of the input is the
difference between the CHX and COM input. A voltage or
signal is common to both of these inputs. The peak-to-peak
amplitude of each input is VREF about this common voltage.
However, since the inputs are 180° out-of-phase, the peakto-peak amplitude of the difference voltage is 2 • VREF. The
value of VREF also determines the range of the voltage that
may be common to both inputs, as shown in Figure 4.
The external reference sets the analog input range. The
ADS8343 will operate with a reference in the range of 500mV
to +VCC/2. Keep in mind that the analog input is the difference between the CHX input and the COM input, as shown
in Figure 5. For example, in the single-ended mode, with
VREF and COM pin set to 1.25V, the selected input channel
(CH0-CH3) will properly digitize a signal in the range of 0V to
2.50V relative to GND. If the COM pin is connected to 2.0V,
the input range on the selected channel is 0.75V to 3.25V.
A2-A0
(Shown 001B)
CH0
CH1
CH2
+IN
CH3
5.2
Converter
5
–IN
VCC = 5V
4.2
Common Voltage Range (V)
4
3
COM
Differential Input
SGL/DIF
(Shown HIGH)
2
FIGURE 5. Simplified Diagram of the Analog Input.
1
0.8
0.2
0
0.0
1.0
1.5
2.0
2.5
VREF (V)
FIGURE 4. Differential Input—Common Voltage Range vs VREF.
There are several critical items concerning the reference
input and its wide voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB
(Least Significant Bit) size and is equal to the reference
voltage divided by 65,536. Any offset or gain error inherent
in the A/D converter will appear to increase, in terms of LSB
ADS8343
SBAS183C
www.ti.com
11
size, as the reference voltage is reduced. For example, if the
offset of a given converter is 2LSBs with a 2.5V reference,
then it will typically be 10LSBs with a 0.5V reference. In each
case, the actual offset of the device is the same, 76µV.
converter enters the conversion mode. At this point, the input
sample-and-hold goes into the hold mode. The next 16 clock
cycles accomplish the actual A/D conversion.
The noise or uncertainty of the digitized output will increase
with lower LSB size. With a reference voltage of 500mV, the
LSB size is 7.6µV. This level is below the internal noise of the
device. As a result, the digital output code will not be stable
and vary around a mean value by a number of LSBs. The
distribution of output codes will be gaussian and the noise
can be reduced by simply averaging consecutive conversion
results or applying a digital filter.
Also shown in Figure 6 is the placement and order of the
control bits within the control byte. Tables I and II give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS8343 will ignore inputs on the DIN pin until the
start bit is detected. The next three bits (A2-A0) select the
active input channel or channels of the input multiplexer, as
shown in Tables III and IV and Figure 5.
Control Byte
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
S
A2
A1
A0
—
SGL/DIF
PD1
PD0
TABLE I. Order of the Control Bits in the Control Byte.
The voltage into the VREF input is not buffered and directly
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS8343. Typically, the input current is 13µA
with a 2.5V reference. This value will vary by microamps
depending on the result of the conversion. The reference
current diminishes directly with both conversion rate and
reference voltage. As the current from the reference is drawn
on each bit decision, clocking the converter more quickly
during a given conversion period will not reduce overall
current drain from the reference.
BIT
NAME
DESCRIPTION
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN.
6-4
A2-A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2-A0, this bit controls the setting of the multiplexer
input.
1-0
PD1-PD0
Power-Down Mode Select Bits. See Table V for
details.
TABLE II. Descriptions of the Control Bits within the Control Byte.
DIGITAL INTERFACE
Figure 6 shows the typical operation of the ADS8343’s digital
interface. This diagram assumes that the source of the digital
signals is a microcontroller or digital signal processor with a
basic serial interface (note that the digital inputs are overvoltage tolerant up to 5.5V, regardless of +VCC). Each communication between the processor and the converter consists of eight clock cycles. One complete conversion can be
accomplished with three serial communications, for a total of
24 clock cycles on the DCLK input.
A2
A1
A0
CH0
0
0
1
+IN
1
0
1
0
1
0
1
1
0
CH1
CH2
CH3
COM
–IN
+IN
–IN
+IN
–IN
+IN
–IN
TABLE III. Single-Ended Channel Selection (SGL/DIF HIGH).
The first eight cycles are used to provide the control byte via
the DIN pin. When the converter has enough information
about the following conversion to set the input multiplexer
appropriately, it enters the acquisition (sample) mode. After
three more clock cycles, the control byte is complete and the
A2
A1
A0
CH0
CH1
0
0
1
+IN
–IN
CH2
CH3
1
0
1
–IN
+IN
0
1
0
+IN
–IN
1
1
0
–IN
+IN
COM
TABLE IV. Differential Channel Control (SGL/DIF LOW).
CS
tACQ
DCLK
1
8
Idle
DIN
S
A2
8
1
Acquire
A1
A0
1
8
1
8
Conversion
Idle
SGL/ PD1 PD0
DIF
S
(START)
A2
Acquire
A1
A0
1
Conversion
SGL/ PD1 PD0
DIF
(START)
BUSY
DOUT
15
14
13
12
11
10
9
8
7
(MSB)
6
5
4
3
2
1
0
(LSB)
Zero Filled...
15
14
(MSB)
FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
12
ADS8343
www.ti.com
SBAS183C
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables III and IV and Figure 5 for more
information. The last two bits (PD1-PD0) select the powerdown mode as shown in Table V. If both inputs are HIGH, the
device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be valid.
PD1
PD0
0
0
1
0
1
0
1
1
DESCRIPTION
Power-down between conversions. When each
conversion is finished, the converter enters a lowpower mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
Selects internal clock mode.
Reserved for future use.
No power-down between conversions, device always powered. Selects external clock mode.
TABLE V. Power-Down Selection.
Clock Modes
The ADS8343 can be used with an external serial clock or an
internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data
in and out of the device. Internal clock mode is selected
when PD1 is HIGH and PD0 is LOW.
If the user decides to switch from one clock mode to the
other, an extra conversion cycle will be required before the
ADS8343 can switch to the new mode. The extra cycle is
required because the PD0 and PD1 control bits need to be
written to the ADS8343 prior to the change in clock modes.
When power is first applied to the ADS8343, the user must
set the desired clock mode. It can be set by writing PD1 = 1
and PD0 = 0 for internal clock mode or PD1 = 1 and PD0
= 1 for external clock mode. After enabling the required clock
mode, only then should the ADS8343 be set to power-down
between conversions (i.e., PD1 = PD0 = 0). The ADS8343
maintains the clock mode it was in prior to entering the
power-down modes.
External Clock Mode
In external clock mode, the external clock not only shifts data
in and out of the ADS8343, it also controls the A/D conversion steps. BUSY will go HIGH for one clock period after the
last bit of the control byte is shifted in. Successive-approximation bit decisions are made and appear at DOUT on each
of the next 16 DCLK falling edges, see Figure 6. Figure 7
shows the BUSY timing in external clock mode.
Since one clock cycle of the serial clock is consumed with
BUSY going HIGH (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits of
data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
presented in Figure 6, where the beginning of the next
control byte appears at the same time the LSB is being
clocked out of the ADS8343. This method allows for maximum throughput and 24 clock cycles per conversion.
CS
tCSS
tCL
tCH
tBD
tBD
tD0
tCSH
DCLK
tDS
DIN
tDH
PD0
tBDV
tBTR
BUSY
tDV
tTR
DOUT
15
14
FIGURE 7. Detailed Timing Diagram.
ADS8343
SBAS183C
www.ti.com
13
The other method is shown in Figure 8, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when CS goes HIGH; after the next
CS falling edge, BUSY will go LOW.
SYMBOL
DESCRIPTION
MIN
tACQ
Acquisition Time
1.5
TYP
MAX
UNITS
tDS
DIN Valid Prior to DCLK Rising
100
ns
tDH
DIN Hold After DCLK HIGH
10
ns
µs
tDO
DCLK Falling to DOUT Valid
200
ns
Internal Clock Mode
tDV
CS Falling to DOUT Enabled
200
ns
tTR
CS Rising to DOUT Disabled
200
ns
In internal clock mode, the ADS8343 generates its own
conversion clock internally. This relieves the microprocessor
from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz. BUSY
goes LOW at the start of conversion and then returns HIGH
when the conversion is complete. During the conversion,
BUSY will remain LOW for a maximum of 8µs. Also, during
the conversion, DCLK should remain LOW to achieve the
best noise performance. The conversion result is stored in an
internal register; the data may be clocked out of this register
any time after the conversion is complete.
tCSS
CS Falling to First DCLK Rising
100
ns
tCSH
CS Rising to DCLK Ignored
0
ns
tCH
DCLK HIGH
200
ns
tCL
DCLK LOW
200
tBD
DCLK Falling to BUSY Rising
200
ns
tBDV
CS Falling to BUSY Enabled
200
ns
tBTR
CS Rising to BUSY Disabled
200
ns
ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
SYMBOL
If CS is LOW when BUSY goes LOW following a conversion,
the next falling edge of the external serial clock will write out
the MSB on the DOUT line. The remaining bits (D14-D0) will
be clocked out on each successive clock cycle following the
MSB. If CS is HIGH when BUSY goes LOW then the DOUT
line will remain in tri-state until CS goes LOW, as shown in
Figure 9. CS does not need to remain LOW once a conversion has started. Note that BUSY is not tri-stated when CS
goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8343 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition time
tACQ, is kept above 1.7µs.
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
Acquisition Time
1.7
tDS
DIN Valid Prior to DCLK Rising
50
ns
tDH
DIN Hold After DCLK HIGH
10
ns
µs
tDO
DCLK Falling to DOUT Valid
100
ns
tDV
CS Falling to DOUT Enabled
70
ns
tTR
CS Rising to DOUT Disabled
70
ns
tCSS
CS Falling to First DCLK Rising
50
ns
tCSH
CS Rising to DCLK Ignored
0
ns
tCH
DCLK HIGH
150
ns
tCL
DCLK LOW
150
tBD
DCLK Falling to BUSY Rising
100
ns
tBDV
CS Falling to BUSY Enabled
70
ns
tBTR
CS Rising to BUSY Disabled
70
ns
ns
TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V,
TA = –40°C to +85°C, CLOAD = 50pF).
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for the
digital interface of the ADS8343.
CS
tACQ
DCLK
1
8
Idle
DIN
S
A2
1
8
Acquire
A1
A0
1
1
8
8
Conversion
Idle
SGL/
DIF PD1 PD0
(START)
BUSY
DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(MSB)
Zero Filled...
0
(LSB)
FIGURE 8. External Clock Mode 32 Clocks Per Conversion.
CS
tACQ
DCLK
1
8
Idle
DIN
S
A2
Acquire
A1
A0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Conversion
SGL/
DIF PD1 PD0
(START)
BUSY
DOUT
15
14
13
12
11
10
(MSB)
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
FIGURE 9. Internal Clock Mode Timing.
14
ADS8343
www.ti.com
SBAS183C
DATA FORMAT
The output data from the ADS8343 is in Binary Two’s
Complement format, as shown in Table VIII. This table
represents the ideal output code for the given input voltage
and does not include the effects of offset, gain, or noise.
DIGITAL OUTPUT
Full-Scale Range
2 • VREF
Least Significant
Bit (LSB)
2 • VREF/65536
BINARY CODE
HEX CODE
+Full-Scale
+VREF – 1LSB
0111 1111 1111 1111
7FFF
0V
0000 0000 0000 0000
0000
0V – 1LSB
1111 1111 1111 1111
FFFF
–VREF
1000 0000 0000 0000
8000
Midscale
Midscale – 1LSB
–Full-Scale
BINARY TWO’S COMPLEMENT
1000
fCLK = 24 • fSAMPLE
TABLE VIII. Ideal Input Voltages and Output Codes.
POWER DISSIPATION
There are three power modes for the ADS8343: full-power
(PD1 = PD0 = 1B), auto power-down (PD1 = PD0 = 0B), and
shutdown (SHDN LOW). The affects of these modes varies
depending on how the ADS8343 is being operated. For
example, at full conversion rate and 24-clocks per conversion, there is very little difference between full-power mode
and auto power-down, a shutdown (SHDN LOW) will not
lower power dissipation.
When operating at full-speed and 24 clocks per conversion
(see Figure 6), the ADS8343 spends most of its time acquiring or converting. There is little time for auto power-down,
assuming that this mode is active. Thus, the difference
between full-power mode and auto power-down is negligible.
If the conversion rate is decreased by simply slowing the
frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the
maximum rate during a conversion, but conversion are simply done less often, then the difference between the two
modes is dramatic. Figure 10 shows the difference between
reducing the DCLK frequency (“scaling” DCLK to match the
conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversion per second.
In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto
power-down mode is active).
Supply Current (µA)
ANALOG VALUE
Operating the ADS8343 in auto power-down mode will result
in the lowest power dissipation, and there is no conversion
time “penalty” on power-up. The very first conversion will be
valid. SHDN can be used to force an immediate power-down.
100
fCLK = 2.4MHz
10
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
PD1 = PD0 = 0
1
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 10. Supply Current versus Directly Scaling the Frequency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
14
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
fCLK = 24 • fSAMPLE
PD1 = PD0 = 0
12
Supply Current (µA)
DESCRIPTION
If DCLK is active and CS is LOW while the ADS8343 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 11.
10
8
6
CS LOW
(GND)
4
2
CS HIGH (+VCC)
0
0.09
0.00
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 11. Supply Current vs State of CS .
ADS8343
SBAS183C
www.ti.com
15
NOISE
AVERAGING
The noise floor of the ADS8343 itself is extremely low, as can
be seen from Figures 12 and 13, and is much lower than
competing A/D converters. The ADS8343 was tested at both
5V and 2.7V and in both the internal and external clock
modes. A low-level DC input was applied to the analog input
pins and the converter was put through 5000 conversions.
The digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8343. This is true for all
16-bit, SAR-type, A/D converters. Using a histogram to plot
the output codes, the distribution should appear bell-shaped
with the peak of the bell curve representing the nominal code
for the input value. The ±1σ, ±2σ, and ±3σ distributions will
represent the 68.3%, 95.5%, and 99.7%, respectively, of all
codes. The transition noise can be calculated by dividing the
number of codes measured by 6 and this will yield the ±3σ
distribution or 99.7% of all codes. Statistically, up to 3 codes
could fall outside the distribution when executing 1000 conversions. The ADS8343, with < 3 output codes for the ±3σ
distribution, will yield a < ±0.5LSB transition noise at 5V
operation. Remember, to achieve this low noise performance, the peak-to-peak noise of the input signal and
reference must be < 50µV.
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to
±0.25LSBs. Averaging should only be used for input signals
with frequencies near DC.
3295
774
131
FFFEH
FFFFH
0000H
0001H
0002H
Code
FIGURE 12. Histogram of 5000 Conversions of a DC Input at the
Code Transition, 5V Operation External Clock Mode.
2387
905
8
512
38
38
7
FFFCH FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H 0004H
Code
FIGURE 13. Histogram of 5000 Conversions of a DC Input at the
Code Center, 2.7V Operation Internal Clock Mode.
16
For optimum performance, care should be taken with the
physical layout of the ADS8343 circuitry. This is particularly true
if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output of the
analog comparator. Thus, during any single conversion for an nbit SAR converter, there are n “windows” in which large external
transient voltages can easily affect the conversion result. Such
glitches might originate from switching power supplies, nearby
digital logic, and high-power devices. The degree of error in the
digital output depends on the reference voltage, layout, and the
exact timing of the external event. The error can change if the
external event changes in time with respect to the DCLK input.
The reference should be similarly bypassed with a 1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8343 draws very little
current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS8343 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply will
appear directly in the digital results. While high-frequency
noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
694
411
LAYOUT
With this in mind, power to the ADS8343 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
705
95
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signalto-noise ratio will improve 3dB.
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller
or digital signal processor. If needed, run a ground trace
directly from the converter to the power-supply entry point. The
ideal layout will include an analog ground plane dedicated to
the converter and associated analog circuitry.
ADS8343
www.ti.com
SBAS183C
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADS8343E
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS
8343E
ADS8343E/2K5
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS
8343E
ADS8343EB
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS
8343E
B
ADS8343EBG4
ACTIVE
SSOP
DBQ
16
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS
8343E
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
