User's Guide
SBAU210A – June 2014 – Revised August 2014
ADS8353EVM-PDK and ADS7853EVM-PDK
ADS8353EVM-PDK and ADS7853EVM-PDK
This user's guide describes the characteristics, operation and use of the ADS8353EVM and
ADS7853EVM performance demonstration kits (PDKs). These kits are evaluation platforms for the
ADS8353 and ADS7853, dual-channel, 16-bit and 14-bit, simultaneous sampling, successive
approximation register (SAR) analog-to-digital converters (ADCs) that support single-ended and pseudodifferential analog inputs. These EVMs ease the evaluation of the ADS8353 and ADS7853 devices with
hardware and software for computer connectivity through universal serial bus (USB). This user's guide
includes a complete circuit descriptions, schematic diagrams, and bill of materials.
Throughout this document, the terms ADSxx53EVM-PDK, demonstration kit, evaluation board, evaluation
module are synonyms with the ADS8353EVM-PDK and ADS7853EVM-PDK.
The following related documents are available through the Texas Instruments web site at
http://www.ti.com.
Related Documentation
Device
Literature Number
ADS8353
SBAS584
ADS7853
SBAS584
REF5025
SBOS410
OPA2350
SBOS099
OPA376
SBOS406
OPA836, OPA2836
SLOS712
TPS3836E18
SLVS292
TPS7A4700
SBVS204
REG71055
SBAS221
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Contents
Overview ...................................................................................................................... 4
1.1
ADSxx53EVM Features ............................................................................................ 4
1.2
ADSxx53EVM-PDK Features ..................................................................................... 4
EVM Analog Interface ....................................................................................................... 4
2.1
Analog Input Range Settings ...................................................................................... 6
2.2
Single-Ended or Pseudo-Differential Input Configuration ..................................................... 6
2.3
Bipolar Input-Signal Configuration ................................................................................ 6
2.4
Unipolar Input-Signal Configuration .............................................................................. 7
2.5
ADSxx53EVM Onboard Reference and ADSxx53 Device Internal Reference ............................. 7
Digital Interface .............................................................................................................. 9
3.1
Serial Interface (SPI) ............................................................................................... 9
3.2
I2C Bus for Onboard EEPROM.................................................................................... 9
Power Supplies ............................................................................................................. 10
ADSxx53EVM-PDK Initial Setup ......................................................................................... 11
5.1
Default Jumper Settings .......................................................................................... 11
5.2
Software Installation .............................................................................................. 12
ADSxx53EVM-PDK Kit Operation ........................................................................................ 18
6.1
About the Simple Capture Card Controller Board............................................................. 18
6.2
Loading the ADSxx53EVM-PDK Software ..................................................................... 18
6.3
ADSxx53EVM Settings ........................................................................................... 19
6.4
Device Registers .................................................................................................. 22
6.5
Capturing Data with the ADSxx53EVM-PDK .................................................................. 22
6.6
FFT Analysis ...................................................................................................... 25
6.7
Histogram Analysis ................................................................................................ 27
6.8
Troubleshooting ................................................................................................... 27
Bill of Materials, PCB Layout, and Schematics......................................................................... 29
7.1
Bill of Materials .................................................................................................... 29
7.2
PCB Layout ........................................................................................................ 31
7.3
Schematics ......................................................................................................... 32
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2
.................................................................... 5
Single-Ended or Pseudo-Differential Input Configuration .............................................................. 6
Bipolar Input Signal Configuration with 2 × Vref range................................................................... 7
Unipolar Input Signal Configuration ....................................................................................... 7
REF5025 2.5-V External Reference Source and OPA2350 Reference Driver ..................................... 8
ADSxx53EVM Default Jumper Settings ................................................................................. 11
Bottom View of Simple Capture Card Board with microSD Card Installed ........................................ 13
Bottom View of ADSxx53EVM Rev C with microSD Card Installed ................................................. 13
Connecting the ADSxx53EVM Board to the Simple Capture Card Controller Board ............................. 14
LED Indicators on a Simple Capture Card Board ...................................................................... 14
Welcome Screen and Destination Directory Screens ................................................................. 15
License Agreement and Start Installation Screens .................................................................... 15
Progress Bar and Installation Complete Screens ...................................................................... 16
Windows 7 Driver Installation Warning .................................................................................. 16
Simple Capture Card Device Driver Installation ........................................................................ 17
Simple Capture Card Device Driver Completion ....................................................................... 17
GUI Display Prompt ........................................................................................................ 18
Open the ADSxx53 EVM Settings Page ................................................................................ 19
Selecting the External Onboard Reference or the ADSxx53 Internal Dual Reference ............................ 19
Programming the REFDAC Registers in the ADSxx53EVM.......................................................... 20
ADSxx53EVM Analog Interface Input Connections
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Selecting 0 to Vref Range or 0 to 2 × Vref Range ........................................................................ 20
22
Single-Ended or Pseudo-Differential Jumper Settings Description on the GUI .................................... 21
23
Bipolar or Unipolar Signal Jumper Settings Description on the GUI
24
Device Registers Page .................................................................................................... 22
................................................
21
25
Open the Data Monitor Page on the GUI ............................................................................... 22
26
Data Monitor Page ......................................................................................................... 23
27
Saving Data to a Text File
28
FFT Performance Analysis Page ......................................................................................... 25
29
Histogram Analysis ......................................................................................................... 27
30
Open the GUI Settings Page
31
Set Capture Mode to SDCC Interface While Using the EVM Hardware ............................................ 28
32
ADSxx53EVM PCB: Top Layer........................................................................................... 31
33
ADSxx53EVM PCB: Ground Layer ...................................................................................... 31
34
ADSxx53EVM PCB: Power Layer........................................................................................ 32
35
ADSxx53EVM PCB: Bottom Layer ....................................................................................... 32
................................................................................................
.............................................................................................
24
28
List of Tables
1
2
3
4
5
6
7
................................................................................ 5
SMA Analog Interface Connections ....................................................................................... 5
Analog Input Range Jumpers .............................................................................................. 6
Connector J6 Pin Out ....................................................................................................... 9
Power-Supply Jumpers .................................................................................................... 10
Default Jumper Configuration............................................................................................. 11
ADSxx53EVM Bill of Materials ........................................................................................... 29
JP1 - JP2: Analog Interface Connections
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Overview
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Overview
The ADSxx53EVM-PDK is a platform for evaluation of the ADSxx53 analog-to-digital converter (ADC).
The evaluation kit combines the ADSxx53EVM board with a simple capture card controller board. The
simple capture card controller board consists of a TI Sitara embedded microcontroller (AM3352) and a
field programmable gate array (FPGA). The simple capture card board provides an interface from the
EVM to the computer through a universal serial bus (USB) port. The included software communicates with
the simple capture card controller board platform, and the simple capture card board provides the power
and digital signals used to communicate with the ADSxx53EVM board. These demonstration kits include
the ADSxx53EVM board, the simple capture card controller board, a microSD memory card, and an A-tomicro-B USB cable.
1.1
ADSxx53EVM Features
•
•
•
•
•
•
1.2
ADSxx53EVM-PDK Features
•
•
•
•
•
•
2
Contains support circuitry as a design example to match ADC performance
3.3-V slave serial peripheral interface (SPI™)
Onboard 5-V analog Supply
Onboard REF5025 (2.5-V) reference
Voltage reference buffering with OPA2350
Onboard OPA2836 (205-MHz BW, 1-mA quiescent current) ADC operational amplifier input drivers
Jumper-selectable (0 to 1 × Vref range or 0 to 2 × Vref range.
USB port for computer interfacing
Easy-to-use evaluation software for Windows XP®, Windows 7®, Windows 8® operating systems
Data collection to text files
Built-in analysis tools including scope, FFT, and histogram displays
Complete control of board settings
EVM Analog Interface
The ADSxx53 is a dual-channel, simultaneous-sampling ADC that supports single-ended and pseudodifferential analog inputs. Each channel of the ADSxx53 uses a OPA2836 dual operational amplifier to
drive the inputs of the ADC. The positive input terminals of each ADC are driven by the OPA836
operational amplifier configured in the inverting configuration. The negative input terminals of each ADC
are driven by the OPA836 in the buffer configuration. The ADSxx53EVM is designed for easy interfacing
to multiple analog sources. SMA connectors allow the EVM to have input signals connected through
coaxial cables. In addition, header connectors JP1 and JP2 provide a convenient way to connect input
signals. Figure 1 illustrates the ADSxx53EVM analog interface input connections.
Windows XP, Windows 7, Windows 8, Excel are registered trademarks of Microsoft Corporation.
SPI is a trademark of Motorola Inc.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
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OPA836
Inverting Configuration
AVDD
ADSxx53
VCM
SMA J1
AIN_A
+
AINP-A (Pin 1)
-
Header JP1.2
AINM-A (Pin 2)
Optional voltage divider and
OPA836 Buffer
VREF
JP7
OPA836
Inverting Configuration
AVDD
VCM
SMA J2
AIN_B
+
AINP-B (Pin 8)
-
Header JP2.2
AINM-B (Pin 7)
Optional voltage divider and
OPA836 Buffer
VREF
JP8
Figure 1. ADSxx53EVM Analog Interface Input Connections
Table 1 summarizes the JP1 and JP2 analog interface connections.
Table 1. JP1 - JP2: Analog Interface Connections
Pin Number
Signal
Description
JP1.2
AIN_A
CHA inverted input. The signal is routed through an OPA836
in the inverting configuration.
JP2.2
AIN_B
CHB inverted input. The signal is routed through an OPA836
in the inverting configuration.
Table 2 lists the SMA analog inputs.
Table 2. SMA Analog Interface Connections
Pin Number
Signal
Description
J1
AIN_A
Channel A inverted input. The signal is routed through an
OPA836 in the inverting configuration
J2
AIN_B
Channel B inverted input. The signal is routed through an
OPA836 in the inverting configuration.
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EVM Analog Interface
2.1
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Analog Input Range Settings
The full-scale range (FSR) of the ADSxx53 device can be programmed to either from (0 to 1 × Vref) or (0 to
2 × Vref) range by setting bit B9 of the ADSxx53 configuration register. This register is common to both
ADCs in the device (ADC_A and ADC_B). Configure the full-scale range setting in the EVM by navigating
to the ADSxx53EVM Settings page on the grpahical user interface (GUI); see section Section 6.3 for more
information. Install jumpers JP3 and JP4 when supporting the 0 to 1 × Vref range, and remove jumpers JP3
and JP4 when supporting the 0 to 2 x Vref range, as shown in Table 3.
Table 3. Analog Input Range Jumpers
Jumper Number Default Position
2.2
Description
JP3
Installed
Install for FSR = 0 to 1 × Vref; remove for FSR = 0 to 2 × Vref.
JP4
Installed
Install for FSR = 0 to 1 × Vref; remove for FSR = 0 to 2 × Vref.
Single-Ended or Pseudo-Differential Input Configuration
The ADSxx53 dual, simultaneous ADC supports single-ended or pseudo-differential analog input signals.
To support single-ended inputs, set bit B7 in the configuration (CFR) register to 0 (CFR.B7 = 0), and
connect ADC inputs AINM_A and AINM_B to GND. These devices can also be programmed to support
pseudo-differential inputs by setting bit B7 in the CFR register to 1 (CFR.B7 = 1). In this configuration,
AINM_A is connected to FSR_ADC_A / 2, and AINM_B is connected to FSR_ADC_B / 2. Note that bit
CFR.B7 is common to both ADCs. By configuring jumpers JP7 and JP8 on the ADSxx53EVM, the
negative inputs of the ADC can be connected to GND to support the single-ended configuration, or
connected to FSR/2 when programmed to support pseudo-differential inputs, as shown in Figure 2. See
Section 6.3 for more information.
FSR
FSR
AINP_x
0V
AINP_x
0V
ADSxx53
ADSxx53
AINM_x
AINM_x
FSR / 2
FSR / 2
JP7/JP8:
Shunt 2-3
JP7/JP8:
Shunt 1-2
Single-Ended Configuration
Pseudo-Differential Configuration
Figure 2. Single-Ended or Pseudo-Differential Input Configuration
2.3
Bipolar Input-Signal Configuration
The ADSxx53EVM-PDK supports both bipolar or unipolar input signals on the J1 (JP1.2) and J2 (JP2.2)
analog interface connectors. When jumpers JP9 and JP10 are closed, the inverting amplifier (OPA836) is
biased at the appropiate common-mode voltage level to support bipolar signals on the analog interface
connectors. In this configuration, apply a bipolar input signal with 0-V common-mode voltage.
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Figure 3 shows an example where the ADSxx53EVM is configured to support a bipolar input signal with 2
× Vref range at the J1 (JP1.2) and J2 (JP2.2) analog interface connectors.
4.8 V
Bipolar Input Signal
2.5 V
1 k
10
+2.3 V
1 k
0V
0.2 V
AINP
5V
J1/J2
-
-2.3 V
8200 pF
OPA836
+1.25 V
JP9/JP10 (CLOSED)
+
10
GND or
FSR/2
AINN
Figure 3. Bipolar Input Signal Configuration with 2 × Vref range
2.4
Unipolar Input-Signal Configuration
When jumpers JP9 and JP10 are open, the inverting amplifier (OPA836) is biased at the appropiate
common-mode voltage level to support unipolar signals on the analog interface connectors. In this
configuration, apply a unipolar input signal with FSR / 2 common-mode voltage. Figure 4 shows an
example where the ADSxx53EVM is configured to support a unipolar input signal with 2 × Vref range at the
J1 (JP1.2) and J2 (JP2.2) analog interface connectors.
4.8 V
2.5 V
1 k
Unipolar Input Signal
10
+4.8 V
1 k
2.5 V
0.2 V
AINP
5V
J1/J2
-
0.2 V
8200 pF
OPA836
+2.5 V
JP9/JP10 (OPEN)
+
10
GND or
FSR/2
AINN
Figure 4. Unipolar Input Signal Configuration
2.5
ADSxx53EVM Onboard Reference and ADSxx53 Device Internal Reference
The ADSxx53 dual, simultaneous ADC operates with reference voltages VREF_A and VREF_B present
on pins REFIO_A and REFIO_B, respectively. The ADSxx53 device incorporates two internal individuallyprogrammable 2.5-V reference sources. Alternatively, the onboard 2.5-V reference, REF5025 (U5), can
also be selected. The reference voltage source is determined by setting bit B6 of the ADC configuration
register. Note that this bit is common to ADC_A and ADC_B. Configure the reference settings on the
ADSxx53EVM-PDK by navigating to the ADSxx53EVM Settings page on the GUI; see Section 6.3 for
more information. By default, the evaluation module is set up with the onboard external reference source,
with jumpers JP5 and JP6 installed, as shown in Figure 5. If the ADSxx53 must be configured with the
internal reference, make sure to remove jumpers JP5 and JP6 before enabling the internal reference.
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1k
2.5V from
REF5025
1µF
0.22
OPA2350
A/B
+
+
JP5/JP6
REFIO-A/
REFIO-B
0.22
5V
10µF
10µF
Figure 5. REF5025 2.5-V External Reference Source and OPA2350 Reference Driver
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3
Digital Interface
Socket strip connector J6 provides the digital I/O connections between the ADSxx53EVM board and the
simple capture card board.
Table 4 summarizes the pin-outs for connector J6.
Table 4. Connector J6 Pin Out
3.1
Pin Number
Signal
J6.2, J6.10, J6.15, J6.16,
J6.18
GND
J6.4
EVM PRESENT
2
Description
Ground connections
EVM present signal, active low
I2C bus; used only used to program the U7
EEPROM on the EVM board
J6.11, J6.12
I C™ bus
J6.13
DVDD
J6.34
CS
J6.36
SCLK
J6.38
SDI
J6.40
SDO_A
Serial data output for channel A
J6.42
SDO_B
Serial data output for channel B
3.3V digital supply from the simple capture card
controller board
Chip select, active low
Serial interface clock
Serial data input
Serial Interface (SPI)
The ADSxx53 digital output is available in SPI-compatible format, which makes interfacing with
microprocessors, digital signal processors (DSPs), and FPGAs easy. The ADSxx53EVM offers 47-Ω
resistors between the SPI signals and connector J6 to aid with signal integrity. Typically, in high-speed
SPI communication, fast signal edges can cause overshoot; these 47-Ω resistors slow down the signal
edges in order to minimize signal overshoot.
3.2
I2C Bus for Onboard EEPROM
The ADSxx53EVM has an I2C bus to communicate with the onboard EEPROM that records the board
name and assembly date. It is not used in any form by the ADSxx53 converter.
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Power Supplies
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Power Supplies
The analog portion of the ADSxx53EVM-PDK requires a 5-V supply. The ADSxx53EVM-PDK is configured
at the factory using the onboard regulated analog 5-V supply (+VA); and an onboard 3.3-V digital supply.
Alternatively, set the AVDD analog supply voltage by connecting an external power source through twoterminal connector (J5). Table 5 lists the configuration details for P3.
Table 5. Power-Supply Jumpers
Pin Number
Pin Name
JP12
Shunt 2-3 (default)
Shunt 1-2
JP11
Function
Onboard 5-V AVDD analog supply selected
External 5-V AVDD connected through two-terminal
block J5
Open
Onboard regulated AVDD supply set to 5.0 V
Closed
Onboard regulated AVDD supply set to 5.2 V
CAUTION
The external AVDD supply applied to external two-terminal connector J5 must
not exceed 5.5 V or device damage may occur. The external AVDD supply
must be in the range of 5.0 V to 5.5 V for proper ADSxx53EVM operation.
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5
ADSxx53EVM-PDK Initial Setup
This section presents the steps required to set up the ADSxx53EVM-PDK kit before operation.
5.1
Default Jumper Settings
Figure 6 shows the silkscreen plot detailing the default jumper settings. Table 6 descibes the configuration
for these jumpers.
Figure 6. ADSxx53EVM Default Jumper Settings
Table 6. Default Jumper Configuration
Pin Number
Default Position
JP1
Open
JP1.2 Header connector to inverted AINP-A input
JP2
Open
JP2.2 Header connector to inverted AINP-B input
JP3
Closed
Closed when configured in 0 to 1 × Vref range; open to support 0 to 2 × Vref range
JP4
Closed
Closed when configured in 0 to 1 × Vref range; open to support 0 to 2 × Vref range
JP5
Closed
Closed to connect onboard 2.5-V reference to REFIO_A; open when using ADSxx53
internal reference.
JP6
Closed
Closed to connect onboard 2.5-V reference to REFIO_B; open when using ADSxx53
internal reference.
JP7
Shunt 1-2
Shunt 1-2 connects AINM-A(–) to GND; shunt 2-3 connects AINM-A(–) to FSR / 2.
JP8
Shunt 1-2
Shunt 1-2 connects AINM-B(–) to GND; shunt 2-3 connects AINM-B(–) to FSR / 2 .
JP9
Closed
Open for channel A unipolar input signals at SMA connector; installed for channel A
bipolar input signals at SMA connector
JP10
Closed
Open for channel B unipolar input signals at SMA connector; installed for channel B
bipolar input signals at SMA connector
JP11
Open
JP12
Shunt 2-3
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Switch Description
Open: onboard AVDD set to +5 V; closed: onboard AVDD set to +5.2 V
Shunt 2-3 selects onboard regulated AVDD supply; shunt 1-2 selects external AVDD
through J5
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ADSxx53EVM-PDK Initial Setup
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Software Installation
This section presents the steps required to the install the software. Section 6 explains how to operate the
software to acquire data.
NOTE:
The ADSxx53EVM-PDK with ADSxx53 PWB Board revision A includes (1) microSD card.
Ensure the microSD memory card included in the kit is installed in the microSD socket on the
back of the simple capture card board before connecting the EVM to the PC. Otherwise, as a
result of improper boot up, Windows cannot recognize the ADSxx53EVM-PDK as a
connected device.
The ADSxx53EVM-PDK with ADSxx53 PWB Board revision C includes (2) microSD cards.
Ensure both microSD memory cards that contain the software are installed in the microSD
sockets on the back of the simple capture card board and on the back of ADSxx53EVM
board respectively. Otherwise, as a result of improper boot up, Windows cannot recognize
the ADSxx53EVM-PDK as a connected device.
Complete the following steps to install the software:
Step 1. Verify the microSD memory card(s) are installed:
• ADSxx53EVM PWB revision A: This PDK kit version includes (1) microSD Card. Verify
the microSD memory card is installed on the simple capture card controller board.
• ADSxx53EVM PWB revision C: This PDK kit version includes (2) microSD Cards. Ensure
both microSD memory cards are installed in the microSD sockets on the back of the
simple capture card board and ADSxx53EVM board respectively.
Step 2. Verify jumpers are in the factory-default position and connect the hardware
Step 3. Install the ADSxx53EVM-PDK software.
Step 4. Complete the simple capture card device driver installation.
Each task is described in the following subsections.
5.2.1
Verify the microSD Memory Card is Installed on the Simple Capture Card Controller Board
The ADSxx53EVM-PDK includes the micro SD card(s) that contain the EVM software and simple capture
card controller board firmware required for the EVM operation.
NOTE: Ensure the microSD memory card is installed in the microSD socket (P6) on the back of the
simple capture card board.
Figure 7 illustrates the bottom view of the simple capture card controller board with the
microSD card installed.
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Figure 7. Bottom View of Simple Capture Card Board with microSD Card Installed
NOTE:
ADSxx53EVM-PDK with ADSxx53EVM PWB Board revision C (only): This
ADSxx53EVM PWB version includes (2) microSD cards. Ensure both microSD memory
cards are installed in the microSD sockets on the back of the simple capture card board and
on the back of ADSxx53EVM, as shown on Figure 7 and Figure 8 respectively.
Figure 8. Bottom View of ADSxx53EVM Rev C with microSD Card Installed
The microSD card(s) is formatted from the factory with the necessary firmware files for the simple capture
card controller board to boot properly. In addition to the simple capture card firmware files ('app' and 'MLO'
files), the microSD card(s) contain the ADSxx53EVM-PDK software installation files inside the ADS835x
EVM V#.#.# folder. refers to the installation software version number, and increments with
software installer releases.
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5.2.2
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Verify Jumpers are in the Factory-Default Position and Connect the Hardware
The ADSxx53EVM-PDK includes both the ADSxx53EVM and the simple capture card controller board;
however, the devices are shipped unconnected. Follow these steps to verify that ADSxx53EVM-PDK kit is
configured and connected properly.
Step 1. Verify the microSD card is installed on the back of the simple capture card board; see
Figure 7.
Step 2. Verify the ADSxx53EVM jumpers are configured; see Figure 6.
Step 3. Connect the ADSxx53EVM board to the simple capture card controller board as Figure 9
shows.
Figure 9. Connecting the ADSxx53EVM Board to the Simple Capture Card Controller Board
Step 4.
Step 5.
Connect the simple capture card controller board to the PC through the micro USB cable.
Verify that LED D5 Power Good indicator is illuminated. Wait approximately ten seconds and
verify that diode D2 blinks, indicating that USB communication with the host PC is functioning
properly. Figure 10 shows the location of the LED indicators in the simple capture card
controller board.
Figure 10. LED Indicators on a Simple Capture Card Board
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5.2.3
Install the ADSxx53EVM-PDK software
The ADS835x EVM V#.#.# software needs to be installed on the PC. This software supports the
ADSxx53EVM-PDK. The user must have Administrator privileges on the PC to be able to install the EVM
software. The following steps list the directions to install the software.
1. Open Windows explorer and find the microSD memory card in the browser as a storage device.
2. Navigate to the ...\ADS835x EVM Vx.x.x\Volume\ folder.
3. Run the installer by right-clicking the setup.exe and selecting Run as Administrator. This action installs
the EVM GUI software and the required simple capture card device driver components.
4. After the installer begins, a welcome screen displays. Click Next to continue.
5. A prompt appears with the destination directory; select the default directory under: ...\Program
Files(x86)\Texas Instruments\ads835xevm\, as shown in Figure 11.
Figure 11. Welcome Screen and Destination Directory Screens
6. One or more software license agreements appear. Select I Accept the License Agreement and click
Next.
7. The Start Installation screen appears. Click Next, as shown in Figure 12.
Figure 12. License Agreement and Start Installation Screens
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8. A progress bar appears; this step takes a few minutes.
9. The progress bar is followed by an installation complete notice, as shown in Figure 13.
Figure 13. Progress Bar and Installation Complete Screens
5.2.4
Simple Capture Card Device Driver Installation
During installation of the simple capture card device driver, a prompt may appear with the Windows
security message shown in Figure 14. Select Install this driver software anyway to install the driver
required for proper operation of the software. The drivers contained within the installers are safe for
installation to your system.
Figure 14. Windows 7 Driver Installation Warning
NOTE: Driver installation prompts do not appear if the simple capture card device driver has been
installed on your system previously.
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Follow these procedures to install the simple capture card device driver, if prompted.
Step 1. Immediately after the ADS835x EVM software installation is complete, prompts appear to
install the simple capture card device driver, as shown in Figure 15 and Figure 16
Step 2. A computer restart may be required to finish the software installation. If prompted, restart the
PC to complete the installation.
Figure 15. Simple Capture Card Device Driver Installation
Figure 16. Simple Capture Card Device Driver Completion
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ADSxx53EVM-PDK Kit Operation
6
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ADSxx53EVM-PDK Kit Operation
This section describes how to use ADSxx53EVM-PDK and the ADSxx53EVM software to configure the
EVM and acquire data.
6.1
About the Simple Capture Card Controller Board
The simple capture card controller board provides the USB interface between the PC and the
ADSxx53EVM. The controller board is designed around the AM335x processor, a USB 2.0 high-speed
capability, 32-bit ARM core. The simple capture card controller board incorporates an onboard FPGA
subsystem and 256 MB of onboard DDR SRAM memory.
The simple capture card controller board is not sold as a development board, and it is not available
separately. TI cannot offer support for the simple capture card controller board except as part of this EVM
kit.
6.2
Loading the ADSxx53EVM-PDK Software
The ADS835x EVM software (this software also supports the ADSxx53EVM-PDK) provides control over
the settings of the ADSxx53. Adjust the ADSxx53EVM settings when the EVM is not acquiring data.
During acquisition, all controls are disabled and settings cannot be changed.
Settings on the ADSxx53EVM correspond to settings described in the ADSxx53 product data sheet
(available for download at http://www.ti.com); see the product data sheet for details.
To load the ADS835x EVM software, follow these steps:
Step 1. Make sure the EVM kit is configured and powered up as explained in Section 5.2.2 and
Figure 6.
Step 2. Start the ADS835x EVM software. Go to Start → All Programs →Texas Instruments →
ADS835x EVM and click ADS835x EVM to load the software.
Step 3. Verify that the software detects the ADSxx53EVM. The GUI identifies the EVM hardware that
is connected to the controller board and displays either Loading the ADSxx53evm Settings or
Loading the ADS7854evm Settings. After the settings are loaded, ADSxx53EVM GUI or
ADS7854 EVM GUI displays at the top of the GUI screen, as shown in Figure 17.
Figure 17. GUI Display Prompt
18
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6.3
ADSxx53EVM Settings
Configure the ADSxx53EVM with different settings for evaluation. In order to configure the device settings,
follow these steps:
1. Load the ADSxx53 EVM settings page in the GUI. Hover the cursor over the red arrow at the leftcenter side of the GUI screen; a menu with different GUI pages appears. Click on ADSxx53 EVM
Settings, as shown in Figure 18.
Figure 18. Open the ADSxx53 EVM Settings Page
2. On the ADSxx53 EVM Settings page, find the Internal Reference [CFR, Bit[6] ] button to select the
internal or external onboard reference sources. Jumpers JP5 and JP6 must be installed when selecting
the external REF5025 (U5) onboard reference. Make sure to uninstall jumpers JP5 and JP6 when
selecting the ADSxx53 device internal reference. The GUI displays the appropriate reference jumper
settings, as shown in Figure 19.
Figure 19. Selecting the External Onboard Reference or the ADSxx53 Internal Dual Reference
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3. The ADSxx53 device incorporates two internal programmable 2.5-V reference sources. When selecting
the dual, internal programmable reference, independently change the voltages at VREF_A and
VREF_B by writing to user-programmable registers REFDAC_A and REFDAC_B. The Vref Value-ADC
A and Vref Value-ADC B control panels contain the REFDAC_x register settings. The reference
voltage can be programmed in the range of 2.5 V to 2.0 V by entering the REFDAC_x register value in
the control panel and clicking the Write REFDAC_x button. Figure 20 shows the internal reference Vref
Value-ADC x control panels on the ADSxx53EVM Settings page of the GUI.
Figure 20. Programming the REFDAC Registers in the ADSxx53EVM
4. Scroll down in the ADSxx53EVM Settings page and find the Input Range Selection [CFR, Bit[9]] button
to select the 0 to Vref range mode or the 0 to 2 × Vref range mode. Install jumpers JP3 and JP4 when
selecting the 0 to Vref range. Uninstall jumpers JP3 and JP4 when selecting the 0 to 2 × Vref range .
The GUI displays the appropriate JP3 and JP4 jumper settings, as shown in Figure 21.
Figure 21. Selecting 0 to Vref Range or 0 to 2 × Vref Range
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5. Scroll down in the ADSxx53EVM Settings page and find the ADSxx53 Analog Inputs connections
descriptions on the GUI. The ADSxx53 device can be programmed to support single-ended inputs or
pseudo-differential inputs by setting the INM_SEL [CFR, Bit[7]] button. Configure jumpers JP7 and JP8
on the ADSxx53EVM to connect the negative inputs of the ADSxx53 to GND to support single-ended
configuration, or to FSR / 2 to support pseudo-diffential inputs. Figure 22 shows jumpers JP7 and JP8
on the ADSxx53EVM Settings page of the GUI.
Figure 22. Single-Ended or Pseudo-Differential Jumper Settings Description on the GUI
6. The ADSxx53EVM can be driven with a signal generator producing a bipolar source signal centered on
GND, or a unipolar signal centered at +FSR / 2. Install jumpers JP9 and JP10 when supporting a
bipolar signal centered at GND. Remove jumpers JP9 and JP10 when supporting a unipolar signal
source signal centered at FSR / 2. Figure 23 shows jumpers JP9 and JP10 on the ADSxx53EVM
Settings page of the GUI.
Figure 23. Bipolar or Unipolar Signal Jumper Settings Description on the GUI
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ADSxx53EVM-PDK Kit Operation
6.4
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Device Registers
In addition to the ADSxx53EVM Settings page, the GUI also allows access to the SCLK frequency settings
and the ADSxx53 device register settings on the Device Registers page of the GUI. Use the EVM software
to change the following register settings of the configuration register (CFR):
• INPUT_RANGE (CFR.B9)
• INM_SEL (CFR.B7)
• REF_SEL (CFR.B6)
• STANDBY (CFR.B5)
Use the EVM software to also program the REFDAC register settings. See Section 6.3 or the ADSxx53
device datasheet for more information. Figure 24 shows the Device Registers page of the GUI.
Figure 24. Device Registers Page
6.5
Capturing Data with the ADSxx53EVM-PDK
Access the Data Monitor page in the GUI to monitor data acquired by the ADSxx53. This GUI page
displays the acquired data versus time. To access the Data Monitor page, hover over the red arrow at the
left-center side of the GUI screen; a menu with different GUI pages appears. Click on the Data Monitor
option in the menu, as shown in Figure 25.
Figure 25. Open the Data Monitor Page on the GUI
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Figure 26 shows the Data Monitor page of the EVM GUI. Configure the device sampling rate and capture
settings by using the Capture Settings portion of the Data Monitor page. The change in configuration
settings are executed immediately after pressing the Configure Device button. The following list describes
the different options available on the Data Monitor page.
# of Samples— This option is used to select the number of samples captured in a block.
The number of samples captured in a block are contiguous. The drop-down menu is used to select
a data block in the range of 1024 samples to 1,048,576 samples per channel. This control provides
a drop-down list for values restricted to 2n, where n is an integer.
SCLK— This control sets the clock frequency used by the SPI interface to capture data.
By configuring the SCLK frequency, the data rate of the ADS7853 is configured.
The ADS7853EVM-PDK software supports SCLK frequencies of 34 MHz, 24 MHz, 20 MHz, and
16.2 MHz. These SCLK frequencies correspond to data rates of 1 MSPS, 705.8 kSPS, 588 kSPS,
and 476.5 kSPS, respectively.
The ADS8353EVM-PDK software supports SCLK frequencies of 20 MHz, 16.2 MHz, and 10MHz .
These SCLK frequencies correspond to data rates of 606 kSPS, 490.9 kSPS, and 303.03 kSPS,
respectively
Internal Reference?— Use this button to select the ADSxx53 device internal reference, or the onboard
REF5025 2.5-V external reference.
Program the internal reference settings by navigating into the ADSxx53 EVM Settings GUI page, as
described in Section 6.3 of this document.
2*VREF Mode— This option is used to configure the ADSxx53 to the 0 to 1 × Vref range or the 0 to 2 ×
Vref range.
Make sure to configure jumpers JP3 and JP4 appropriately, depending on the mode of operation.
Figure 26. Data Monitor Page
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ADSxx53EVM-PDK Kit Operation
6.5.1
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Data Collection to Text Files
The Data Monitor page of the GUI allows data to be saved in a tab-delimited text file format that can be
imported into Excel® or other spreadsheet software tools. The text file contains the raw ADC data of both
channel A and channel B in decimal data format. Information such as the device name, date and time, the
sampling frequency, and number of samples of the data record are also stored. In order to save any data
captured by the EVM, click on the Save Data button and specify the file path and file name of the data file,
as shown in Figure 27.
Figure 27. Saving Data to a Text File
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6.6
FFT Analysis
The Performance Analysis page in the GUI performs the fast fourier transform (FFT) of the captured data,
and displays the resulting frequency domain plots of channel A and channel B of the ADSxx53. This page
also calculates key ADC dynamic performance parameters, such as signal-to-noise ratio (SNR), total
harmonic distortion (THD), signal-to-noise and distortion ratio (SINAD) and spurious-free dynamic range
(SFDR).Figure 28 shows the FFT performance analysis display. The FFT calculated parameters are
shown on the right side of the display.
Figure 28. FFT Performance Analysis Page
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ADSxx53EVM-PDK Kit Operation
6.6.1
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FFT Analysis Settings and Controls
Sample Rate (kHz)— This field indicates the sampling frequency of the ADC data (kHz).
Samples (#)— The FFT requires a time domain record with a number of samples that is a power of 2.
The Samples (#) drop-down menu provides a list of values that satisfy this requirement.
Fi Calculated— This field displays the frequency of the largest amplitude input signal computed from the
FFT data, typically the fundamental frequency.
Window— The window function is a mathematical function that reduces the signal to zero at the end
points of the data block.
In applications where coherent sampling cannot be achieved, a window-weighting function can be
applied to the data to minimize spectral leakage. The following opions are available:
• None (no window weighting function applied; use for coherent data)
• Hanning
• Hamming
• Blackman-Harris
• Exact Blackman
• Blackman
• Flat Top
• 4-Term Blackman-Harris
• 7-Term Blackman-Harris
• Low Sidelobe
For a more thorough discussion of windowing, refer to IEEE1241-2000.
Harmonics— This field sets the number of harmonics that are included in the FFT performance
calculations.
Leakage Bins— These fields provide for the removal of the unwanted frequency bins that may be the
result of noncoherent data sampling.
Set the Fundamental Leakage Bins and Harmonic Leakage Bins fields to the number of adjacent
bins on either side of the fundamental or harmonic frequencies to include the main frequency
power. The DC Leakage Bins field allows the number of frequency bins that are a result of the dc
portion of the measurement to be excluded from the calculations.
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6.7
Histogram Analysis
Histogram testing is commonly used when characterizing ADCs. A histogram is merely a count of the
number of times a code has occurred in a particular data set. The Histogram Analysis page of the GUI
creates a histogram of the data of the acquired data set and displays it. Figure 29 shows the Histogram
Analysis page of the GUI.
Figure 29. Histogram Analysis
The DC Analysis table shown in Figure 29 displays several parameters of the captured data set:
• The StDev column displays the standard deviation of the data set. This value is equivalent to the RMS
noise of the signal when analyzing a dc data set.
• The Codes(pp) column shows the peak-to-peak spread of the codes in the data set; for a dc data set,
this range would be the peak-to-peak noise.
• The Mean column displays the average value of the data set.
• The ENOB(StDev) column displays the effective number of bits of the converter, as calculated from the
standard deviation or RMS noise.
• The Noise Free Bits column displays the effective bits of the converter when calculated using the peakto-peak noise.
6.8
Troubleshooting
If the ADSxx53EVM software stops responding while the ADSxx53EVM-PDK is connected, unplug the
USB cable from the EVM, unload the ADSxx53EVM-PDK software, reconnect the ADSxx53EVM-PDK to
the PC, and reload the ADSxx53EVM software.
When initially setting up the EVM, the software detects the EVM hardware, and loads the appropriate
hardware settings. If the EVM hardware is not detected, the GUI defaults to the Capture Mode: Software
Debug mode of operation using a preloaded captured data file for demonstration purposes.
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While using the EVM-PDK hardware for data acquisition, keep the GUI in the Capture Mode: SDCC
interface mode of operation. The GUI indicates the selected mode of operation on the top-right corner of
the GUI display. In order to select the hardware interface mode of operation, navigate to the GUI Settings
page and select the SDCC Interface option on the Capture Mode drop-down menu, as shown in Figure 30
and Figure 31.
Figure 30. Open the GUI Settings Page
Figure 31. Set Capture Mode to SDCC Interface While Using the EVM Hardware
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Bill of Materials, PCB Layout, and Schematics
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7
Bill of Materials, PCB Layout, and Schematics
Section 7.1 lists the bill of materials. Section 7.2 shows the printed circuit board (PCB) layout for the
ADSxx53EVM. The schematics for the ADSxx53EVM are appended to the end of this user's guide.
7.1
Bill of Materials
NOTE: All components should be compliant with the European Union Restriction on Use of
Hazardous Substances (RoHS) Directive. Some part numbers may be either leaded or
RoHS. Verify that purchased components are RoHS-compliant. (For more information about
TI's position on RoHS compliance, see the http://www.ti.com.)
Table 7. ADSxx53EVM Bill of Materials
Item No.
Qty
Ref Des
Description
Vendor
Part Number
Murata
GRM21BR61C106KE15L
Murata
GRM188R70J105KA01D
1
11
C1, C20, C21, C39,
CAP, CERM, 10uF, 16V, +/-10%, X5R,
C41, C42, C43,
0805
C44, C45, C46, C54
2
11
C2, C5, C9, C10,
CAP, CERM, 1uF, 6.3V, +/-10%, X7R,
C12, C13, C14,
0603
C15, C28, C30, C40
3
0
C3, C4, C18, C19,
C22, C23
Not installed
N/A
N/A
4
0
R1, R2, R5, R8,
R19, R30
Not installed
N/A
N/A
5
4
C6, C26, C27, C51
CAP, CERM, 10uF, 6.3V, +/-20%, X5R,
0603
TDK
C1608X5R0J106M
10
C7, C8, C11, C16,
C17, C29, C31,
C48, C52, C53
CAP, CERM, 0.1uF, 16V, +/-5%, X7R,
0603
AVX
0603YC104JAT2A
TDK
C2012C0G1H822J060AA
6
7
2
C24, C25
CAP CER 8200PF 50V 5% NP0 0805
8
2
C47, C50
CAP, CERM, 2.2uF, 16V, +/-10%, X5R,
0603
Murata
GRM188R61C225KE15D
9
1
C49
CAP, CERM, 0.22uF, 16V, +/-10%, X5R,
0603
TDK
GRM188R61C224KA88D
10
1
D1
DIODE ZENER 5.9V 250MW SOT23
NXP
Semiconductors
PLVA659A.215
11
2
J1, J2
Connector, TH, SMA
TE Connectivity
142-0701-201
On Shore
Technology Inc
ED555/2DS
12
1
J5
2 Terminal Block 3.5MM 2POS PCB
13
1
J6
SAMTEC, dual-row, right-angle, female,
latching
SAMTEC
ERF8-025-01-L-D-RA-L-TR
14
1
J7
Note: Connector Not Installed on PWB
Rev. A
MOLEX connector for microSD card
Molex Inc
Note: Connector Not Installed on
PWB Rev. A
MOLEX 502570-0893
15
9
JP1, JP2, JP3, JP4,
JP5, JP6, JP9,
JP10, JP11
Header, TH, 100mil, 2x1, Gold plated,
230 mil above insulator
SAMTEC
TSW-102-07-G-S
16
3
JP7, JP8, JP12
Header, TH, 100mil, 3x1, Gold plated,
230 mil above insulator
SAMTEC
TSW-103-07-G-S
17
1
R3
RES, 0.22 ohm, 1%, 0.1W, 0603
Panasonic
Electronic
Components
ERJ-3RQFR22V
18
9
R4, R14, R16, R36,
R37, R44, R45,
R89, R90
RES, 0 ohm, 5%, 0.1W, 0603
Vishay Dale
CRCW06030000Z0EA
19
2
RES, 100 ohm, 1%, 0.1W, 0603
Yageo
CRCW0603100RFKEA
R9, R15, R39, R40,
RES, 47.0 ohm, 1%, 0.1W, 0603
R41, R42, R43, R31
Yageo
RC0603FR-0747RL
Susumu
RG1608P-102-B-T5
RES, 1.00k ohm, 1%, 0.1W, 0603
Vishay Dale
CRCW06031K00FKEA
R21, R22, R23, R24 RES, 20.0k ohm, 1%, 0.1W, 0603
Vishay Dale
CRCW060320K0FKEA
20
8
21
8
22
2
23
4
R6, R7
R10, R12, R17,
R18, R20, R25,
R46, R47
R11, R13
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Bill of Materials, PCB Layout, and Schematics
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Table 7. ADSxx53EVM Bill of Materials (continued)
Item No.
Qty
Ref Des
Vendor
Part Number
24
2
R26, R27
RES, 1.00 ohm, 1%, 0.1W, 0603
Vishay Dale
CRCW06031R00FKEA
25
2
R28, R29
RES, 0.1 ohm, 1%, 0.1W, 0603
Panasonic
Electronic
Components
ERJ-3RSFR10V
26
4
R38, R86
RES, 100k ohm, 5%, 0.1W, 0603
Vishay Dale
CRCW0603100KJNEA
28
6
R70, R71, R72,
R73, R74, R75
RES, 10k ohm, 5%, 0.063W, 0402
Vishay Dale
CRCW040210K0JNED
29
1
R76
RES, 10.0k ohm, 1%, 0.1W, 0603
Vishay Dale
CRCW060310K0FKEA
30
2
R80, R84
RES, 0 ohm, 5%, 0.125W, 0805
Vishay Dale
CRCW08050000Z0EA
31
0
R83, R87, R88
N/A
N/A
Texas Instruments
ADS8353IPWR or ADS7853IPWR
30
Description
Not installed
32
1
U1
Dual, 600kSPS or 1-MSPS,16-bit or 14Bit Simultaneous Sampling ADC
33
1
U2
High-Speed, Single-Supply, Rail-to-Rail
OPA
Texas Instruments
OPA2350EA
34
2
U3, U4
Very Low-Power, Rail-to-Rail Out,
Negative Rail In, VFB Op Amp 205MHz
Texas Instruments
OPA2836IDGS
35
1
U5
Low Noise, Low Drift, Precision Voltage
Reference
Texas Instruments
REF5025IDGK
36
2
U6, U10
N/A
N/A
Not installed
37
1
U7
Atmel I2C Compatible (2-Wire) Serial
EEPROM
Atmel
38
1
U8
36-V, 1-A, 4.17uVRMS RF LDO Voltage
Regulator
Texas Instruments
39
1
U9
60mA, 5.5V, Buck/Boost Charge Pump
Texas Instruments
REG71055DDC
40
1
U14
NanoPower Supervisory Circuit
Texas Instruments
TPS3836E18DBVT
41
2
U15, U16
Low Noise, Low Quiescent Current,
Precision OPA
Texas Instruments
OPA376AIDBVT
42
9
N/A
Conn Shunt, Pitch 0.100"; Height 0.240" ,
Gold Plated
SAMTEC
SNT-100-BK-G
43
1
TP0
TEST POINT PC MINI .040"D BLACK
Keystone
Elerctronics
5001
44
4
TP7, TP8, TP9,
TP10
Note: These Test Points only available
on PWB Rev. C
TEST POINT PC MINI .040"D BLACK
Keystone
Elerctronics
Note: These Test Points only
available on PWB Rev. C
5001
45
0
TP1, TP2, TP3,
TP4, TP5, TP6
Not Installed
N/A
N/A
46
2
N/A
BUMPON CYLINDRICAL .375X.135 BLK
3M
SJ61A8
ADS8353EVM-PDK and ADS7853EVM-PDK
Copyright © 2014, Texas Instruments Incorporated
AT24C02C-XHM
TPS7A4700RGW
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7.2
PCB Layout
Figure 32 through Figure 35 show the PCB layout for the ADSxx53EVM.
NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing ADSxx53EVM PCBs.
Figure 32. ADSxx53EVM PCB: Top Layer
Figure 33. ADSxx53EVM PCB: Ground Layer
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Figure 34. ADSxx53EVM PCB: Power Layer
Figure 35. ADSxx53EVM PCB: Bottom Layer
7.3
Schematics
The schematics for the ADSxx53EVM are appended to the end of this user's guide.
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Revision History
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Revision History
Changes from Original (June 2014) to A Revision ......................................................................................................... Page
•
•
•
•
•
•
•
Added ADS8353EVM-PDK to document ............................................................................................... 1
Changed ADS7853 to ADSxx53 where applicable throughout document ......................................................... 1
Changed SDCC controller to simple capture card controller throughout document .............................................. 4
Changed ADSxx53EVM revision C requirement to two microSD cards in Section 5.2 ........................................ 12
Added Figure 8 .......................................................................................................................... 13
Added SCLK frequencies for the ADS8353EVM in Section 6.5 .................................................................. 22
Changed J7 ,TP7,TP8, TP9, TP10 rows (item no. 14 and 44) in Table 7 ....................................................... 29
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SBAU210A – June 2014 – Revised August 2014
Submit Documentation Feedback
Revision History
Copyright © 2014, Texas Instruments Incorporated
33
1
2
3
4
5
6
COR20
R20
PIR2001
142-0701-201
COR1
R1
PIR101
NI
PIJP102 PIJP10
COC29
C29
PIC2902
0.1uF COC16
C16
PIC2901
PIC1602
PIR2 02
COR22
R22
20k
COC28
C28
1µF
4
PIU1504
2
PIU302
-
COU15
U15
COR10
R10
1
PIU1501
-
PIU1502
PIR1001
PIC1202
PIR4601
COC12
C12
/PD
PIU304
COU3A
U3A
2
1
COR32
R32
PIR3201
COR44
R44
PIR4402
PIR3202
PIC2401
PIC2402
PIR1101
COR9
R9
PIR901
PIU307
PIC1301
PIC1302
47.0
COC7
C7 PIC701
NI
PIC702
7
PIR1102
1.00k
PIR902
-
COR33
R33
COR26
R26
9
PIU309
PIR2601
PIR3301
1.00
+
PIC2 01
PIC2 02
OPA2836
COC13
C13
1uF
PIR3302
1µF
3
PIU503
4
PIU504
6
VOUT PIU506
TEMP
GND
TRIM/NR PIU505
REF5025IDGK
GND
PIR402
COR3
R3
PIC501
1µF
PIR601
COR4
R4
0.22
PIC601
PIC602
PIR602
100
0
PIR301
COC5
C5
PIC502
COR6
R6
PIR302
PIR401
PIR502
COC6
C6
10µF
PIC901
PIC902
3
PIU203
COR14
R14
COU2A
U2A
PIR1401
1
PIU201
+
PIU204
COC9
C9
PIR2802
PIJP502 PIJ501
COR21
R21
PIR2101
OPA2350EA
NLREF0AINA
REF-AINA
PIR2102
1uF
1
PIU101
AINP-A
COR28
R28
0.1
2
PIU102
PIRC280 1
COC20
C20
PIC20 2 10µF
20.0k
COJP5
JP5
GND
PIR501
PIR1901
PIR1502
GND
47.0
COR23
R23
PIR2301
GND
COC8
C8
100
PIC801
-
COR16
R16
7
PIU207
5
PIR702 PIU205 +
PIC10 1
PIC10 2
8
PIU108
PIR2901
COU2B
U2B
PIR1601
PIR1602
0
OPA2350EA
COC10
C10
C
142-0701-201
PIJP602 PIJ601
PIR1801
AVDD
NI
PIJP20 PIJP201
GND
GND
GND
REF-AINB
PIC1802
PIC1801
NI
PIR2401
AVDD
6
5
COU16
U16
COTP4
TP4
PO\C\S
CS
GND
POSDI
SDI
9
PIU109
C30
COC30
PIR3802
COR38
R38
100k
C
PIR3801
PITP0 1
COC26
C26
10µF
COTP0
TP0
1
PIU1601
-
PIU1602
OPA376DBV
R12
COR12
PIR1201
7
PIR1202
1.00k
PIU407
PIR4702
GND
GND
+
R47
COR47
1.00k
PIR4701
1µF
GND
9
PIJP10 2 PIJP10 1
PIC1401
C14
COC14
PIC1402 1µF
GND
R34
COR34
GND
PIR3401
GND
AVDD
PIR3402
10.0
0.1µF COC17
C17
PIC1702
PIC2501
PIC1701
COC25
C25
2
PIU402 -
R13
COR13
3
PIR1302
1.00k
PIC1501
PIC1502
PIU401
1
+
C15
COC15
1µF
COR35
R35
PIU405
PIU401
PIU403
PIU40
OPA2836
PIR3501
R27
COR27
PIR2701
1.00
4
PIR1301
V-
D
8200pFPIC2502
/PD
5
PIR3502
D
10.0
PIR2702
PIC2301
PIC2302
C23
COC23
NI
PIJ803 PIJP802 PIJP801
3
2
1
10
V+
U4A
COU4A
GND
GND
GND
GND
JP8
COJP8
GND
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
1
PITP401
PIU409
JP10
COJP10
JP4
COJP4
DVDD
PITP101
47.0
OPA2836
PIU406
8
PIU408
-
2
1
PIJP402 PIJ401
PIC30 1
PIC30 2
47.0
PIR4301
GND
2
1
COR24
R24
20k
3
PIU1603 +
4
PIU1604
PIU1605
2
PIR2402
COR43
R43
PIR4302
47.0
POSDO0A
SDO_A
PIU10 3
U4B
COU4B
V-
GND
PIR1802
1.00k
/PD
0.1µF
COJP2
JP2
10
SDI/GND PIU1010
PIR3601
PIC2601
PIC2602
1.00k
COC18
C18
C31
COC31
PIR201
GND
PIR4202
0
PIR2502
PIC3102 PIC3101
V+
R2
COR2
NI
2
1
2
3
4
5
PIR202
C4
COC4
PIR4102
COR42
R42
PIR4201
R36
COR36
PIR2501
1
PIC402
COR41
R41
PIR4101
11
CS PIU1011
COTP3
TP3
PIR3602
COR25
R25
PIR801
COR18
R18
PIC401
12
SCLK PIU1012
COTP2
TP2
PITP201
SCLK
COTP1 POSCLK
TP1
PITP301
4
Y PIU1004
DVDD
COR8
R8
PIR802
PIJ201
PIJ20 PIJ203 PIJ204 PIJ205
2
PIU1002 A
1uF
NI
COJ2
J2
47.0
PIR4002
ADSxx53IPWR
JP6
COJP6
GND
ANIP-B
COR40
R40
PIR4001
B
COU10
U10
Not Install
2
1
COR7
R7
PIR701
7
PIU107
ANIM-B
COR29
R29
0.1
20.0k
NI
PIC802
6
PIU206
PIR2902
NLREF0AINB
REF-AINB
PIR2302
6
PIU106
REFIO-B
VCC
PIU10 5
15
PIU1015
13
SDO-A PIU1013
PIU105 REFGND-B
COC21
C21
10µF
GND
4
5
PIC2101
PIC2102
NI
COR15
R15
PIR1501
GND
16
AVDD PIU1016
14
SDO-B PIU1014
PIU104 REFGND-A
COR19
R19
GND
NI
AINM-A
0
PIR4501
DVDD
3
PIU103 REFIO-A
PIR1902
COR5
R5
GND
PIR1402
0
2
1
PIU208
-
V-
COC2
C2
PIC202
GNDPIU202
2
7
NC PIU507
COR45
R45
PIR4502
47.0
PIR3902
COU1
U1
4
PIC201
POSDO0B
SDO_B
GND
COR39
R39
PIR3901
GND
COJP7
JP7
GND
8
DNC PIU508
8
VIN
GND
V+
2
PIU502
PIC1101
COTP5
TP5
GND
PIR3701
PIC2701
COC27
C27
PIC2702 10µF
PIJ703 PIJP702 PIJP701
PITP501
4
PIU604
PIU603
0
COC22
C22
NI
Y
5
PIC1102
A
COR37
R37
COC11 AVDD
0.1uF C11
COU5
U5
2
PIU602
PIR3702
10.0
PIR2602
COU6
U6
Not Install
VCC
PIU605
AVDD
3
2
1
8
PIU308
COC24
C24
8200pF
AVDD
/PD
6
PIU306
0
PIR4401
DVDD
GND
COR11
R11
DNC
A
10.0
GND
1
PIU501
PITP801
COTP8
TP8
OPA2836
GND
COU3B
U3B
AVDD
COTP10
TP10
GND
AVDD
COTP7
TP7
B
PITP10 1
5
PIU305
GND
COJP9
JP9
PITP701
COTP9
TP9
1uF
PIJP902 PIJP901
GND
COJP3
JP3
PIU301
1
PIU301
+
PIR4602 PIC1201
COR46
R46
1.00k
2
1
PIJ302 PIJP301
3
PIU303
PIR1002
1.00k
OPA376DBV
2
PIR2 01
PIC2801
PIC2802
3
PIU1503
+
V+
GND
PIU150
5
REF-AINA
V-
GND
10
V+
GND
GND
GND
PITP901
Do Not Install
4
COJP1
JP1
GND
DVDD
PIC1601
5
NI
AVDD
3
COC3
C3
PIC1901
NI
1.00k
AVDD
0.1µF
A
COC19
C19
PIC1902
PIR1702
3
PIR102
2
1
2
3
4
5
PIJ102 PIJ103 PIJ104 PIJ105
PIR1701
PIC301
PIC302
PIR2002
1.00k
COR17
R17
1
PIJ101
V-
COJ1
J1
2
3
4
Number: XX####
Rev: C
SVN Rev: Not in version control
Drawn By: Luis Chioye
Engineer: Luis Chioye
5
Designed for: Public Release
Mod. Date: 6/30/2014
Project Title: ADS8353EVM
Sheet Title:
Assembly Variant: Variant name not interpreted Sheet: 1 of 1
File: Main_ADS8353EVM_Revc.SchDoc
Size: B
Contact: http://www.ti.com/support
6
http://www.ti.com
?Texas Instruments
2014
1
2
3
+5_SDCC
4
5
6
+3.3V SDCC Digital Supply
Unreg_5V
VOUT
1
PIU901
COR84
R84
PIR8402
PIC4501
PIC4502
COC45
C45
10µF
PIC4601
PIC4602
PIC4701
PIC4702
COC46
C46
10µF
3
PIU903
COC47
C47
2.2µF
ENABLE
2
GND PIU902
PIC50 1
PIC50 2
PIR8401
PIC3901
0
PIC3902
COC50
C50
2.2µF
COU9
U9
REG71055DDC
16
PIU8016
IN
15
PIU8015
IN
COR83
+5V_SDCC PIR8302R83 PIR8301
NI
COC39
C39
GND
COC40
C40
1µF
GND
17
18
0P1V
7
GND PIU807
2
PIU1402
GND
3
PIU1403
MR
PIC4201
PIC420
COC41
C41
10µF
COC42
C42
10µF
PIC4301
PIC4302
COC43
C43
10µF
PIC4 01
PIC4 02
PIR8602
100k
COR86
R86
COC44
C44
10µF
GND
6P4V2
6P4V1
GND
21
PAD PIU8021
NLUnreg05V
Unreg_5V
NLEVMSDCLK
EVMSDCLK
NLEVMSDDATA1
EVMSDDATA1
NLEVMSDDATA3
EVMSDDATA3
4
5
VDD PIU1405
5
PIU80 PIU806 PIU805 PIU804
6
CT
8
1
PIU1401
3P2V
COU14
U14
9
PIU809
0P8V
1P6V
+5.5V Charge Pump
PIC4101
PIC4102
0P2V
10
PIU8010 0P4V
PIC4801 PIC4802
0.1µF
ID_SDA
DVDD
20
OUT PIU8020
3
SENSE PIU803
11
COC48
C48
TPS7A4700RGW
1
OUT PIU801
GND
NI
GND
14
PIU8014
NR
12
PIU8012
PIR8702
COU8
U8
13
PIU8013
EN
PIU8011
GND
GND
PIR8601
10µF
PIC40 1
PIC40 2
19
2
PIU802 PIU8019 PIU8018 PIU8017
NC
VIN
COR87
R87
PIR8701
NC
5
PIU905
51
GND PIJ6051
PIU906
NC
4
0.22µF
NC
PIR9102
A
PIU904
NI
PIC4901
6
COR91
R91
PIR80 2
COJ6
J6
COC49
C49
PIC4902
PIR9101
COR80
R80
0
CP+
PIR80 1
CP-
NLDVDD
DVDD
4
RESET PIU1404
PIR90 2
TPS3836DBV
5.2V
COR90
R90
GND
0
B
COR88
R88
Enable_Pow
PIR8801
PIR90 1
PIR8802
1
PIJP1101
2
PIJP1102
PIR8902
2
2 PIJ602
4
4 PIJ604
6
6 PIJ606
8
PIJ608
8
10
10 PIJ6010
12
12 PIJ6012
14
14 PIJ6014
16
16 PIJ6016
18
18 PIJ6018
20
20 PIJ6020
22
PIJ6022
22
24
24 PIJ6024
26
26 PIJ6026
28
28 PIJ6028
30
30 PIJ6030
32
32 PIJ6032
34
34 PIJ6034
36
PIJ6036
36
38
38 PIJ6038
40
40 PIJ6040
42
42 PIJ6042
44
44 PIJ6044
46
46 PIJ6046
48
48 PIJ6048
50
PIJ6050
50
GND
EVM_Present~
A
GND
NLID0SCL
ID_SCL
NL05V0SDCC
+5V_SDCC
COTP6
TP6
PI+5_SDCC
TP601
NLEnable0Pow
Enable_Pow
PO\C\S
CS
POSCLK
SCLK
POSDI
SDI
POSDO0A
SDO_A
POSDO0B
SDO_B
EVMSDCMD
NLEVMSDDATA0
EVMSDDATA0
NLEVMSDDATA2
EVMSDDATA2
GND
COR89
R89
0
ERF8-025-01-L-D-RA-L-TR
B
PIR8901
COJP11
JP11
NI
1
1
3
PIJ603
3
5
PIJ605
5
7
PIJ607
7
9
PIJ609 9
11
PIJ6011
11
13
PIJ6013
13
15
PIJ6015
15
17
PIJ6017
17
19
PIJ6019 19
21
PIJ6021
21
23
PIJ6023 23
25
PIJ6025
25
27
PIJ6027
27
29
PIJ6029
29
31
PIJ6031
31
33
PIJ6033 33
35
PIJ6035
35
37
PIJ6037 37
39
PIJ6039
39
41
PIJ6041
41
43
PIJ6043
43
45
PIJ6045
45
47
PIJ6047 47
49
PIJ6049
49
PIJ601
Regulated AVDD
GND
AVDD
3
PIJP1203
2
PIJP1202
GND
PIC101
PIC102
Do Not Install
1
PIJP1201
COC1
C1
10µF
COJP12
JP12
External AVDD
NLEVMSDCMD
EVMSDCMD
GND
ED555/2DS
COJ5
J5
1
PIJ501
2
PIJ502
3
PID103
COD1
D1
PLVA659A.215
NC 5.6V
COC54
C54
10µF
1
PID10
PID102
2
PIC5401
PIC5402
C
C
DVDD
GND
COR76
R76
10k R75
10k R74
10k R73
PIR710
10k R72
PIR70 1
10k R71
10k R70
COR70PIR70 2 COR71PIR7102 COR72PIR7202 COR73PIR7302 COR74PIR7402 COR75PIR7502
PIC510
PIC5102
COC51
C51
10µF
PIC5201
PIC5202
PIR7601
PIR7602
10.0k
COC52
C52
0.1µF
DVDD
COR30
R30
PIR3001
PIR7201 PIR7301 PIR7401 PIR7501
NI
J7
COJ7
GND
1
PIJ701
2
PIJ702
3
PIJ703
4
PIJ704
5
PIJ705
6
PIJ706
7
PIJ707
8
PIJ708
EVMSDDATA2
EVMSDDATA3
EVMSDCMD
EVMSDCLK
EVMSDDATA0
EVMSDDATA1
9
GND PIJ709
10
GND1 PIJ7010
11
CD PIJ7011
12
GND2 PIJ7012
13
GND3 PIJ7013
14
GND4 PIJ7014
DAT2
CD/DAT3
CMD
VDD
CLOCK
VSS
DAT0
DAT1
PIR3002
C53
COC53
0.1µF
COU7
U7
R31
COR31
PIR3101
GND
PIC5301
PIC5302
1
PIR3102
PIU701
47.0
2
PIU702
3
PIU703
4
PIU704
microSD
A0
A1
VCC
8
PIU708
GND
7
WP PIU707
ID_SCL
6
A2
SCL PIU706
VSS
5
SDA PIU705
NLID0SDA
ID_SDA
AT24C02C-XHM
MOLEX 502570-0893
GND
GND
GND
D
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
1
2
3
4
GND
Number: XX####
Rev: C
SVN Rev: Not in version control
Drawn By:
Engineer: Luis Chioye
5
GND
D
Designed for: Public Release
Mod. Date: 6/30/2014
Project Title: ADS8353EVM
Sheet Title:
Assembly Variant: Variant name not interpreted Sheet: 1 of 1
File: Connector_ADS8353EVM_RevC.SchDoc
Size: B
Contact: http://www.ti.com/support
6
http://www.ti.com
© Texas Instruments 2014
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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