ADS8413IRGZTG4

Burr Brown Products from Texas Instruments ADS8413 SLAS490 – OCTOBER 2005 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER FEATURES • • • • • • • • • • • • • • • • • 2-MHz Sample Rate 16-Bit Resolution SNR 92 dB at 10 kHz I/P THD –107 dB at 10 kHz I/P ±1 LSB Typ, ±2 LSB INL Max +0.7/–0.5 LSB Typ, +1.5/–1 LSB DNL Max Unipolar Differential Input Range: –4 V to 4 V Internal Reference Internal Reference Buffer 200-Mbps LVDS Serial Interface Optional 200-MHz Internal Interface Clock 16-/8-Bit Data Frame Zero Latency at Full Speed Power Dissipation: 290 mW at 2 MSPS Nap Mode (125 mW Power Dissipation) Power Down (5 µW) 48-Pin QFN Package APPLICATIONS • • • • Medical Instrumentation HIgh-Speed Data Acquisiton Systems High-Speed Close-Loop Systems Communication DESCRIPTION The ADS8413 is a 16-bit, 2-MSPS, analog-to-digital (A/D) converter with 4-V internal reference. The device includes a capacitor based SAR A/D converter with inherent sample and hold. The ADS8413 also includes a 200-Mbps, LVDS, serial interface. This interface is designed to support daisy chaining or cascading of multiple devices. A selectable 16-/8-bit data frame mode enables the use of a single shift register chip (SN65LVDS152) for converting the data to parallel format. The ADS8413 unipolar differential input range supports a differential input swing of –Vref to +Vref with a common-mode voltage of +Vref/2. The nap feature provides substantial power saving when used at lower conversion rates. The ADS8413 is available in a 48-pin QFN package. High-Speed SAR Converter Family Type/Speed 18-Bit Pseudo-Diff 18-Bit Pseudo-Bipolar, Fully Diff 16-Bit Pseudo-Diff 500 kHz ADS8383 ~ 600 kHz ADS8381 ADS8380 (S) ADS8382 (S) ADS8411 ADS8370 (S) ADS8371 ADS8401/05 ADS8410 (S-LVDS) ADS8412 16-Bit Pseudo-Bipolar, Fully Diff 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS8372 (S) ADS8402/06 ADS7890 (S) ADS8413 (S-LVDS) ADS7891 ADS7881 750 kHZ 1 MHz 1.25 MHz 2 MHz 3 MHz 4 MHz Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated ADS8413 www.ti.com SLAS490 – OCTOBER 2005 + VA AGND + VBD BDGND Core Supply I/O Supply SAR LVDS I/O + IN − IN + CDAC − Comparator CMOS I/O REFIN Clock 4 V Internal Reference Conversion and Control Logic Mode Selection CSTART SYNC_O, CLK_O, SDO SYNC_I, CLK_I, SDI CONVST BUS BUSY RD BUSY CS LAT_Y/N BYTE, MODE_C/D, CLK_I/E, PD, NAP REFOUT ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ±2 ±4 MAXIMUM DIFFERENTIAL LINEARITY (LSB) 1.5/–1 NO MISSING CODES AT RESOLUTION (BIT) 16 PACKAGE TYPE 48 pin QFN 48 pin QFN PACKAGE DESIGNATOR TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C ORDERING INFORMATION ADS8413IBRGZT ADS8413IBRGZR ADS8413IRGZT ADS8413IRGZR TRANSPORT MEDIA QUANTITY 250 2000 250 2000 ADS8413lB RGZ ADS8413l 3/–1 16 RGZ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT +IN to AGND -IN to AGND +VA to AGND +VBD to BDGND Digital input voltage to GND Digital output to GND Operating temperature range Storage temperature range Junction temperature (TJmax) QFN package Lead temperature, soldering (1) Power dissipation θJA Thermal impedance Vapor phase (60 sec) Infrared (15 sec) –0.3 V to +VA + 0.3 V –0.3 V to +VA + 0.3 V –0.3 to 7 V –0.3 to 7 V –0.3 V to (+VBD + 0.3 V) –0.3 V to (+VBD + 0.3 V) –40°C to 85°C –65°C to 150°C 150°C (TJ Max – TA)/ θJA 86°C/W 215°C 220°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted) PARAMETER ANALOG INPUT Full-scale input voltage span Absolute input voltage range Input common-mode voltage range Ci Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution No missing codes Integral linearity (2) ADS8413IB ADS8413I ADS8413IB ADS8413I ADS8413IB ADS8413I ADS8413IB ADS8413I ADS8413IB ADS8413I External reference 16 16 –2 –4.0 –1 –1.0 –1 –3.0 –0.1 –0.15 ±1 ±2 0.7/–0.5 1.5/–0.8 ±0.2 ±1 ±0.03 ±0.1 60 80 2 4.0 1.5 3 1 3.0 0.1 0.15 16 Bits Bits LSB (3) LSB (3) (1) TEST CONDITIONS MIN TYP MAX UNIT +IN – (–IN) +IN –IN –Vref –0.2 –0.2 Vref/2–0.2 Vref/2 25 500 Vref Vref + 0.2 Vref + 0.2 Vref/2+0.2 V V V pF pA INL DNL Differential linearity EO EG CMMR PSRR Offset error Gain error (4) Common-mode rejection ratio Power supply rejection ratio mV External reference With common mode input signal = 200 mVp-p at 1 MHz At FFF0H output code +VBD = 5 V +VBD = 3 V +VBD = 5 V +VBD = 3 V % of FS dB dB SAMPLING DYNAMICS Conversion time 360 391 391 100 100 2.0 20 10 50 50 ns Acquisition time Maximum throughput rate with or without latency Aperture delay Aperture jitter Step response Overvoltage recovery DYNAMIC CHARACTERISTICS ns MHz ns psec ns ns VIN 0.5 dB below FS at 10 kHz THD Total harmonic distortion (5) VIN 0.5 dB below FS at 100 kHz VIN 0.5 dB below FS at 0.5 MHz VIN 0.5 dB below FS at 10 kHz SNR Signal-to-noise ratio VIN 0.5 dB below FS at 100 kHz VIN 0.5 dB below FS at 0.5 MHz VIN 0.5 dB below FS at 10 kHz SINAD Signal-to-noise and distortion VIN 0.5 dB below FS at 100 kHz VIN 0.5 dB below FS at 0.5 MHz VIN 0.5 dB below FS at 10 kHz SFDR Spurious free dynamic range VIN 0.5 dB below FS at 100 kHz VIN 0.5 dB below FS at 0.5 MHz –3 dB Small signal bandwidth –107 –95 –90 92 90 89 92 86 84 –113 –98 –93 37.5 MHz dB dB dB dB (1) (2) (3) (4) (5) Ideal input span; does not include gain or offset error. This is endpoint INL, not best fit. Least significant bit Measured relative to actual measured reference. Calculated on the first nine harmonics of the input frequency. 3 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted) PARAMETER EXTERNAL REFERENCE INPUT Input voltage range, VREF Resistance (6) INTERNAL REFERENCE OUTPUT Start-up time Reference voltage range, Vref Source current Line regulation Drift POWER SUPPLY REQUIREMENTS Power supply voltage +VBD +VA 2.7 4.75 3.3 5 58 +VA = 5 V 290 5.25 5.25 64 320 V mA mW From 95% (+VA), with 1-µF storage capacitor on REFOUT to AGND At room temperature Static load +VA = 4.75 V to 5.25 V IOUT = 0 V 0.6 36 4.080 4.096 25 4.112 10 ms V µA mV PPM/°C To internal reference voltage 3.9 4.096 500 4.2 V kΩ TEST CONDITIONS MIN TYP MAX UNIT Supply current, 2-MHz sample rate +VA Power dissipation, 2-MHz sample rate NAP MODE Supply current POWER DOWN Supply current Powerdown time Powerup time Invalid conversions after power up or reset TEMPERATURE RANGE Operating free air LOGIC FAMILY CMOS VIH VIL VOH VOL DRIVER |VOD(SS)| ∆|VOD(SS)| VOC(SS) ∆|VOC(SS)| VOC(pp) IOS IOZ Steady-state differential output voltage magnitude Change in steady-state differential output voltage magnitude between logic states Steady-state common-mode output voltage Change in steady-state common-mode output voltage between logic states Peak to peak change in common-mode output voltage Short circuit output current High impedance output current VOY or VOZ = 0 V VOD = 0 V VO = 0 V or +VBD –5 See Figure 54 247 RL = 100 Ω, See Figure 52, Figure 53 -50 1.125 –50 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage IIH = 5 µA IIL = 5 µA IOH = 2 TTL loads IOL = 2 TTL loads +VBD –1 –0.3 +VBD – 0.6 0 –40 With 1-µF storage capacitor on REFOUT to AGND +VA +VA 25 mA µA µs ms Numbers °C V V V V 1 10 25 3 2.5 85 +VBD +0.3 0.8 +VBD 0.4 LOGIC FAMILY LVDS (7) 340 454 50 mV 1.2 1.375 50 V mV 50 3 3 150 10 10 5 mA µA (6) (7) Can vary ±20% All min max values ensured by design. 4 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V,+VBD = 5 V or 3.3 V, Vref = 4.096 V, f sample = 2 MHz (unless otherwise noted) PARAMETER RECEIVER VITH+ VITHVIC CI Positive going differential voltage threshold Negative going differential voltage threshold Common mode input voltage Input capacitance –50 0.2 1.2 5 2.2 50 mV V pF TEST CONDITIONS MIN TYP MAX UNIT TIMING REQUIREMENTS TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted) PARAMETER SAMPLING AND CONVERSION RELATED tacq tcnv tw1 tw2 td1 td2 td3 td4 tw3 tw4 td5 td6 Acquisition time Conversion time Pulse duration, CONVST high Pulse duration, CONVST low Delay time, CONVST rising edge to sample start Delay time, CONVST falling edge to conversion start Delay time, CONVST falling edge to busy high +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V +VBD = 5 V 100 100 40 5 5 14 13 8 7 100 391 ns ns ns ns ns ns ns Figure 1, Figure 2 Figure 1, Figure 2 Figure 1 Figure 1, Figure 2 Figure 1 Figure 1, Figure 2 Figure 1, Figure 2 Figure 1, Figure 2 Figure 1, Table 2 Figure 1, Figure 2, Table 2 Figure 1, Table 2 Figure 1, Figure 2, Table 2 Figure 1, Figure 2, Table 2 MIN TYP MAX UNIT REF Delay time, conversion end to busy low Pulse duration, CSTART high ns ns Pulse duration, CSTART low 45 ns Delay time, CSTART rising edge to sample start 7.5 ns Delay time, CSTART falling edge to conversion start +VBD = 3.3 V 7.5 16.5 15.5 ns td7 Delay time, CSTART falling edge to busy high +VBD = 5 V ns I/O RELATED td8 td9 td10 td11 td12 td13 tw5 td14 td15 Delay time, RD falling edge while CS low to BUS_BUSY high Delay time, RD falling edge while CS low to SYNC_O and SDO out of 3-state condition (for device with LAT_Y/N pulled low) +VBD = 3.3 V +VBD = 5 V 16 29 28 22 8 7 6 +VBD = 3.3 V +VBD = 5 V 5.5 + 4*tCLK 5 + 4*tCLK 5 +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V +VBD = 5 V 4*tCLK– 6.5 4*tCLK– 6 1.4 1.3 4*tCLK– 3 4*tCLK– 2.5 9 + tCLK 8.5 + 5*tCLK 8 + 5*tCLK ns ns ns ns ns ns ns ns Figure 5 Figure 5 Figure 6 Figure 6 Figure 6 Figure 5 Figure 11 Figure 5, Figure 6 Figure 7, Figure 12 Delay time, pre_conversion end (point A) to SYNC_O and SDO out of 3-state condition Delay time, pre_conversion end (point A) to BUS_BUSY high Delay time, conversion phase end to SYNC_O high Delay time, RD falling edge while CS low to SYNC_O high Pulse duration, RD low for device in no latency mode Delay time, CLK_O rising edge to data valid Delay time, BUS_BUSY low to SYNC_O high in daisy chain mode indicating receiving device to output the data VBD = 3.3 V +VBD = 5 V ns 5 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 TIMING REQUIREMENTS (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V (unless otherwise noted) PARAMETER MIN TYP MAX UNIT REF Figure 7, Figure 8, Figure 12, Figure 15 Figure 12 Figure 8 Figure 11, Figure 14 Figure 6 Figure 53 Figure 53 td16 tpd1 td17 td18 td19 tr tf Delay time, CLK_O to SDO and SYNC_O 3-state 4 ns Propagation delay time, SYNC_I to SYNC_O in daisy chain mode Delay time, SYNC_O and SDO 3-state to BUS_BUSY low in cascade mode. Delay time, RD rising edge to BUS_BUSY high for device with LAT_Y/N = 1 Delay time, point A indicating clear for bus 3-state release to BUSY falling edge Rise time, differential LVDS output signal Fall time, differential LVDS output signal CLK frequency (serial data rate) 190 +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V +VBD = 5 V 0 11 + 0.5*tCLK 2 8 7 40.5 40 950 950 210 10 10 25 4 335 406 ns ns ns ns ps ps MHz ns µs ms ms ns ns td20 td21 td22 ts1 td23 td24 Delay time, from PD falling edge to SDO 3-state Delay time, from PD falling edge to device powerdown Delay time, from PD rising edge to device powerup Settling time, internal reference after first three conversions Delay time, CONVST falling edge to start of restricted zone for start of data read cycle Delay time, CONVST falling edge to end of restricted zone for start of data read cycle Figure 22, Figure 23 Figure 22, Figure 23 Figure 22, Figure 23 Figure 22 Figure 9 Figure 9 6 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 DEVICE INFORMATION RGZ PACKAGE (TOPVIEW) MODE_C/D LAT_Y/N CONVST 2 REFM REFM CLK_I/E AGND BYTE NAP +VA 12 11 10 9 8 7 6 5 PD 4 3 1 48 47 46 45 44 43 42 41 40 39 38 37 REFIN REFOUT NC +VA AGND +IN −IN AGND +VA +VA AGND AGND CS 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BUS_BUSY RD BUSY BDGND +VBD SYNC_O + SYNC_O − SDO + SDO − CLK_O + CLK_O − +VA (M2+) SDI + (M2−) SDI − CLK_I + CLK_I − AGND +VA AGND (M1 +) SYNC_I + CSTART+ CSTART− NC − No internal connection TERMINAL FUNCTIONS TERMINAL NO. 11, 12 13 14 18 19 NAME REFM REFIN REFOUT +IN –IN I/O ANALOG PINS I I O I I Reference ground. Connect to analog ground plane. Reference (positive) input. Decouple with REFM pin using 0.1-µF bypass capacitor and 1-µF storage capacitor. Internal reference output. Short to REFIN pin when internal reference is used. Do not connect to REFIN pin when external reference is used. Always decouple with AGND using 0.1-µF bypass capacitor. Noninverting analog input channel Inverting analog input channel LVDS I/O PINS (1) 28, 29 (1) CSTART+ CSTART– I Device sample and convert control input. Device enters sample phase with rising edge of CSTART and conversion phase starts with falling edge of CSTART (provided other conditions are satisfied). Set CSTART = 0 when CONVST input is used. DESCRIPTION All LVDS inputs and outputs are differential with signal+ and signal– lines. Whenever only the 'signal' is mentioned it refers to the signal+ line and signal– line is the compliment. For example CLK_O refers to CLK_O+. (M1 −) SYNC_I − AGND 7 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL NO. NAME SYNC_I + SYNC_I– M1+ M1– SDI+ SDI– 32, 33 M2+ M2– CLK_I+ CLK_I– CLK_O– CLK_O+ SDO– SDO+ SYNC_O – SYNC_O + CS CONVST BYTE PD NAP MODE_C/D CLK_I/E LAT_Y/N BUSY RD BUS_BUSY I/O I Dasiy Chain DESCRIPTION Connect to previous device SYNC_O with same polarity, while device is selected to operate in daisy chain mode. 30, 31 Mode 1 (valid in cascade mode only). CLK_O available while M1=1 (LVDS) or M1+ is pulled up to I +VBD and M1– is grounded (AGND). CLK_O o/p goes to 3-state when M1 = 0 (LVDS) or M1+ is Cascade grounded (AGND) and M1– is pulled up to +VBD. Do not allow these pins to float. I Daisy Chain Serial data input. Connect to previous device SDO with same polarity, while device is selected to operate in daisy chain mode. Mode 2 (valid in cascade mode only). Doubles LVDS o/p current while M2 = 1 (LVDS) or M2+ is I pulled up to +VBD and M2– is grounded (AGND). LVDS o/p current is normal (3.4 mA typ) when M2 Cascade = 0 (LVDS) or M2+ is grounded (AGND) and M2 – is pulled up to +VBD. Do not allow these pins to float. I O O O Serial external clock input. Set CLK_I/E (pin 7) = 0 to select external clock source. Serial clock out. Data is latched out on the rising edge of CLK_O and can be captured on the next falling edge. Serial data out. Data is latched out on the rising edge of CLK_O with MSB first format. Synchronizes the data frame. (2) 34, 35 38, 39 40, 41 42, 43 1 2 3 4 5 6 7 8 46 47 48 CMOS I/O PINS I I I I I I I I O I O Chip select, active low signal. All of the LVDS o/p except CLK_O are 3-state if this pin is high. CMOS equivalent of CSTART input. So functionality is the same as the CSTART input. Set CONVST = 0 when the CSTART input is used. Controls the data frame (2) duration. The frame duration is 16 CLKs if BYTE = 0 or 8 CLKs if BYTE = 1. Active low input, acts as device power down. Selects nap mode while high. Device enters nap state at conversion end and remains so until next acquisition phase begins. Selects cascade (MODE_C/D = 1) or daisy chain mode (MODE_C/D = 0). Selects the source of the I/O clock. CLK_I/E = 1 selects internally generated clock with 200-MHz typ frequency. CLK_I/E = 0 selects CLK_I as the I/O clock. Controls the data read with latency (LAT_Y/N = 1) or without latency ((LAT_Y/N = 0). It is essential to set LAT_Y/N = 0 for the first device in daisy chain or cascade. Active high signal, indicates a conversion is in progress. Data read request to the device, also acts as a hand shake signal for daisy chain and cascade operation. Status output. Indicates that the bus is being used by the device. Connect to RD of the next device for daisy chain or cascade operation. POWER SUPPLY PINS 10, 16, 21, 22, 26, 37 +VA – Analog power supply and LVDS input buffer power supply. 9, 17, 20, 23, 24, AGND 25, 27, 36 44 45 (2) 8 +VBD BDGND – – – Analog ground pins. Short to the analog ground plane below the device. Digital power supply for all CMOS digital inputs and CMOS, LVDS outputs. Digital ground for all digital inputs and outputs. Short to the analog ground plane below the device. The duration from the first rising edge of SYNC_O to the second rising edge of SYNC_O is one data frame. The data frame duration is 16 CLKs if BYTE = 0 or 8 CLKs if BYTE = 1. ADS8413 www.ti.com SLAS490 – OCTOBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL NO. 15 NC NAME I/O DESCRIPTION NOT CONNECTED PINS – No connection pins Table 1. Device Configuration for Various Modes of Operation DEVICE PINS AND RECOMMENDED LOGIC LEVELS OPERATION MODE MODE_C/D CLK_I/E LAT_Y/N M1+ M1– M2+ M2– COMMENTS REFERENCE FIGURES FOR SAMPLING AND CONVERSION Recommended configuration or M1 = 1 LVDS Single device 0 1 or 0 0 See comments See comments Set SYNC_I and SDI to logic 0 or + terminal to AGND and –ve terminal to +VBD Set SYNC_I and SDI to logic 0 or + terminal to AGND and –ve terminal to +VBD Maximum 4 devices supported at 2 MSPS with 200-MHz CLK 1 or 2 See Figures 3,4 and 5,6,7 for more details See Figures 3,4,11 and 6,12 for more details or M2 = 0 LVDS 1 or 2 FOR DATA READ See Figures 3,4 and 5,6,8 for more details +VBD 1 1 or 0 0 AGND AGND +VBD Multiple devices in daisy chain 1st Device 2nd To last device 1st Device 2nd To last device 0 1 or 0 0 See comments See comments 1 or 2 0 1 0 0 1 0 See comments +VBD AGND See comments AGND +VBD 1 or 2 Multiple devices in cascade or M1 = 1 LVDS +VBD 1 0 1 or M1 = 0 LVDS AGND or M2 = 0 LVDS (1) AGND +VBD Maximum 3 devices supported at 2 MSPS 1 or 2 See Figures 3,4,14 and 6,15 for more details or M2 = 0 LVDS (1) (1) Specified polarity is suitable for a 100-Ω differential load across the LVDS outputs. However, polarity can be reversed to double the output current in order to support two 100-Ω loads on both ends of the transmission lines, resulting in 50-Ω net load. DETAILED DESCRIPTION SAMPLE AND CONVERT The sampling and conversion process is controlled by the CSTART (LVDS) or CONVST (CMOS) signal. Both signals are functionally identical. The following diagrams show control with CONVST. The rising edge of CONVST (or CSTART) starts the sample phase, if the conversion has completed and the device is in the wait state. Figure 2 shows the case when the device is in the conversion phase at the rising edge of CONVST. In this case, the sample phase starts immediately at the end of the conversion phase and there is no wait state. CONVST tw1 td2 tw2 td4 td1 BUSY td3 Wait Sample Phase tacq Conversion Phase tcnv Wait Figure 1. Sample and Convert With Wait (Less Than 2 MSPS Throughput) 9 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 DETAILED DESCRIPTION (continued) tw2 CONVST Not less than td1 to avoid device entering wait state td2 BUSY td3 Sample Phase tacq Conversion Phase tcnv td4 Sample Phase Figure 2. Sample and Convert With No Wait or Back to Back (2 MSPS Throughput) The device ends the sample phase and enters the conversion phase on the falling edge of CONVST (CSTART). A high level on the BUSY output indicates an ongoing conversion. The device conversion time is fixed. The falling edge of CONVST (CSTART) during the conversion phase aborts the ongoing conversion. A data read after a conversion abort fetches invalid data. Valid data is only available after a sample phase and a conversion phase has completed. The timing diagram for control with CSTART is similar to Figure 1 and Figure 2. Table 2 shows the equivalent timing for control with CONVST and CSTART. Table 2. CONVST and CSTART Timing Control TIMING CONTROL WITH CONVST tw1 tw2 td1 td2 td3 TIMING CONTROL WITH CSTART tw3 tw4 td5 td6 td7 DATA READ OPERATION The ADS8413 supports a 200-MHz serial LVDS interface for data read operation. The three signal LVDS interface (SDO, CLK_O, and SYNC_O) is well suited for high-speed data transfers. An application with a single device or multiple devices can be implemented with a daisy chain or cascade configuration. The following sections discuss data read timing when a single device is used. DATA READ FOR A SINGLE DEVICE (See Table 1 for Device Configuration) For a single device, there are two possible read cycle starts: a data read cycle start during a wait or sample phase or a data read cycle start at the end of a conversion phase. Read cycle end conditions can change depending on MODE C/D selection. Figure 3 explains the data read cycle. The details of a read frame start with the two previous listed conditions and a read cycle end with MODE C/D selection are explained in Figure 5 and Figure 6 and Figure 7 and Figure 8, respectively. 10 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 See Figures 5 and 6 See Figures 7 and 8 RD SYNC_O CLK_O 1F 1R 2R 18F 18R SDO D15 BUS BUSY D14 D0 Figure 3. Data Read With CS Low and BYTE = 0 As shown in Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to rising edge) if BYTE i/p is held low and can be used to synchronize a data frame. The clock count begins with the first CLK_O falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling edges of the clock. The next rising edge of SYNC_O coincides with the 16th rising edge of the clock. D0 is latched out on the 17th rising edge of the clock. The receiver can latch the de-serialized 16-bit word on the 18th rising edge (18R, or the second rising edge after a SYNC_O rising edge). CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the next data read cycle. DATA READ IN BYTE MODE Byte mode is selected by setting BYTE = 1, this mode is allowed for any condition listed in Table 1. Figure 4 shows a data read operation in byte mode. RD SYNC_O CLK_O 1F 1R 2R 9F 9R 10R 18F 18R SDO D15 BUS BUSY D14 D8 D7 D0 Figure 4. Data Read Timing Diagram with CS Low and BYTE = 1 Similar to Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and device is in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 8 clocks wide (rising edge to rising edge) if BYTE i/p is held high and can be used to synchronize a data frame. The clock count begins with the first CLK_O falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling edges of clock. The next rising edge of SYNC_O coincides with the 8th rising edge of the clock. D8 is latched out on the 9th rising edge of the clock. The receiver can latch the de-serialized higher byte on the 10th rising edge (10R, or second rising edge after a SYNC_O rising edge). The de-serialized lower byte can be latched on the 18th rising edge (18R). 11 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the next data read cycle. DATA READ CYCLE START DURING WAIT OR SAMPLE PHASE As shown in Figure 5, the falling edge of RD , with CS low and the device is in a wait or sample phase, triggers the start of a read cycle. The cycle starts when BUS_BUSY goes high and SYNC_O, SDO are released from 3-state. SYNC_O is low at the start and rises to a high level td13 ns after the falling edge of RD. As shown in Figure 5, the MSB is shifted on the 2nd rising edge of the clock (2R). Other details about the data read cycle are discussed in the previous section (see Figure 3). RD td9 td13 td8 BUSY BUS_BUSY 0R CLK_O 1F 1R 2R 3R SYNC_O td14 SDO_O MSB MSB − 1 Figure 5. Start of Data Read Cycle with RD with CS Low and Device in Wait or Sample Phase DATA READ CYCLE START AT END OF CONVERSION PHASE (Read Without Latency, Back-to-Back) This mode is optimized for a data read immediately after the end of a conversion phase and ensures the data read is complete before the sample end while running at 2 MSPS. Point A in Figure 6 indicates 'pre_conversion_end'; it occurs td19 ns before the falling edge of BUSY or [(td2 + tcnv + td4) – td19] ns after the falling edge of CONVST. A read cycle is initiated at point A if RD is issued before point A while CS is low. Alternately, RD and CS can be held low. At the start of the read cycle, BUS_BUSY rises to a high level and the LVDS outputs are released from 3-state. The rising edge of SYNC_O occurs td12 ns after the conversion end. As shown in Figure 6, the MSB is shifted on the 2nd rising edge of the clock (2R). Other details about the data read cycle are discussed in the previous section (see Figure 3). 12 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 Conversion Phase A td19 RD_REQ (Int) td11 BUSY td10 BUS_BUSY O/P 0R CLK_O td12 SYNC_O td14 SDO_O MSB MSB − 1 1F 1R 2R 3R td4 Conversion End Figure 6. Start of Data Read Cycle with End of Conversion DATA READ CYCLE END (With MODE C/D = 0) A data read cycle ends after all 16 bits have been serially latched out. Figure 7 shows the timing of the falling edge of BUS_BUSY and the rising edge of SYNC_O with respect to SDO. SYNC_O rises on the 16th rising edge of CLK_O. As shown in Figure 5 and Figure 6, the MSB is shifted out on the 2nd rising edge of CLK_O. Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O. CONVST CS = 0 BUS_BUSY td15 SYNC_O 15R CLK_O 16R 17R 18R td16 SDO LSB − 1 LSB Figure 7. Data Read Cycle End with MODE C/D = 0 13 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 The next two rising edges of CLK_O are shown as 17R and 18R in Figure 7. On 17R the LSB is latched out, and on 18R SDO and SYNC-O go to 3-state. Note that BUS_BUSY falls td15 ns before the rising edge of SYNC_O when MODE C/D = 0. Care must be taken not to allow LVDS bus usage by any other device until the end of the read cycle or (td15 + 2/fclk + td16) ns after the falling edge of BUS_BUSY. DATA READ CYCLE END (With MODE C/D = 1) A data read cycle ends after all 16 bits have been serially latched out. Figure 8 shows the timing of the falling edge of BUS_BUSY and the rising edge of SYNCO with respect to SDO. SYNC_O rises on the 16th rising edge of CLK_O. As shown in Figure 5 and Figure 6, the MSB is shifted out on the 2nd rising edge of CLK_O. Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O. CONVST CS = 0 BUS_BUSY td17 SYNC_O 15R CLK_O 16R 17R 18R td16 SDO LSB − 1 LSB Figure 8. Data Read Cycle End with MODE C/D = 1 The next two rising edges of CLK_O are shown as 17R and 18R in Figure 8. On 17R the LSB is latched out and on 18R the SDO and SYNC_O go in 3-state. In cascade mode (with MODE C/D = 1) unlike daisy chain mode BUS_BUSY falling edge occurs after LVDS outputs are 3-state. One can use BUS_BUSY falling edge to allow the LVDS bus usage by any other device. RESTRICTIONS ON READ CYCLE START CONVST td23 td24 BUSY Read cycle not allowed to start in this region Figure 9. Read Cycle Restriction Region The start of a data read cycle is not allowed in the region bound by td23 and td24. Previous conversion results are available for a data read cycle start before this region, and current conversion results are available for a read cycle start after this region. 14 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 MULTIPLE DEVICES IN DAISY CHAIN OR CASCADE Multiple devices can be connected in either a daisy chain or cascade configuration. The following sections describes detailed timing diagrams and electrical connections. The ADS8413 provides all of the hand-shake signals required for both of these modes. CONVST or CSTART is the only external signal needed for operation. DAISY CHAIN Figure 10 shows the first two devices in daisy chain. The signals shown by double lines are LVDS and the others are CMOS. Daisy chain mode is selected by setting MODE_C/D = 0. The first device in the chain is identified by selecting LAT_Y/N = 0. Device 1 See Table 1 External Clock (Optional) See Table 1 Last_Device BUS_BUSY SDI CLK_I SYNC_I SD0 CLK_0 SYNC_0 SDI CLK_I SYNC_I Device 2 SD0 CLK_0 SYNC_0 To Next Device or Receiver RD BUS_BUSY +V CLK_I/E LAT_Y/N RD CLK_I/E MODE_C/D BUS_BUSY +V LAT_Y/N MODE_C/D CS CS From Controller Figure 10. Connecting Multiple Devices in Daisy Chain For all of the other devices in the chain LAT_Y/N = 1. See Table 1 for more details on device configurations. SDO, CLK_O, and SYNC_O of device n are to be connected to SDI, CLK_I, and SYNC_I of the n+1 device. SDO, CLK_O, and SYNC_O of the last device in the chain go to the receiver. BUS_BUSY of device n is connected to RD of device n+1 and so on. Finally, BUS_BUSY of the last device in the chain is connected to RD of device 1. This ensures the necessary handshake to seamlessly propagate the data of all devices through the chain (it is also allowed to tie RD = 0 for device 1). TIMING DIAGRAMS FOR DAISY CHAIN OPERATION The conversion speed for n devices in the chain must be selected such that: 1/conversion speed > read startup delay + n*(data frame duration) + td16 Read startup delay = 10 ns + (td19 - td4) + td12 + 2/fCLK Data frame duration = 16/fCLK Note that it is not necessary for all devices in the chain to sample the data simultaneously. But all of the devices must operate with the same exact conversion speed. 15 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 nth CONV CONVST #1 n + 1 Tracking n + 1 Conversion See Figure 6 for details CS tw5 RD #1 BUS_BUSY (Last device) BUS_BUSY #1 RD #2 SDO #1 SDI #2 16−Bit Data nth conversion See Figure 12 for details SYNC_O #1 SYNC_I #2 td18 BUS_BUSY #2 RD #3 SDO #2 SDI #3 #1 16−Bits nth conversion #2 16−Bits nth conversion SYNC_O #2 SYNC_I #3 Figure 11. Data Read Operation for Devices in Daisy Chain DATA READ OPERATION On power up, BUS_BUSY of all of the devices is low. The devices receive CONVST or CSTART to sample and start the conversion. The first device in the chain starts the data read cycle at the end of its conversion. BUS_BUSY of device 1 (connected to RD of device 2) goes high on the read cycle start. Device 2 BUS_BUSY goes high on the rising edge of RD. This propagates until the last device in the chain. Device 2 receives CLK_I, SDI, and SYNC_I from device 1 and it passes all of these signals to the next device. Device 2 (and every subsequent device in the chain) passes the received signals to its output until it sees the falling edge of RD (same as BUS_BUSY of the previous device). In daisy chain mode, BUS_BUSY for any device falls when it has passed all of the previous device data followed by its own data. The falling edge of BUS_BUSY occurs before the rising edge of SYNC_O. This indicates to the receiving device that the previous data chain is over and it is its own turn to output the data. The device outputs the data from the last completed conversion. BUS_BUSY of the last device in the chain is fed back to RD of the first device as shown in Figure 10 (or device 1 RD tied to 0). This makes sure that RD of device 1 is low before its conversion is over. The chain continues with only one external signal (CONVST or CSTART) when CS is held low. Every device LVDS output goes to 3-state once all data transfer through the device has been completed. CS going high during the data read cycle of any device 3-states its SYNC_O and SDO. This halts the propagation of data through the chain. To reset this condition it is necessary to assert CS high for all devices. The new read sequence starts only after CS for all devices is low before point A as shown in Figure 6. The high pulse on CS must be at least 20 ns wide. It is better to connect CS of all of the devices together to avoid undesired halting of the daisy chain. 16 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 CS = 0 BUS_BUSY #1 RD #2 td15 SYNC_O #1 SYNC_I #2 15R CLK_O #1 CLK_I #2 16R 17R td16 18R SDO #1 SDO #2 LSB − 1 #1 LSB #1 BUSY_BUS #2 = 1 17F 17R CLK_O #2 18R tpd1 SYNC_O #2 #1 DATA LSB − 1 #1 LSB #1 MSB MSB − 1 #2 DATA Figure 12. Data Propagation from Device n to Device n+1 in Daisy Chain Mode As shown in Figure 12 there is a propagation delay of tpd1 from SYNC_I to SYNC_O or SDI to SDO. Note that the data frames of all devices in the chain appear seamless at the last device output. The rising edge of SYNC_O occurs at an interval of 16 clocks (or 8 clocks in BYTE mode); this can be used as a data frame sync. The deserializer at the output of the last device can shift the data on every falling edge of the clock and it can latch the parallel 16-bit word on the second rising edge of CLK_O (shown as 18R) after every rising edge of SYNC_O. CASCADE Figure 13 shows the cascade connection. The signals shown with double lines are LVDS and the others are CMOS. Cascade mode is selected by setting MODE_C/D = 1. Similar to daisy chain, the first device in the chain is identified by selecting LAT_Y/N = 0. For all other devices in the chain LAT_Y/N = 1. See Table 1 for more details on device configuration. SDO, CLK_O, and SYNC_O are connected to the common bus. This means only one device occupies the bus at a time, while LVDS drivers for all other devices 3-state. Unlike SDO and SYNC_O, the clock cannot be switched out from device to device as the receiver requires a continuous clock. So only device 1 outputs the clock and CLK_O of all other devices is 3-stated by appropriately setting M1+ and M1as listed in Table 1. 17 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 Device 1 SD0 External Clock CLK_I CLK_0 SYNC_0 BUS_BUSY Last Device BUS_BUSY +V RD M1+,M2− CLK_I/E, LAT_Y/N, +V To Receiver MODE_C/D CS M1−,M2+ From Controller Device 2 RD SD0 CLK_I CLK_0 SYNC_0 BUS_BUSY +V +V M1−,M2−,LAT_Y/N M1+,M2+, MODE_C/D CLK_I/E CS From Controller To Next Device Figure 13. Cascade Connection CLOCK SOURCE In this mode it is very critical to control the skew between the three LVDS o/p signals. It is recommended to use external clock mode only for all of the devices in cascade. BUS_BUSY of device n is connected to RD of device n + 1 and so on. Finally BUS_BUSY of the last device in the chain is to be connected to RD of device 1. This ensures the necessary handshake to control the sequence of data reads for all of the devices in cascade. (It is also allowed to tie RD to 0 for device 1.) TIMING DIAGRAMS FOR CASCADE OPERATION The conversion rate for n devices in cascade must be selected such that: 1/conversion speed > first device read cycle duration + (n - 1) next device read cycle duration First device read cycle duration = read startup delay_1 + data frame duration + (td16 + td17) Next device read cycle duration = read startup delay_n + data frame duration + (td16 + td17) Read startup delay_1 = 10 ns + (td19 - td4 + td12) + 2/fclk Read startup delay_n = (td13 + 2/fclk) Data frame duration = 16/fclk Note that it is not necessary that all devices in the chain to sample the data simultaneously. But all of the devices must operate with the same exact conversion speed. 18 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 nth CONV CONVST n + 1 Tracking n + 1 Conversion See Figure 6 for details CS RD #1 BUS_BUSY #n (Last device) See Figure 15 for details BUS_BUSY #1 RD #2 td18 BUS_BUSY #2 SDO #1 16−Bits nth conversion #2 16−Bits nth conversion SYNC_O SYNC_O #1 SYNC_O #2 Figure 14. Data Read Operation for Devices in Cascade Mode DATA READ OPERATION On power up, BUS_BUSY for all of the devices is low. The devices receive CONVST or CSTART to sample and start the conversion. The first device starts the data read cycle at the end of its conversion. BUS_BUSY of device 1 (connected to RD of device 2) goes high on the read cycle start, indicating that it wants to occupy the bus. Device 2 BUS_BUSY goes high on the rising edge of RD. This propagates until the last device. Device 1 BUS_BUSY goes low after it outputs its data, at this time SDO and SYNC_O for device 1 go to 3-state. The falling edge of BUS_BUSY (RD of the next device) indicates to the next device that it is its turn to output the data. The next device outputs the data from the last completed conversion. BUS_BUSY of the last device goes low and its SYNC_O and SDO go to 3-state after it outputs its data. BUS_BUSY of the last device is fed back to RD of the first device as shown in Figure 13 (RD can also be tied to 0 for device 1). This ensures that RD of device 1 is low before its conversion is over. The data read sequence continues with only one external signal, CONVST or CSTART, when CS = 0. For any device, CS high during the data read cycle 3-states SYNC_O and SDO of the device and halts the data read sequence. To reset this condition it is necessary to assert CS high for all of the devices. The new read sequence starts only after CS for all of the devices is low before point A as shown in Figure 6. The high pulse on CS must be at least 20 ns wide. It is better to connect CS for all of the devices together to avoid undesired halting of the data read sequence. 19 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 CS = 0 BUS_BUSY #1 RD #2 td17 SYNC_O #1 15R CLK_O #1 16R 17R 18R td16 SDO #1 LSB − 1 #1 LSB #1 BUSY_BUS #2 = 1 SYNC_O #2 td13 1F #2 2R #2 SDO #2 MSB MSB − 1 Figure 15. Device n Read Cycle End and Device n+1 Read Cycle Start Unlike daisy chain, the data frames of all the devices in cascade are not seamless and there is a loss of time between one device 3-state to other device data valid due to wakeup time from 3-state and a two clock phase shift between SYNC and data (see Figure 15 for details). As a result, the number of data frames per second in this mode is less than in daisy chain mode. Also, a maximum of 4 devices can be cascaded on the same bus. But, I/O power per device is considerably lower in cascade as compared to daisy chain as each device LVDS o/p goes to 3-state after its data transfer. The deserializer at the output of the last device can shift the data on every clock falling edge, and it can latch the parallel 16-bit word on the second CLK_O rising edge (shown as 18R) after every SYNC_O rising edge. THEORY OF OPERATION The ADS8413 is a member of the high-speed successive approximation register (SAR) analog-to-digital converters family. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The device includes a built-in conversion clock, internal reference, and 200-MHz LVDS serial interface. The device can be operated at maximum throughput of 2 MSPS. ANALOG INPUT An analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the voltage difference between these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. 20 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 THEORY OF OPERATION (continued) +VA ADS8413 +IN 170 W + _ 25 pF −IN 170 W 25 pF AGND AGND Figure 16. Simplified Input Circuit When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal frequency, and source impedance. Essentially, the current into the ADS8413 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current (this may not happen when the signal is moving continuously). The source of the analog input voltage must be able to charge the input capacitance (25 pF) to better than a 16-bit settling level with a step input within the acquisition time of the device. For calculation, the step size can be selected equal to the maximum voltage difference between two consecutive samples at the maximum signal frequency (see the TYPICAL ANALOG INPUT CIRCUIT section). When the converter goes into hold mode, the input impedance is greater than 1GΩ. 49.9 W VCC+ 7 2 3 − THS4031 + 4 1 8 A 10 mF + REF 15 W 680 pF 15 W 0.1 mF 1 mF 6 12 REFM REFIN 18 +IN 19 −IN ADS8413 11 REFM INPUT+ NULL NULL VCC− 49.9 W VCC+ 7 2 3 − THS4031 + 4 1 8 6 INPUT− NULL NULL VCC− Figure 17. Typical Analog Input Schematic 21 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 THEORY OF OPERATION (continued) Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both -IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter linearity may not meet specifications. Care should be taken to ensure that +IN and -IN see the same impedance to the respective sources. If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and linearity error which changes with temperature and input voltage. REFERENCE The ADS8413 has a built-in 4.096-V (nominal value) reference. The ADS8413 can also operate with an external reference. When the internal reference is used, pin 14 (REFOUT) should be connected to pin 13 (REFIN), and a 0.1-µF decoupling capacitor and 1-µF storage capacitor must be connected between pin 14 (REFOUT) and pins 11 and 12 (REFM) (see Figure 18). The internal reference of the converter is buffered. ADS8413 REFOUT 1 WF 0.1 WF REFM AGND REFIN Figure 18. Using Internal Reference The REFIN pin is also internally buffered. This eliminates the need to put a high bandwidth buffer onboard to drive the ADC reference and saves system area and power. When an external reference is used, the reference must be low noise, which can be achieved by the additional bypass capacitor from the REFIN pin to the REFM pin (see Figure 19). REFM must be connected to the analog ground plane. ADS8413 REFOUT 0.1 mF 50 W REF3040 22 mF AGND 0.1 mF 1 mF AGND REFM REFIN Figure 19. Using External Reference DIGITAL INTERFACE TIMING AND CONTROL Refer to the timing diagrams and TIMING REQUIREMENTS table for detailed information. SAMPLING AND CONVERSION Sampling and conversion is controlled by the CONVST pin. For higher noise performance it is essential to have low jitter on the falling edge of CONVST. The device uses the internally generated clock for conversion, hence it has a fixed conversion time. 22 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 THEORY OF OPERATION (continued) READING DATA The ADS8413 includes a high-speed LVDS serial interface. As discussed prior, an external clock (CLK_I, less than 200 MHz) or an internal 200-MHz clock can be used for a data read. The device outputs data in two’s compliment format. Table 3 lists the ideal output codes. Table 3. Ideal Input Voltages and Output Codes DESCRIPTION Full-scale range Least significant bit (LSB) Full scale Midscale Midscale – 1LSB –Full scale 2(+Vref) 2(+Vref)/216 Vref – 1 LSB 0V 0 V – 1 LSB –Vref ANALOG VALUE (+IN – (–IN)) – – 7FFF 0000 FFFF 8000 HEX CODE 23 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 The restrictions on read cycle start are described in the section RESTRICTIONS ON READ CYCLE START (see Figure 9). ADS8413 SDO+ GND 100 W BYTE SDO− SYNC_O+ 100 W SYNC_O− CLK_O+ 100 W CLK_O− MCI− CO− LCI− MCI+ DI− LCI+ CO_EN D15−D6 D9−D0 SN65LVDS152 #1 DI+ LVI EN VCC CO+ SN65LVDS152 #2 DI+ 100 W DI− LCI+ D5−D0 D9−D4 LCI− MCI+ LVI EN VCC MCI− CO− CO_EN CO+ Figure 20. 16-Bit Data De-Serialization While BYTE = 0 24 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 ADS8413 +VBD SDO+ 100 W BYTE SDO− SYNC_O+ 100 W SYNC_O− CLK_O+ 100 W CLK_O− SN65LVDS152 DI+ LVI EN DI− LCI+ D7−D0 D9−D2 LCI− MCI+ VCC MCI− CO− CO_EN CO+ Figure 21. 8-Bit Data De-Serialization While BYTE = 1, Data POWER SAVING The converter provides two power saving modes, full powerdown and nap. Table 4 lists information on the activation/deactivation and resumption times for both modes. Table 4. Powerdown Modes POWERDOWN MODE Normal operation Full powerdown (internal reference) Full powerdown (external reference) Nap powerdown SDO Refer to DATA READ OPERATION section 3 Stated 3 Stated Not 3 stated POWER CONSUMPTION 58 mA 1 µA 1 µA 25 mA ACTIVATED BY NA PD = 0 PD = 0 Nap = 1 ACTIVATION TIME NA td21 td21 150 ns RESUME POWER BY NA PD = 1 PD = 1 Sample start FULL POWERDOWN MODE Full powerdown mode is activated by deasserting PD = 0; the device takes td21 ns to reach the full powerdown state. The device can return to normal mode from full powerdown by asserting PD = 1. The powerup sequence is different for device operation with an internal reference or external reference as shown in Figure 22 and Figure 23. 25 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 PD tw6   Invalid Conversion     Valid Conversion td20   td22 BUSY td21 VREF ICC PD 1 2 3 Full ICC Full ICC Figure 22. Device Full Powerdown and Powerup Sequence with Device Operation in Internal Reference Mode When an internal reference is used, a conversion can be started td22 ns after asserting PD = 1. After the first three conversions, ts1 ns are required for reference voltage settling to the trimmed value. Any conversions after this provide data at the specified accuracy. PD tw6 td20 SDO td22 BUSY td21 1 Invalid Conversion Valid Conversion 2 3 Full ICC ICC PD Full ICC Figure 23. Device Full Powerdown and Powerup Sequence with Device Operation in External Reference Mode When an external reference is used, a conversion can be started td22 n after asserting PD = 1. The first three conversions are required for internal circuit stabilization. Any conversions after this provide data at the specified accuracy. NAP MODE The device automatically enters the nap state if nap = 1 at end of a conversion, and it remains in the nap state until the start of the sampling phase. A minimum of 150 ns is required after a sample start for the device to come out of the nap state and to perform normal sampling. So the minimum sampling time needed for nap mode is tacq(min) + 150 ns, or the maximum conversion speed in nap mode is 1.5 MHz. 26 ¡    ¡       ¡    ¡    SDO ts1  ¡    ¡  ADS8413 www.ti.com SLAS490 – OCTOBER 2005 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8413 circuitry. The device offers single-supply operation, and it is often used in close proximity with digital logic, FPGA, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to the end of sampling and just prior to latching the output of the analog comparator during the conversion phase. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. Noise during the end of sampling and the later half of a conversion must be kept to a minimum (the former half of a conversion is not very sensitive since the device uses a proprietary error correction algorithm to correct for transient errors during this period). The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the device draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor are recommended from REFIN directly to REFM. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a +5-V power supply plane that is separate from the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power to the ADC should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 5 for the placement of the capacitor. In addition to the 0.1-µF capacitor, a 1-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors; all designed to essentially low-pass filter the +5-V supply, thus removing the high frequency noise. Table 5. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE (44,45) Pair of pins require a shortest path to decoupling (9,10) (16,17) (20,21) (22,23) (26,27 or 25,26) capacitors (36,37) TYPICAL CHARACTERISTICS HISTOGRAM (DC CODE SPREAD AT THE CENTER OF CODE) 120000 108126 100000 +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V Number of Hits 120000 100000 HISTOGRAM (DC CODE SPREAD WITH I/P CLOSE TO FS) 140000 EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE 15.25 ENOB − Effective Number of Bits − Bits 15.2 15.15 15.1 15.05 15 14.95 14.9 14.85 14.8 14.75 −40 −20 0 20 40 60 80 +VA = 5 V, fi = 1 kHz, fs = 2 MSPS, Vref = 4.096 V +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V 121865 80000 Number of Hits 80000 60000 60000 40000 40000 30724 11013 8 0 65504 65505 65506 Code 65507 230 65508 20721 20000 8 0 32763 32764 32765 Code 32766 32767 8436 7 20000 TA − Free-Air Temperature − °C Figure 24. Figure 25. Figure 26. 27 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) SIGNAL TO NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 93 SINAD − Signal − to − Noise and Distortion − dB 92.8 92.6 92.4 92.2 92 91.8 91.6 91.4 91.2 91 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 +VA = 5 V, fi = 1 kHz, fs = 2 MSPS, Vref = 4.096 V 93 92.8 SNR − Signal-to-Noise Ratio − dB 92.6 92.4 92.2 92 91.8 91.6 91.4 91.2 91 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 SFDR − Spurious Free Dynamic Range − dB SIGNAL TO NOISE RATIO vs FREE-AIR TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE −105 +VA = 5 V, fi = 1 kHz, fs = 2 MSPS, Vref = 4.096 V −106 −107 −108 −109 −110 −111 −112 −113 −114 −115 −40 +VA = 5 V, fi = 1 kHz, fs = 2 MSPS, Vref = 4.096 V −20 0 20 40 60 TA − Free-Air Temperature − °C 80 Figure 27. TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE −100 ENOB − Effective Number of Bits − Bits 16 Figure 28. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 93 SINAD − Signal − to − Noise and Distortion − dB +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V 15 92 91 90 89 88 87 86 85 84 83 0.1 +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V Figure 29. SIGNAL TO NOISE AND DISTORTION vs INPUT FREQUENCY THD − Total Harmonic Distortion − dB −101 −102 −103 −104 −105 −106 −107 −108 −109 −110 −40 +VA = 5 V, fi = 1 kHz, fs = 2 MSPS, Vref = 4.096 V 14 13 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 0.1 1 10 100 1000 fI − Input Frequency − kHz 1 10 100 fI − Input Frequency − kHz 1000 Figure 30. Figure 31. Figure 32. 28 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) SIGNAL TO NOISE RATIO vs INPUT FREQUENCY 93 +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V SFDR − Spurious Free Dynamic Range − dB SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY −90 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY −80 THD − Total Harmonic Distortion − dB +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V SNR − Signal-to-Noise Ratio − dB −95 92 +VA = 5 V, TA = 25°C, fs = 2 MSPS, Vref = 4.096 V −85 −90 −95 −100 −105 −110 −115 0.1 −100 91 −105 90 −110 89 −115 88 0.1 −120 0.1 1 10 100 fI − Input Frequency − kHz 1000 1 10 100 fI − Input Frequency − kHz 1000 1 10 100 fI − Input Frequency − kHz 1000 Figure 33. OFFSET ERROR vs SUPPLY VOLTAGE 0.1 0.08 0.06 Offset Error − mV Gain Error − % FS 0.01 0.009 0.008 0.007 0.006 0.005 0.004 0.003 TA = 25°C, fs = 2 MSPS, Vref = 4.096 V Figure 34. GAIN ERROR vs SUPPLY VOLTAGE 0.15 0.13 0.11 Offset Error − mV 0.09 0.07 0.05 0.03 0.01 4.85 4.95 5.05 5.15 VCC − Supply Voltage − +VA in V 5.25 Figure 35. OFFSET ERROR vs FREE-AIR TEMPERATURE fs = 2 MSPS, Vref = 4.096 V, +VA = 5 V 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 4.75 TA = 25°C, fs = 2 MSPS, Vref = 4.096 V 0.002 0.001 0 4.75 4.85 4.95 5.05 5.15 5.25 VCC − Supply Voltage − +VA in V −0.01 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 Figure 36. GAIN ERROR vs FREE-AIR TEMPERATURE 0.015 +VA = 5 V, fs = 2 MSPS, Vref = 4.096 V Figure 37. POWER DISSIPATION vs SAMPLE RATE 320 Figure 38. POWER DISSIPATION vs SUPPLY VOLTAGE 315 TA = 25°C, fs = 2 MSPS, Vref = 4.096 V 300 Normal PD − Power Dissipation − mW PD − Power Dissipation − mW 0.01 310 305 300 295 290 285 280 275 Gain Error − % FS 0.005 250 0 Nap 200 −0.005 −0.01 150 +VA = 5 V, TA = 25°C, Vref = 4.096 V −0.015 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 100 0 0.5 1 1.5 Sample Rate − MSPS 2 270 4.75 4.85 4.95 5.05 5.15 5.25 VCC − Supply Voltage − +VA in V Figure 39. Figure 40. Figure 41. 29 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) POWER DISSIPATION vs FREE-AIR TEMPERATURE 320 315 PD − Power Dissipation − mW 310 305 300 295 290 285 280 −40 fs = 2 MSPS, Vref = 4.096 V, +VA = 5 V DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 1.5 +VA = 5 V, fs = 2 MSPS, Vref = 4.096 V 1 max 0.5 2 1.5 INL − Integral Nonlinearity − LSB 1 0.5 0 −0.5 −1 −1.5 INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE +VA = 5 V, fs = 2 MSPS, Vref = 4.096 V max DNL − Differential Nonlinearity − LSB 0 min −0.5 min −20 0 20 40 60 TA − Free-Air Temperature − °C 80 −1 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 −2 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C 80 Figure 42. POSITIVE INTEGRAL NONLINEARITY DISTRIBUTION OVER 25 UNITS 12 12 Figure 43. NEGATIVE INTEGRAL NONLINEARITY DISTRIBUTION OVER 25 UNITS 4.112 4.108 TA = 25°C, fs = 2 MSPS, Vref = 4.096 V Figure 44. INTERNAL REFERENCE OUTPUT vs SUPPLY VOLTAGE 10 10 Internal Reference Output − V 4.104 4.1 4.096 4.092 4.088 4.084 Number of Devices Number of Devices 8 8 6 6 4 4 2 2 4.08 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 0 0.8 0.9 1 1.1 1.2 INL − Integral Nonlinearity max − LSB 0 −1.4 −1.2 −1.0 −0.8 −0.6 INL − Integral Nonlinearity min − LSB VCC − Supply Voltage − +VA in V Figure 45. Figure 46. Figure 47. 30 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) INTERNAL REFERENCE OUTPUT vs FREE-AIR TEMPERATURE 4.112 4.108 Internal Reference Output − V 4.104 4.1 4.096 4.092 4.088 4.084 4.08 −40 fs = 2 MSPS, Vref = 4.096 V, +VA = 5 V −20 0 20 40 60 TA − Free-Air Temperature − °C 80 Figure 48. 1.5 1 DNL − LSBs 0.5 0 −0.5 −1 0 32767 Figure 49. Typical DNL 65535 2 1.5 1 INL − LSBs 0.5 0 −0.5 −1 −1.5 −2 0 32767 Figure 50. Typical INL 65535 31 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 TYPICAL CHARACTERISTICS (continued) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 −180 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 f − Frequency − MHz Figure 51. Typical FFT PARAMETER MEASUREMENT INFORMATION DRIVER Driver Enable II Y VOD Z VI VOZ IOZ VOY VOC VOY + VOZ 2 IOY Driver Enable Y Input Z CL = 10 pF (2 Places) VOD 100 W + 1% Figure 52. Driver Voltage and Current Definitions 32 ADS8413 www.ti.com SLAS490 – OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) 100% 80% Differential Output VOD(H) 0V VOD(L) 20% 0% tf tr Figure 53. Timing and Voltage Definitions of the Differential Output Signal Driver Enable Y Input Z VOC CL = 10 pF (2 Places) VOC VOC(PP) VOC(SS) 49.9 Ω, ±1% (2 Places) 3V 0V Figure 54. Test Circuit and Definitions for the Driver Common-Mode Output Voltage A V IA )V 2 VIA VIC B VIB VO IB VID R Figure 55. Receiver Voltage Definitions 33 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device ADS8413IBRGZR ADS8413IBRGZRG4 ADS8413IBRGZT ADS8413IBRGZTG4 ADS8413IRGZR ADS8413IRGZRG4 ADS8413IRGZT ADS8413IRGZTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN QFN QFN QFN QFN Package Drawing RGZ RGZ RGZ RGZ RGZ RGZ RGZ RGZ Pins Package Eco Plan (2) Qty 48 48 48 48 48 48 48 48 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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