AMC6821SDBQR

Burr Brown Products from Texas Instruments AM C6 AMC 82 1 6821 AMC6821 SBAS386A – MAY 2006 – REVISED MAY 2006 Analog Monitor and Control Circuit FEATURES • • • • • • • • Remote Temperature Sensor: ±1°C Accuracy, 0.125°C Resolution Local Temperature Sensor: ±2°C Accuracy, 0.125°C Resolution PWM Controller Frequency: 10Hz to 40kHz Duty Cycle: 0% to 100%, 8 Bits Automatic Fan Speed Control Loops SMBus Interface Power: 3V to 5.5V Packages (Green): SSOP-16 (4mm × 5mm) and QFN-16 (4mm × 4mm) VDD GND APPLICATIONS • • • • • • Notebook PCs Network Servers Desktop PCs Telecommunications Equipment PC-Based Equipment DLP™ and LCD Projectors A0 A1 THERM AMC6821 SMBus/I C Interface Temperature Threshold Registers 2 SCLK SDA FAN-FAULT THERM Control OVR Limit Comparator Chip Registers Control Logic SMBALERT Remote Sensing Transistor Local/Remote Temperature Registers IN+ TACH Data +V Mux ADC INmP Signal Conditioning Fan Speed Counter TACH On-Chip Diode Temperature Sensor Ref Current Source (I1; I0) PWM Control PWM Output +5V PWM-MODE Automatic Fan Speed Controller US patents pending. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a trademark of Texas Instruments. Pentium-IV is a trademark of Intel. JMC is a registered trademark of JMC Products. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2006, Texas Instruments Incorporated PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT AMC6821 PACKAGE-LEAD SSOP-16 PACKAGE DESIGNATOR DBQ SPECIFIED TEMPERATURE RANGE –40°C to +125°C PACKAGE MARKING AMC6821SDBQ ORDERING NUMBER AMC6821SDBQ AMC6821SDBQR TRANSPORT MEDIA, QUANTITY Tubes, 75 Tape and Reel, 2500 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) VDD to GND (1) VALUE –0.3 to +6.5 –0.3 to +6.5 –0.3 to VDD + 0.3 –40 to +125 –65 to +150 +150 UNIT V V V °C °C °C PRODUCT PREVIEW Digital input voltage to GND Analog input voltage to GND Operating temperature range Storage temperature range Junction temperature (TJ Max) (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 ELECTRICAL CHARACTERISTICS At TA = –40°C to +100°C and VDD = +3V or +5V, unless otherwise noted. AMC6821 PARAMETER TEMPERATURE MEASUREMENT Local sensor accuracy TA = +50°C to +100°C TA = –25°C to +100°C TR = +50°C to +100°C Remote sensor accuracy (1) Sensor resolution Conversion time PWM CONTROLLER PWM frequency range (programmable) PWM frequency accuracy Duty cycle Duty cycle resolution FAN RPM-TO-DIGITAL CONVERTER Accuracy Full-scale count Nominal input RPM Internal clock frequency DIGITAL INPUT/OUTPUT VOH IOH VIH VIL IIH IIL Open-drain output low voltage Open-drain high-level output leakage current Input high voltage Input low voltage Input high current Input low current 5 2.70 Normal operation Standby mode –40 –65 5 1.1 TBD 5 +125 +150 5.25 TBD 2.1 0 –1 1 Sink current 6 mA, VDD = +3V Sink current 6mA, VDD = +5V 0 TBD 0.1 1 VDD + 0.3 0.8 0.4 V V µA V V µA µA pF V mA µA mW °C °C 100 100 0°C to +100°C ±6 65535 23000 RPM kHz % 0°C to +100°C Programmable 8-bit 0 0.39 10 40k ±6 100 Hz % % %/bit TA = 0°C to +100°C TR = –40°C to +125°C Both channels Two channels ±0.5 ±1.0 ±0.5 ±1.0 0.125 62.5 ±2.0 ±3.0 ±1.0 ±3.0 °C °C °C °C °C ms CONDITIONS MIN TYP MAX UNIT Input capacitance POWER SUPPLY VDD Current Power dissipation Operating temperature Storage temperature (1) The remote temperature sensor is optimized for thePentium-IV™ thermal diode with diode ideality nMIN = 1.0012, nTYP = 1.0021, and nMAX = 1.0030. Submit Documentation Feedback 3 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 SDA tSU;DAT tBUF tF SCL tLOW tF tF tHD;STA tSP tR S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S MSC510 Figure 1. Definition of Timing Specification TIMING REQUIREMENTS At VDD = +3V or +5V, and TA = TMIN to TMAX, unless otherwise noted. AMC6821 PARAMETER fSCLK tBUF tSU;STA tHD;STA tSU;STO tLOW tHIGH tR tF tSU;DAT tHD;DAT tTIMEOUT Clock frequency Bus free time Start setup time Start hold time Stop condition setup time SCL low time SCL high time SCL, SDA rise time SCL, SDA fall time Data setup time Data hold time Detect clock low timeout 250 300 30 4.7 4.7 4.0 4.0 4.7 4.0 1000 300 CONDITIONS MIN TYP MAX 100 UNIT kHz µs µs µs µs µs µs ns ns ns ns ms PRODUCT PREVIEW 4 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 DEVICE INFORMATION SSOP-16 (body size: 5mm x 4mm) QFN-16 (body size: 4mm x 4mm) PWM-OUT TACH OVR NC GND VDD THERM FAN-FAULT 1 2 3 4 5 6 7 8 16 SCLK 15 SDA 14 SMBALERT TACH OVR NC GND 1 2 3 4 16 15 14 13 12 A0 A1 PWM-MODE IN+ AMC6821 13 A0 12 A1 11 PWM-MODE 10 IN+ 9 IN- AMC6821 (Thermal pad must be connected to GND.) SMBALERT 11 10 9 8 PWM-OUT SCLK 6 5 SDA 7 FAN-FAULT THERM VDD IN- TERMINAL FUNCTIONS PIN NO. NAME PWM-OUT TACH OVR NC GND VDD THERM FAN-FAULT IN– IN+ SSOP 1 2 3 4 5 6 7 8 9 10 QFN 16 1 2 3 4 5 6 7 8 9 DESCRIPTION Output, open-drain. PWM output to control fan speed. Input. Fan tachometer input to measure the fan speed. Digital output, open-drain, active low. Goes low when temperature reaches the critical shutdown threshold or remote temperature sensor failed. (See the Interrupt section for details.) Not connected. Reserved for manufacturer's testing. System ground Power supply, +3 to +5V Digital input/output (open-drain). As an output, an active low output indicates the temperature over the THERM temperature limit. As an input, the pin provides an external fan control. When the pin is pulled low by external signal, the THERM-IN bit is set, and the fan is set to full-speed. Open-drain output. Goes low when a fan failure is detected. Negative analog differential input. Connected to cathode of external temperature-sensing diode. Positive analog differential input. Connected to anode of external temperature-sensing diode Pentium-IV™ substrate transistor or general-purpose 2N3904 type transistor. Digital input, PWM mode selection. When tied low (GND), the high PWM frequency range (1kHz to 40kHz) is selected. When tied to VDD or floated, the low PWM frequency range (10Hz to 94Hz) is selected. Device slave address selection pin (see the SMB Interface section for details). Device slave address selection pin (see the SMB Interface section for details). Digital output, open-drain, SMBALERT, active low. Requires a pull-up resistor (2.2kΩ typical). Bi-directional digital I/O pin, SMBus data, open-drain. Requires a pull-up resistor (2.2kΩ typical). Digital input, SMBus clock. Requires a pull-up resistor (2.2kΩ typical). PWM-MODE A1 A0 SMBALERT SDA SCLK 11 12 13 14 15 16 10 11 12 13 14 15 Submit Documentation Feedback 5 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 SMBUS INTERFACE The AMC6821 communicates through the serial system management bus (SMBus). The AMC6821 is connected to this bus as a slave device, under the control of a bus master. The AMC6821 has a 7-bit serial bus address, which is programmable by properly connecting the address pins A0 and A1. Table 1 shows the selection of the AMC6821 slave address. Table 1. AMC6821 Address Select A0 GND NC (1) VD GND NC VD GND NC VD (1) NC = No connection. A1 GND GND GND NC NC NC VD VD VD ADDRESS 0011000 0011010 0011001 0101100 0101110 0101101 1001100 1001110 1001101 PRODUCT PREVIEW Communication Protocols The AMC6821 employs four standard SMBus protocols: the send byte, receive byte, write byte, and read byte. All other operations result in undefined results. Send Byte S SLAVE ADDRESS 7-bit AMC6821 slave address WR ACK COMMAND 8-bit register address ACK P S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; WR = write (bit value of 0). Receive Byte S SLAVE ADDRESS 7-bit AMC6821 slave address RD ACK DATA 8-bit data from the register selected previously NACK P S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; RD = read (bit value of 1); NACK = not acknowledged. Write Byte S SLAVE ADDRESS 7-bit AMC6821 slave address WR ACK COMMAND 8-bit register address ACK DATA 8-bit data written to register ACK P S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; WR = write (bit value of 0). 6 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Write Multiple Bytes S SLAVE ADDRESS 7-bit AMC6821 slave address DATA Third 8-bit data written third register ACK WR ACK COMMAND 8-bit register address of first register to be written ... ACK DATA First 8-bit data written first register DATA Last 8-bit data ACK DATA Second 8-bit data written second register ACK P ACK S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; WR = write (bit value of 0). The first register is the one to which the first data byte is written. The next register is the second register. If the bus master continues to transfer data into the AMC6821 after writing the last location, all data are ignored until the operation stops. Read Byte S SLAVE ADDRESS 7-bit AMC6821 slave address WR ACK COMMAND 8-bit register address ACK Sr SLAVE ADDRESS 7-bit AMC6821 slave address RD ACK DATA 8-bit data from register NACK P S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; WR = write (bit value of 0); RD = read (bit value of 1); NACK = not acknowledged; Sr = repeated start condition. S SLAVE ADDRESS 7-bit AMC6821 slave address DATA WR ACK COMMAND Address of first register to be read ACK ACK Sr SLAVE ADDRESS 7-bit AMC6821 slave address RD ACK DATA 8-bit data from first register ACK ... DATA Last 8-bit data NACK P 8-bit data from second register S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; WR = write (bit value of 0); RD = read (bit value of 1); NACK = not acknowledged; Sr = repeated start condition. The first register is the one from which the first data byte is transmitted. The next register is the second register. If the bus master continues clocking data out after reading the last location (0x3F), the value 0x00 is sent out until the operation stops. The AMC6821 is entirely controlled by the registers. All registers are 8-bit. The AMC6821 has an address pointer register; the value of the address pointer register determines which register. To write data to the device register or read data from it, the address pointer register must be set properly. Data can then be written into or read from that register. The command issued by the bus master always contains the initial value of the address pointer register. The command is constructed as shown in Table 2. Table 2. Command Format (1) Bit 7 (MSB) 0 Bit 6 0 Bit 5 ADDR5 Bit 4 ADDR4 Bit 3 ADDR3 Bit 2 ADDR2 Bit 1 ADDR1 Bit 0 (LSB) ADDR0 (1) ADDR[5:0] is the address of the register that is accessed first. The register address is stored in the address pointer register. In the send byte operation, the bus master writes the address of a specified device register into the address pointer register. In the receive byte operation, the bus master reads the data back from the device register addressed by the address point register. In the write byte operation, the bus master sets the address pointer register to the address of a specified device register, then writes 8-bit data into it. In the read byte operation, the SMBus master sets the address pointer register to the address of a specified device register first, then reads 8-bit data back from it. Submit Documentation Feedback 7 PRODUCT PREVIEW Read Multiple Bytes AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 In the write multiple bytes operation, the address pointer of the AMC6821 increments by '1' after the data are written, until it reaches the last register address (0x3F). If the host continues to transfer data into the AMC6821 after writing the last location, all data are ignored until the operation stops. When reading multiple bytes, the address pointer of the AMC6821 increments by '1' after transmitting the data until it reaches the last register address (0x3F). If the host continues clocking data out after reading the last location, the value 0x00 is sent out until the operation stops. SMBus ALERT RESPONSE ADDRESS (ARA) The alert response address is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices issue simultaneous interrupts. The SMBALERT pin is an open-drain interrupt output pin. When the AMC6821 issues an interrupt request, the following procedure occurs: 1. SMBALERT is pulled low. 2. The bus master sends an alert response address or ARA (ARA = 0001100), and initiates a read operation, as shown in Table 3. 3. The AMC6821 responds to the ARA by sending the slave address back. The 7-bit device slave address is placed in the seven most significant bits of the byte; the last bit is '0'. 4. The master receives the AMC6821 slave address and starts the interrupt service. 5. If more than one device pulls the SMBus low, the highest priority (lowest slave address) device wins the communication right via standard arbitration during the slave address transfer (refer to the SMBus specification version 2.0 for details). 6. To service the interrupt request of the AMC6821, the master must read the status register. Most interrupt source bits in the status registers are cleared after reading the status register, and are reasserted if the error condition still exists on the next monitoring cycle. The SMBALERT only clears if the interrupt has been resolved. Table 3. ARA Operation S ALERT RESPONSE ADDRESS 00001100 RD ACK DATA 7-bit MSB: slave address of AMC6821 LSB = 0 NACK P PRODUCT PREVIEW S = start condition; P = stop condition; shaded = slave to master; unshaded = master to slave; RD = read (bit value of 1); NACK = not acknowledged. SMBus TIMEOUT The AMC6821 has a programmable SMBus timeout function. If the timeout function is enabled (when a single clock is held low longer than 30ms ±10%), the AMC6821 releases the bus (stops driving the bus and lets SCLK and SDA float high), resets the communication, and is able to receive new START conditions. If the timeout function is disabled (when the clock resumes after being held low for longer than 30ms), the AMC6821 continues the bus communication at the current point. To disable the timeout function, set the bit TODIS (bit 7 of Configuration Register 4) to '1'. To enable this function, clear the bit TODIS to '0'. After power-on or reset, TODIS is cleared and the timeout function is enabled. POWER-ON RESET AND START OPERATION After power-on, all registers are set to the power-on default values. The device does not perform any monitoring functions until the START bit of Configuration Register 1 is set ('1'). No detections are executed until the first monitoring cycle is completed, and all measurement data registers (such as remote and local temp-data registers and the TACH data register) are updated with the new measured value. No interrupt signals are generated until the first cycle of monitoring and detection is completed. This process avoids any false alarms caused by the power-on default setting. After power-on, the fan spin-up process is performed. At the end of spin-up, the duty cycle of the PWM driver is adjusted to 33%. (Refer to the Fan Spin-Up section for details). Device status after software reset is similar to power-on reset. 8 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 APPLICATION INFORMATION ADC CONVERTER The AMC6821 has an 11-bit, on-chip analog-to-digital converter (ADC), as shown in Figure 2. This ADC converts the analog input into digital format. The analog input is passed through front-end signal conditioning circuitry to remove the noise. The resulting signal is then converted by the ADC. To further reduce the effects of noise, digital filtering is performed by averaging the results of 32 measurement cycles. After digital filtering, the newest result is stored in the temperature data register (low byte and high byte) in two’s complement format. The ADC stops when the START bit of Configuration Register 1 is cleared ('0') and runs when START = 1. LPF and Signal Conditioning ADC Digital Filter Data Registers Mux 60kHz Figure 2. On-Chip Analog-to-Digital Converter TEMPERATURE SENSOR The AMC6821 has an integrated temperature sensor (shown in Figure 3) to measure the ambient temperature, and one remote diode sensor (such as a Pentium thermal diode) input to measure external (CPU) temperature. The measurement relies on the characteristics of a semiconductor junction operation at a fixed current level. The forward voltage of the diode (VBE) depends on the current through it and the ambient temperature. The change in VBE when the diode is operated at two different currents, I1 and I2, is shown in Equation 1: DV BE + KT In(N) q (1) Where: k is Boltzmann’s constant, q is the charge of the carrier, T is the absolute temperature in degrees Kelvin, and N is the ratio of the two currents. I1 I2 SW1 SW2 Diode Temperature Sensor Figure 3. Integrated Local Temperature Sensor Mux LPF and Signal Conditioning ADC and Signal Processing Local Temperature Registers Submit Documentation Feedback 9 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 APPLICATION INFORMATION (continued) The remote sensing transistor can be a substrate transistor built within the microprocessor (as in a Pentium-IV), or a discrete small-signal type transistor. This architecture is shown in Figure 4. The internal bias diode biases the IN– terminal above ground to prevent the ground noise from interfering with the measurement. An external capacitor (up to 1000pF) may be placed between IN+ and IN– to further reduce the noise from interfering. I1 I2 Remote Temperature Registers SW1 IN+ Substrate Sensing Transistor uP IN- SW2 ADC and Signal Processing IBIAS Bias Diode Figure 4. Remote Temperature Sensor The analog sensing signal is pre-processed by a low-pass filter and signal conditioning circuitry, then digitized by the ADC. The resulting digital signal is further processed by the digital filter and processing unit. The final result is stored in the local temperature data register and remote temperature data register, respectively. The 8MSBs are stored in the corresponding Temp-DATA-HByte register, and the 3LSBs are stored in the Temp-DATA-LByte register. Refer to the Temperature Data Registers section for details. The format of the final result is in two’s complement; see Table 4. It should be noted that the device measures the temperature from –40°C to +125°C, although the code represents temperatures from –128°C to +127°C. Parasitic resistance (seen in series with the remote diode) to the IN+ and IN– inputs to the AMC6821 is caused by a variety of factors, including printed circuit board (PCB) track resistance and track length. This series resistance appears as a temperature offset in the remote sensor temperature measurement, and causes more than 0.5°C error per ohm. The AMC6821 is implemented with a TI-patented technology to automatically cancel out the effect of this series resistance, giving a more accurate result without the need for user-characterization of this resistance. READING Temperature Data It is important to note that temperature can be read by an 8-bit value (with 1°C of resolution) from the Temp-DATA-HByte register, or as an 11-bit value (with 0.125°C of resolution) from the Temp-DATA-LByte and Temp-DATA-HByte registers. If only 1°C of resolution is required, the temperature readings can be read back at any time and in no particular order. If reading the 11-bit measurement is required, the process involves a two-register read for each measurement. To get an 11-bit result of the remote sensor, the controller must read the Temp-DATA-LByte register (0x06) first, and the Remote-Temp-DATA-HByte register (0x0B) second to complete the reading. However, to get bit 11 of the local sensor only, or to get both local and remote sensors, the controller must read Temp-DATA-LByte first, Local-Temp-DATA-HByte (0x0A) second, and Remote-Temp-DATA-HByte third. This method causes all associated temperature data registers to be frozen until the Remote-Temp-DATA-HByte register has been read. This process also prevents the high byte data from being updated while the three LSBs are being read, and vice-versa. 10 Submit Documentation Feedback Mux LPF and Signal Conditioning PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 APPLICATION INFORMATION (continued) Table 4. Temperature Data Format TEMPERATURE (°C) +127 +125 +100 +75 +50 +25 +10 +1 0 –1 –25 –50 –75 –100 –125 –128 BINARY DIGITAL CODE (11 bits) 01111111000 01111101000 01100100000 01001011000 00110010000 00011001000 00001010000 00000001000 00000000000 11111111000 11100111000 11001110000 10110101000 10011100000 10000000000 10000011000 Temperature Out-of-Range Detection The AMC6821 has the following temperature limitation detections: 1. High and Low Temperature Limit: The value of the High-Temp-Limit and Low-Temp-Limit registers specify the remote or local temperature ranges of normal operation. When the local or remote temperatures are equal to or above the value of the corresponding High-Temp-Limit register, the LTH or RTH bits in the status register are set ('1'). Likewise, when the local or remote temperatures are less than or equal to the corresponding Low-Temp-Limit register, the LTL or RTL bits in the status register are set ('1'). When the local temperature is out-of-range (LTH = 1 or LTL = 1), the local temperature out-of-range event occurs. The LTO bit in the status register is set ('1'), and the LTO interrupt is generated via the SMBALERT pin if it is enabled (the LTOIE bit of Configuration Register 2 is set). Similarly, when the remote temperature is-out-of range (RTH = 1 or RTL = 1), the remote temperature out-of-range event occurs. The RTO bit in the status register is set ('1'), and the RTO interrupt is generated via the SMBALERT pin if it is enabled (the RTOIE bit of Configuration Register 2 is set). 2. Critical Limit: Critical temperature limit is the highest allowed temperature of remote or local temperature. When the temperature is greater than or equal to the corresponding critical temperature, the LTCT or RTCT bit of the status register is set ('1'), the output of the OVR pin goes low, and a non-maskable interrupt is generated through the SMBALERT pin (low). 3. Passive Cooling Temperature (PSV) Limit: This limit defines the threshold of the passive cooling. In the auto temperature fan control mode, the system enters a passive cooling condition when the active control temperature is equal to or below this limit, and the fan stops. In passive cooling, the LPSV bit of Status Register 2 (0x03) is set ('1'), and a PSV interrupt is generated on the SMBALERT pin if enabled (PSVIE = 1). Note that reading the Status Register clears the LPSV bit. After reading, if the active control temperature remains equal to or below the PSV temperature, this bit reasserts on next monitoring cycle. 4. THERM Limit: This limit is an additional fail-safe threshold. When the local or remote temperature is equal to or above this limit, the corresponding L-THERM or R-THERM bit is set ('1'), and the THERM pin is asserted low, which can be used to throttle the CPU clock. Furthermore, the THERM interrupt is generated on the SMBALERT pin if enabled (THERMOVIE = 1). Reading the Status Register 1 clears the R-THERM and L-THERM bits. Once cleared, these bits are not reasserted until the temperature falls 5°C below the THERM limit, even if the THERM condition persists. If the THERM-FAN-EN bit of the Configuration Register 3 is set ('1'), L-THERM = 1 or R-THERM = 1 forces the fan to run at full-speed. When THERM-FAN-EN = 0, the status of the L-THERM and R-THERM bits do not affect the fan speed directly. Note that the THERM limit can be lower or higher than other temperature limits. For example, if the THERM limit is lower than the PSV temperature limit, then the CPU clock can be throttled while the cooling fan is off. Submit Documentation Feedback 11 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Local-High-Temp-Limit LTH LTO LTO Interrupt SMBALERT Pin Low LTOIE Local Temperature LTL Local-Low-Temp-Limit Remote-High-Temp-Limit RTH RTO RTO Interrupt SMBALERT Pin Low RTOIE Remote Temperature RTL Remote-Low-Temp-Limit Loca-Critical-Temp Local Temperature LTC Bit in Status Register 2 OVR Pin Low SMBALERT Pin Low Remote-Critical-Temp Remote Temperature RTC Bit in Status Register 2 OVR Pin Low SMBALERT Pin Low PRODUCT PREVIEW 12 Active Control Temperature PSV-TempT LPSV Bit in Status Register 2 PSV Interrupt SMBALERT Pin Low PSVIE Assert THERM Pin Low L-THERM Limit Local Temperature THERM-FAN-EN L-THERM Bit in Status Register 2 THERMOVIE Local Therm Interrupt SMBALERT Pin Low Force Fan to Full-Speed Assert THERM Pin Low R-THERM Limit Remote Temperature THERM-FAN-EN R-THERM Bit in Status Register 1 THERMOVIE Remote Therm Interrupt SMBALERT Pin Low Force Fan to Full-Speed Figure 5. Temperature Out-of-Range Detection Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Remote Temperature Sensor Failure Detection The remote temperature sensor failure detection determines whether the remote sensor diode has an open-circuit condition, short-circuit to ground, or a short-circuit (IN+) to (IN–) condition. This fault detection is based on the analog input voltage and is not checked until the first monitoring cycle is completed after power-on. Reading the fault sensor returns a value of –128°C (0x80). Since the power-on default value of the temperature data registers is 0x80 (–128°C), a reading of 0x80 from the temperature data register immediately after power-on does not indicate a diode fault condition. The remote temperature sensor failure can be only checked after the first monitoring cycle has completed after power-on. When a remote sensor failure occurs, the remote sensor failure bit (RTF in the Status Register) is set to '1', the OVR pin is forced low, and an RTF interrupt is generated through the SMBALERT pin if the interrupt is enabled (RTFIE = 1). Once this interrupt is generated, the RTF bit remains '1' and the OVR pin stays low until a power-on reset or software reset is issued, whether or not the failure condition persists. PWM Output The PWM-Out pin is an open-drain output. When PWM-EN of Configuration Register 2 is cleared ('0'), the PWM-Out pin is disabled and goes into a high-impedance status. When PWM-EN is set ('1'), the PWM-Out pin is enabled to drive the fan. When enabled, the status of the PWM-Out pin is determined by the PWM duty cycle and phase bits (PWMINV of Configuration Register 1). When PWMINV = 0 (default), the PWM-Out pin goes low for 100% duty cycle (suitable for driving the fan using a PMOS FET). Setting PWMINV to '1' makes the PWM-Out pin go high (with an external pull-up resistor) for a 100% duty cycle. This setting is used to drive an NMOS-power FET. +5V AMC6821 PWM-Out PWM Control PWM-EN PWMINV = 0 (default) for driving the PMOS. ON PWM Control PWM-EN PWMINV = 1 for driving the NMOS. AMC6821 PWM-Out ON +5V Figure 6. PWM Output PWM WAVEFORM SETTING PWM frequency and duty cycle are programmable. The value of the DCY Register defines the duty cycle: it has 8-bit resolution, 1LSB corresponding to 1/255 (0.392%). Writing 0x00 sets the duty cycle to 0%; writing 0xFF sets the duty cycle to 100%. PWM frequency has two ranges: the high range is from 1kHz to 40kHz, and the low range is from 10Hz to 94Hz. The PWM-MODE pin status determines which range is selected. When the PWM-MODE pin is tied to ground, the high range is selected. Otherwise, the low range is selected. Bits [PWM2:PWM0] in the Fan Characteristics Register define the frequency; see Table 5. The resolution of the PWM waveform period is 0.312µs, corresponding to a 3.2MHz clock. The default value after power-on is 30Hz when the low range is selected, or 25kHz when the high range is selected. RPM reduces as the duty cycle decreases. OFF Period ON Figure 7. PWM Waveform (PWMINV = 1) Submit Documentation Feedback 13 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Table 5. PWM Frequency PWM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PWM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PWM0 0 1 0 1 0 1 0 1 When the PWM-MODE Pin is Tied to GND 0 1 0 1 0 1 0 1 1kHz 10kHz 20kHz 25kHz (default) 30kHz 40kHz 40kHz 40kHz PWM FREQUENCY 10Hz 15Hz 23Hz 30Hz (default) 38Hz 47Hz 62Hz 94Hz When the PWM-MODE Pin is Floating or Tied to VDD PRODUCT PREVIEW FAN SPEED MEASUREMENT The AMC6821 monitors the fan speed (RPM) via the TACH pin (Figure 8 illustrates this process). The TACH-EN bit of Configuration Register 2 (bit 2, 0x01) enables the fan speed measurement. When TACH-EN is cleared ('0'), the measurement is disabled. The measurement is enabled when the TACH-EN bit is set to '1'. This section describes the device behavior when TACH-EN is set ('1'). The on-chip fan-speed counter does not count the fan tach output pulses directly because of the low RPM of the fan. Instead, the period of the fan revolution is measured by gating an on-chip clock (100kHz). The result is stored in the TACH-DATA Register that contains two bytes (16 bits total). RPM monitoring is disabled when the START bit of Configuration Register 1 or the TACH-EN bit of Configuration Register 2 is cleared ('0'), and is enabled when START = 1 and TACH-EN = 1. If the TACH-MODE bit is cleared, RPM monitoring stops and the TACH-DATA register is not updated when the duty cycle is less than 7%. If the TACH mode is equal to '1' the RPM monitoring is always performed, and the TACH data are always updated after each monitoring. 14 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 TACH-DATA Register Two fan tach pulse periods (PSPR = 0) or four tach pulse periods (PSPR = 1) are measured and the result is stored in the TACH-DATA Register, as shown in Figure 8. Counting stops if the counter is over-range; the measurement cycle repeats until monitoring is disabled, and the fan speed (RPM) can be calculated as shown in Equation 2: RPM = (10000 x 60) (Value of TACH-DATA Register) (2) Reading the TACH Data Register To read the fan speed, both TACH-DATA-LByte and TACH-DATA-HByte must be read. TACH-DATA-LByte must be read first. This reading causes TACH-DATA-HByte to be frozen until both the high and low byte registers have been read from; this method prevents erroneous TACH readings. RPM Measurement Rate The TACH-FAST bit of Configuration Register 4 determines the rate. When TACH-FAST = 1, the TACH-DATA Register is updated every 250ms (fast monitoring). When TACH-FAST = 0 (default), the reading is updated every second (standard monitoring period). Select Number of Pulses/Revolution TACH Mode Selection The TACH-MODE bit of Configuration Register 2 specifies the TACH pulse output mode of the fan. Some fans (such as three- and two-wire) are powered directly by the PWM, and must be PWM-On to provide a TACH pulse output. When the PWM-Out pin switches these fans ON/OFF directly, the PWM-Out must be kept ON to power the fan during the measurement. In this case, the TACH-MODE bit of Configuration Register 2 must be cleared ('0'). When TACH-MODE = 0, the PWM-Out pin is kept ON during the measurement period. Clearing the TACH mode ('0') also enables the internal correction circuitry to correct the error caused by the extra duty cycle applied in the measurement period. The power-on default value of the PWM mode is 0. Clock PWM TACH Pulse Measurement Period for 2 Pulses/Revolution Measurement Period for 4 Pulses Per Revolution TACH Data TACH Output +5V Clock +5V RPM Measurement for TACH-MODE = 0 Signal Conditioning FAN Speed Counter START TACH-EN AMC6821 PWM Control TACH PWM-Out TACH Pulse Measurement Starts Measurement Period for 2 Pulses/Revolution Measurement Period for 4 Pulses Per Revolution RPM Measurement for TACH-MODE = 1 a) Block Diagram of Fan Speed Monitoring b) Measuring the Period of TACH Pulses to Determine the Fan Speed Figure 8. Fan Speed Measurement 15 Submit Documentation Feedback PRODUCT PREVIEW The speed sensor of most common fans provides two or four TACH pulses per revolution. The PSPR bit of Configuration Register 4 specifies how many pulses per revolution are generated. PSPR = 1 indicates four pulses/revolution and PSPR = 0 (default) indicates two pulses/revolution. AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Some fans (such as the four-wire fan from JMC®) are powered directly by dc power, instead of being powered by the PWM. In this case, the TACH mode must be set to '1'. When TACH-MODE = 1, the PWM-Out pin is not forced ON; instead, the status is controlled completely by the DCY register, just as in normal operation. Setting TACH-MODE to '1' also disables the internal correction circuit because no extra duty cycle is applied. Setting the TACH mode to '1' allows TACH reading continuously, regardless of the status of the PWM-Out pin. The selection of the TACH mode affects the RPM monitoring and control. When the TACH-MODE bit is equal to '1', the duty cycle of the PWM-Out pin is always determined by the calculated value; the TACH data are always updated at every RPM monitoring. However, when the TACH-MODE bit is equal to '0', in the Software-RPM Control mode the PWM-Out pin is forced to 30% if the calculated duty cycle is less than 30%; in other modes, the PWM-Out pin is forced to 0% and the TACH data is not updated if the calculated duty cycle is less than 7%. FAN RPM Out-of-Range Detection The larger value of the TACH data corresponds to a slower speed. When the TACH data are larger than the TACH-Low-Limit, the fan runs at a speed below the predefined minimum RPM, and the FANS bit in Status Register 1 is set to '1'. Note that no FANS (fan-slow) detections are made during spin-up. The FANS bit is cleared ('0') only after reading this register and reasserted ('1') in the next monitoring if a fan-slow is detected. After spin-up, FANS is set ('1') even if the TACH data are less than the TACH-Low-Limit until the register is read. When the TACH data are less than the TACH-High-Limit, the fan runs at a speed above the predefined maximum RPM, and the RPM-ALARM bit in Status Register 1 is set ('1'). Note that the RPM-ALARM bit is cleared when reading the register. Once cleared, this bit is not reasserted in the next monitoring cycle even if the condition persists. This bit may be reasserted only if the RPM drops below the allowed maximum speed. When FANS = 1 or RPM-ALARM = 1, there is a fan-out-of-range interrupt and FAN-ORN is generated if the FANIE bit in Configuration Register 1 is set ('1'). This interrupt makes the SMBALERT pin go low. RPM Alarm (TACH is less than the high limit) FANS (TACH is greater than the low limit) (RPM out-of-range) FANIE (FAN-TACH interrupt enabled) FAN-ORN Interrupt PRODUCT PREVIEW Figure 9. RPM Out-of-Range Detection 16 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 FAN FAILURE DETECTION When the TACH data are larger than the TACH low limit, the fan runs at a speed below the predefined minimum RPM. When this condition occurs, a spin-up process is applied to start the fan again when spin-up is enabled. Bits [STIME2:STIME0] of the Fan Characteristics Register define this time period. Figure 10 shows the function of the fan failure detection. The fan speed is measured immediately after spin-up and the TACH-FAST bit of Configuration Register 4 determines the monitoring rate. If the fan does not return to a normal range after five consecutive spin-ups, a FAN-FAILURE occurs, the FAN-FAULT pin goes low when it is enabled (the FAN-FAULT-EN bit of Configuration Register 1 is set), and the spin-up process continues. If the fan returns to a normal speed range before the fifth spin-up, the FAN-FAULT pin does not go low even though the FANS bit is still set to '1'. No FANS (fan-slow) detections are performed during spin-up. Normal Operation of Fan Failure Detection and Spin-Up Yes Bit FANS = 0 During Spin-Up Process No Clear Spin-Up Time Counter No Measure RPM TACH Data > Low Limit Yes Bit FANS = 1 Fan failure, FAN-FAULT pin goes low. Yes Spin-Up Time Count ³ 5 No Spin-Up Time Count +1 Spin-Up Disabled? No Spin-Up if Disabled No Spin-Up Process Yes Measure the RPM continuously once every 0.25s (TACH-FAST bit = 1) or 1s (TACH-FAST = 0), even after a fan failure. However, there are no FANS detections during spin-up. The FAN-FAULT pin is negated if the fan returns to a normal RPM range. Figure 10. Fan Failure Detection and Spin-Up Submit Documentation Feedback 17 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 The SMBALERT pin continues to generate interrupts after the assertion of the FAN-FAULT pin because the tach measurement continues even after a fan failure. Should the fan recover from the failure condition, the FAN-FAULT pin signal is negated and the fan returns to normal operating speed. Figure 11 shows the operation of a FANS interrupt. PWM_OUT 2s 2s 2s Full-Speed TACH/AIN Third TACH Failure INT Status Register Read to Clear Interrupt FAN_FAULT Continuing TACH Failure Fourth TACH Failure Fifth TACH Failure Figure 11. Operation of the FAN-FAULT Pin with a Spin-Up Time = 2 Seconds (INT is a Fan-Slow (FANS) Interrupt Through the SMBALERT Pin) FAN-FAULT PIN The FAN-FAULT pin is an open-drain output pin, as shown in Figure 12. When the FAN-FAULT-EN bit of Configuration Register 1 is cleared ('1'), this pin is disabled and is always in a high-impedance status. When FAN-FAULT-EN = 1, the pin is enabled and the status indicates a fan-failure. The pin asserts low when a fan failure occurs. FAN-FAULT is negated when the fan returns to normal speed. +V AMC6821 10kW Fan Failure (below minimum speed after fifth spin-up) FAN-FAULT PRODUCT PREVIEW Pin is Enabled (FAN-FAULT-EN bit = 1) Figure 12. FAN-FAULT Pin 18 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 FAN CONTROL THERM Pin and External Hardware Control The THERM pin is a bi-direction I/O, as shown in Figure 13. THERM Pin As An Output As an open-drain output, the THERM pin is the indicator of temperature over the THERM limit. When the remote temperature exceeds the Remote-THERM-Limit, or when the local temperature is greater than the Local-THERM-Limit, the THERM pin goes low and remains low until the measured temperature falls 5°C below the exceeded THERM limit. Drive Fan at Full-Speed THERM-FAN-EN L-THERM Bit (Set to ‘1’ when the local temperature is greater than the Local-THERM-Limit.) Local temperature is less than (Local-THERM-Limit - 5°C) Latch Set Output Reset THERM R-THERM Bit (Set to ‘1’ when the remote temperature is greater than the Remote-THERM-Limit.) Remote temperature is less than (Remote-THERM-Limit - 5°C) Latch Set Output Reset THERM-IN bit (Drive fan at full-speed when THERM-IN = 1) Figure 13. Structure of the THERM Pin Submit Documentation Feedback 19 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 When the THERM limit is exceeded, the corresponding status flag bit (R-THERM or L-THERM of Status Register 1 or Status Register 2) is set to '1', and the THERM interrupt through the SMBALERT pin is generated if it is enabled (THERMOVIE of bit Configuration Register 1 is set to '1'). This interrupt forces the SMBALERT pin low. Reading the status registers clears the flag bit (R-THERM and L-THERM). Clearing the flag bit makes the SMBALERT pin go back to high, but does not negate the THERM pin. It remains low until the temperature falls 5°C below the exceeded THERM limit. After this bit is cleared, the active flag bit (R-THERM for remote temperature or L-THERM for local temperature) and the THERM interrupt are not re-armed until the temperature falls 5°C below the exceeded THERM limit. This procedure is shown in Figure 14. THERM Limit 5° Temperature THERM INT via SMBALERT INT via SMBALERT Status Register Read PRODUCT PREVIEW Figure 14. Operation of the THERM Interrupt and the THERM Pin When working as an output, the status of the THERM pin affects the RPM fan. If the THERM-FAN-EN bit is set ('1'), the fan goes to full-speed (that is, the duty cycle is 100%) when the THERM pin goes low. However, when THERM-FAN-EN = 0, the status of the THERM pin does not affect the fan speed. THERM Pin As An Input When this pin works as input, it is the input of the external hardware control signal; the THERM-IN bit of Status Register 2 reflects the input. When the THERM pin is pulled low as an input, THERM-IN is set ('1') and the fan is driven at full speed (that is, the duty cycle is 100%), no matter what THERM-FAN-EN is. The THERM-FAN-EN bit has no effect when the THERM pin works as an input. 20 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Fan Spin-Up The PWM duty cycle controls the cooling fan speed. To spin-up a fan from a stop or under-speed status, the spin-up process is applied to overcome the fan inertia. During the first third of spin-up, the duty cycle of the PWM gradually increases from 33.3% to 100%, and then maintains at 100% through the rest of the process. At the end of the spin-up process, the duty cycle is adjusted to 33.3%. After starting, the fan speed is controlled normally. The spin-up process is shown in Figure 15. The bits [STIME2:STIME0] (bits 2:0 of 0x20) define the spin-up time, from 0.2 seconds to 8 seconds, as shown in Table 6. Fan speed is monitored immediately after the spin-up process. Spin-up is disabled by setting the FSPD bit of the Fan Characteristics Register to '1'. If disabled, the spin-up process is not applied when the fan stops or an RPM is detected below the minimum speed. The TACH low limit register defines the minimum speed. Note that no FANS (fan-slow) detections are performed during spin-up. This bit is cleared ('0') only after reading it, and reasserts '1' in the next monitoring if a fan-slow condition is detected. After spin-up, FANS is set ('1') even if the TACH data are less than the TACH low limit until the flag is read. DCY 100% 33.3% Normal Control 0 TSPIN-UP/3 TSPIN-UP Figure 15. Spin-Up Process Table 6. Spin-Up Time STIME2 0 0 0 0 1 1 1 1 STIME1 0 0 1 1 0 0 1 1 STIME0 0 1 0 1 0 1 0 1 SPIN-UP TIME (seconds) 0.2 0.4 0.6 0.8 1 2 4 8 Submit Documentation Feedback 21 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Normal Fan Speed Control The fan speed is controlled by four different modes: • software DCY control; • software RPM control, • auto remote temperature fan control; • maximum fast-speed calculated control. Bits FDRC1 and FDRC0 in Configuration Register 1 determine the operation mode. Software DCY Control Mode When the bits [FDRC1:FDRC0] = [00] the fan works in the software DCY control mode. The host writes the desired duty cycle value corresponding to the required RPM into the DCY register. In this mode, if the TACH measurement is enabled (bit 2 of 0x01 = 1) and the TACH-MODE bit (bit 1 of 0x01) is cleared ('0'), the duty cycle from the POW-OUT pin is forced to 0% when the value in the DCY register is less than 7%. However, if the TACH measurement is disabled (bit 2 of 0x01 is cleared) or the TACH mode is set ('1'), the DCY register always keeps the programmed value written by the host and is not forced to '0' even when the programmed value is less than 7%. Software-RPM Control Mode This mode is used to maintain the fan at a fixed target speed. It works only when the TACH measurement is enabled (bit 2 of 0x02 = 1). When the bits [FDRC1:FDRC0] = [01] the fan works in the software RPM control mode, as shown in Figure 16. The host writes the proper value into the TACH Setting Register to set the target fan speed. The actual fan speed is monitored by an on-chip fan speed counter, and the result is stored in the TACH-DATA Register (refer to the Fan Speed Measurement section for more details). The actual speed is compared with the setting value. If there is a difference, the duty cycle is adjusted. +V PRODUCT PREVIEW AMC6821 TACH Data + TACH Setting Register DCY Adjustment Fan Speed Counter TACH +V - PWM Control PWM-Out The PWM duty cycle increases if the TACH data is above the setting value, decreases if the TACH data is below the setting, and does not change if the TACH data is equal to the setting (with a tolerance of 0x000A). Figure 16. Software RPM Control The monitoring and adjustment is made once every second, or once every 250ms, as determined by the TACH-FAST bit of Configuration Register 4 (bit 5, 0x04). Bits [STEP1:STEP0] of the DCY-RAMP Register define the allowed amount of each adjustment. When the difference between the values of the TACH-DATA and TACH Setting Registers are equal to or less than 0x000A, the adjustment finishes. 0x000A corresponds to about 1.8% tolerance for 10000RPMs, or 0.9% for 5000RPMs. This measurement architecture is illustrated in Figure 17. In practice, the selected target speed must be not too low to operate the fan. When the TACH-MODE bit (bit 1 of 0x02) is cleared ('0'), the duty cycle of PWM-Out is forced to 30% when the calculated desired value of duty cycle is less than 30%. Therefore, the TACH setting must be not greater than the value corresponding to the RPM for 30% duty cycle. When TACH mode is equal to '1', the TACH setting must not be greater than the value corresponding to the allowed minimum RPM at which the fan runs properly. 22 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Measure RPM and adjust DCY once every second (TACH-FAST = 0) or once every 250ms (TACH-FAST = 1). (TACH-DATA Register) - TACH-SETTING Register) No |Error| > 0x000A Yes (TACH-DATA) > (TACH-SETTING) No Decrease DCY by one STEP Yes Increase DCY by one STEP Figure 17. RPM Fan DCY Loop Auto Temperature Fan Mode The AMC6821 has two auto temperature fan control modes. When the bits [FDRC1:FDRC0] = [10] (default), the fan is in the auto remote fan temperature control mode. The temperature reading from the remote temperature sensor is the active control temperature that controls the PWM duty cycle. When the bits [FDRC1:FDRC0] = [11], the fan is in the maximum fast-speed calculated control mode. The local temperature and the remote temperature have independently-programmed control loops with different parameters. In the maximum fast-speed calculated control mode, the required fan speed is calculated for the remote and local channels, respectively. Whichever control loop calculates the fastest speed based on the measured temperature drives the fan. After start-up, the PWM duty cycle is determined by the actual control temperature. When the temperature is above the low temperature and below the high temperature, the internal control loop automatically adjusts the duty cycle to a proper value according to the measured temperature. When the temperature rises, the duty cycle increases to a higher value; when the temperature drops, the duty cycle reduces. This architecture makes the fan always run at an optimal speed. This adjustment is based on the control-loop parameters defined in the Local TEMP-FAN Control Register, Remote TEMP-FAN Control Register, and the DCY-RAMP Register. Changing the parameters changes the desired value of the duty cycle and the fan speed. +V The DCY-RAMP Register temperature determines the speed of adjustment. Actual Temperature Temperature-to-DCY Adjustment Temperature Channel PWM Control AMC6821 Figure 18. Auto Fan Temperature Loop Submit Documentation Feedback 23 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 The bits [R-TEMP4:R-TEMP0] of the Remote TEMP-FAN Control Register and the bits [L-TEMP4:L-TEMP0] of the Local TEMP-FAN Control Register are the low temperature bits that define the low temperature of the control loops. Bits [SPL2:SPL0] of these registers are the slope bits that define the increment of the duty cycle when the temprature increases 1°C. The bits [RATE2:RATE0] of the DCY-RAMP Register (bits [4:1], 0x23) specify the updating rate of the duty cycle in the temp-fan control mode, and the bits [STEP1:STEP0] define how much the duty cycle is adjusted by each updating. The high temperature can be calculated by Equation 3: High Temperature + (Low Temperature) ) (100 * Value of DCY−LOW−TEMP Register) Slope (3) 100% Temperature-to-DCY Adjustment Range Duty Cycle DCY-LOW-TEMP (DCY at Low Temperature, Default is 33%) PRODUCT PREVIEW 24 DCY increases when the temperature rises. DCY decreases when the temperature reduces. High Temperature High-Temp-Limit THERM-Limit RPM = 0 0% Low-Temp-Limit LOW-TEMP (Low Temperature) Actual Temperature PSV-Temp (Passive Cooling Temperature) Out-of-Range Out-of-Range Normal Range Figure 19. Active Control Temperature—PWM Duty Cycle When the active control temperature is equal to or below the corresponding low temperature, the duty cycle is equal to the value of the DCY-LOW-TEMP Register and the fan runs at a predefined minimum speed. When the control temperature is equal to or higher than the corresponding high temperature, the PWM duty cycle is set to 100% and the fan runs at full-speed. When the active control temperature is equal to or below the corresponding value of the PSV-Temp Register (the predefined passive cooling temperature), the fan stops and the PWM duty cycle is set to 0. When the actual duty cycle is different from the desired value, the duty cycle is adjusted automatically. When the RAMPE bit of the DCY-RAMP Register is cleared ('0'), the duty cycle changes to the desired value immediately after being calculated. When the RAMPE bit is '1', the duty cycle changes to the new value gradually. The DCY-RAMP Register specifies how quickly the duty cycle changes. The duty cycle can be checked every 0.0625 of a second to every eight seconds, depending on the bits [RATE2:RATE0] bits. It changes 1/255(0.392%) to 4/255 (1.57%) each time, depending on the bits [STEP1:STEP0] bits. When the difference between the actual value and the desired value is equal to or less than the adjustment threshold (as defined by the bits [THRE1:THRE0] bits), the adjustment finishes. See the DCY-RAMP Register for details. When the TACH monitoring is enabled (TACH-EN bit, bit 2 of 0x02, is set to '1') and the TACH-MODE bit (bit 1 of 0x02) is cleared ('0'), the duty cycle is forced to 0% when the calculated value is less than 7%. If the TACH monitoring is disabled (TACH-EN = 0) or the TACH-MODE bit is set ('1'), the duty cycle is always set to the calculated value even if the value is less than 7%. Submit Documentation Feedback Critical-Temp AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 (Update DCY with the rate defined by the bits [RATE2:RATE0] of the DCY ramp register. Read Local Temperature Read Remote Temperature Temperature ³ Local-High-Temp-Limit Yes LTH = 1, LTO = 1 Temperature ³ Remote-High-Temp-Limit Yes RTH = 1, RTO = 1 No Temperature ³ Local-Critical-Temp Yes LTC = 1, OVR is Low No No Temperature ³ Remote-Critical-Temp No Yes RTC = 1, OVR is Low LTL = 1, LTO = 1 Yes Temperature £ Local-Low-Temp-Limit Temperature £ Remote-Low-Temp-Limit No Yes RTL = 1, RTO = 1 No No Update DCY? The temperature updating rate may be faster than the DCY updating rate. Yes Remote Fan Temperature Control Mode No (Maximum fast speed calculated control) Yes Calculate New DCY for the Remote Fan Temperature Control (Remote Fan Temperature Control) Calculate DCY for the remote fan temperature control and local fan temperature control, respectively. Use the larger one as the new DCY. Update DCY Figure 20. Temperature Monitoring Flow Chart Submit Documentation Feedback 25 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 INTERRUPT The AMC6821 provides two interrupt output pins, OVR and SMBALERT. Figure 21 shows the function of the OVR pin and Figure 24 illustrates the function of the SMBALERT pin. Latch LTC Bit (Local temperature reaches the critcal shutdown threshold.) Set Output Local Temperature < (Local-Critical-Temp - 5°C) Reset Latch RTC Bit (Remote temperature reaches the critcal shutdown threshold.) Set Output Remote Temperature < (Remote-Critical-Temp - 5°C) Reset OVR AMC6821 +V RTF (Remote Temperature Sensor Failure) OVREN PRODUCT PREVIEW OVR Pin 26 Figure 21. OVR Pin High Limit Temperature Status Bit Temperature Back in Limit (status bit stays set) SMBALERT Cleared on Read (Temperature below limit) Figure 22. SMBALERT Pin and Status Bits Behavior OVR is an open-drain output pin that works as an over-critical temperature limit (shutdown threshold) indicator and remote sensor failure indicator. Setting the OVREN bit of Configuration Register 4 to '1' enables this pin; clearing OVREN ('0') disables it. When disabled, the OVR pin is in a high-impedance status. When enabled, the status is controlled by the over-critical temperature flag and remote sensor failure flag bits of the Status Registers. When the temperature is over the critical limit (shutdown threshold), the corresponding over-critical limit flag of the Status Register (RTC for the remote channel and LTC for the local channel) is set ('1'). This flag is cleared ('0') when reading the Status Registers. Once cleared, this bit is not reasserted until the temperature falls 5°C below the exceeded critical limit, even if the over-critical limit condition persists. When the temperature is equal to or above the critical temperature limit, the OVR pin is asserted (active low) to indicate this critical condition. As the over-critical temperature limit indicator, the OVR pin remains low once asserted until the measured temperature falls 5°C below the exceeded critical limit. Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 When a remote temperature sensor failure condition is detected (either short-circuit or open-circuit), the remote temperature sensor failure bit (RTF) in Status Register 1 (bit 5, 0x02) is set ('1') and the OVR pin is forced low when the pin is enabled (RTFIE bit of Configuration Register 2 is equal to 1). This value indicates a remote sensor failure condition. Once this condition occurs, the RTF bit remains '1' and the OVR pin stays low until a power-on reset or software reset is issued, regardless if the failure condition continues thereafter. RTF = 1 also generates an RTF interrupt through the SMBALERT pin when RTFIE = 1. SMBALERT Pin The SMBALERT pin is a standard interrupt output defined by SMBus specification revision 2.0. This pin is an open-drain output pin and is shown in Figure 23. SMBALERT Interrupt Behavior When an out-of-limit event occurs, the proper flag bits in the status registers are set ('1'), and the corresponding interrupts are generated, if enabled. When an interrupt is generated, the SMBALERT pin asserts low. The host can poll the device status registers to get the information, or give a response to the SMBALERT interrupt signal. It is important to note how the SMBALERT output and status bits behave when writing interrupt-handler software. Figure 22 shows how the SMBALERT output and status bits behave. Once a limit is exceeded, the corresponding status bit is set to '1'. The status bit remains set until the error condition subsides and the status register gets read. The status bits are referred to as being sticky because they remain set until read by software. This design ensures that out-of-limit events cannot be missed if the software is polling the device periodically. The SMBALERT output remains low for the entire duration that the reading is out of limits and remains low until the status register has been read. This architecture has implications on how software handles the interrupt. High Limit Temperature Cleared on Read (temperature below limit) Sticky Status Bit Temperature Back in Limit (status bit stays set) SMBALERT Interrupt Disabled Interrupt Enabled (SMBALERT Rearmed) Figure 23. How Masking the Interrupt Source Affects SMBALERT HANDLING SMBALERT INTERRUPTS To prevent the system from being tied up while servicing interrupts, it is recommend to handle the SMBALERT interrupt in this manner: 1. Detect the SMBALERT assertion. 2. Enter the interrupt handler. 3. Read the status registers to identify the interrupt source. 4. Disable the interrupt source by clearing the appropriate enable bit in the configuration registers. 5. Take the appropriate action for a given interrupt source. 6. Exit the interrupt handler. 7. Periodically poll the status registers. If the interrupt source bit has cleared, reset the corresponding interrupt enable bit to 1. This makes the SMBALERT output and status bits behave as shown in Figure 23. Submit Documentation Feedback 27 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Individual interrupts can be masked by clearing the corresponding interrupt enable bit in the configuration registers to prevent SMBALERT interrupts. Note that masking an interrupt source only prevents the SMBALERT pin output from being asserted; the appropriate status bit gets set as normal. LTL Bit (Local Temperature £ Local-Low-Temp-Limit) LTH Bit (Local Temperature ³ Local-High-Temp-Limit) (local temperature out-of-range) (Local Temperature Out-of-Range Interrupt) LTOIE Bit (local temperature interrupt enabled) AMC6821 RTL Bit (Remote Temperature £ Remote-Low-Temp-Limit) RTH Bit (Remote Temperature ³ Remote-High-Temp-Limit) (remote temperature out-of-range) RTOIE Bit (remote temperature interrupt enabled) (Remote Temperature Out-of-Range Interrupt) RPM-ALARM Bit (TACH < TACH-High-Limit) FANS Bit (TACH > TACH-Low-Limit) (RPM out-of-range) FANIE Bit (FAN-TACH interrupt enabled) (FAN-ORN interrupt) +V LPSV Bit (PSV interrupt) SMBALERT PSVIE Bit L-THERM Bit (over local THERM interrupt) PRODUCT PREVIEW 28 THERMOVIE Bit R-THERM Bit (over remote THERM interrupt) THERMOVIE Bit INT-EN RTF = 1 (remote sensor failure) RTFIE Bit RTC Bit (remote temperature reaches critical temperature) LTC Bit (local temperature reaches critical temperature) Figure 24. SMBALERT Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 REGISTER MAP All registers are 8-bit. Table 7 shows the memory map. Locations that are marked Reserved read back 0x0000 if they are read by the host. Writing to these locations has no effect. Table 7. Memory Map ADDR NAME R/W DEFAULT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IDENTIFICATION REGISTERS 0 0x3D Device ID Register R 0x21 Device identification number. Always read '0x21'. 0 0x3E Company ID Register R 0x49 Company identification number. CONFIGURATION REGISTERS THERMOVIE 0x00 Configuration Register 1 R/W 0xD4 THERM INT Enable RST 0x01 Configuration Register 2 R/W 0x3D Reset THERM-FANEN 0x3F Configuration Register 3 R/W 0x82 THERM-Fan Control TODIS 0x04 Configuration Register 4 R/W 0x08 Time-Out PSPR Pulse Number LTH LT High L-THERM LT Over Therm TACH-FAST TACH Reading Fast RTF RT Failure LPSV LT Below Therm OVREN OVR Pin EN 1 Part Revision Number 0 Reserved RPMALARM Fan Fast 0 0 0 LPSV Int EN RT Int EN LT Int EN Fan Control Mode PSVIE RTOIE FAN-Fault Pin EN LTOIE PWM Invert RTFIE Remote Failure Int EN 0 RPM Int EN TACH-EN Global Int EN TACHMODE TACH Mode Start Monitor PWM-EN PWM-Out EN FDRC1 FDRC0 FAN-FaultEN PWMINV FANIE INT-EN START 1 0 0 1 0 0 1 0 1 0 0 0 0 1 TACH EN LTL 0x02 Status Register 1 R 0x00 LT Low THERM-IN 0x03 Status Register 2 R 0x00 Therm Input TEMPERATURE MONITORING LT2 0x06 Temp-DATA-LByte R 0x00 R-THERM RT Over Therm LTC LT Over Critical RTL RT Low RTC RT Over Critical RTH RT High 0 Reserved FANS Fan Slow 0 LT1 3 LSBs of Local Reading LT0 0 Reserved 0 RT2 RT1 RT0 3 LSBs of Remote Reading LT6 LT5 LT4 LT3 LT10 (MSB) 0x0A Local-Temp-DATA-HByte R 0x80 LT9 LT8 LT7 The 8 MSBs of newest reading of local temperature sensor. Default = –128°C. RT10 (MSB) RT9 RT8 RT7 RT6 RT5 RT4 RT3 The 8 MSBs of newest reading of remote temperature sensor. Default = –128°C. LT-H10 LT-H9 LT-H8 LT-H7 LT-H6 LT-H5 LT-H4 LT-H3 8 MSBs of upper-bound threshold of out-of-range detection of Local-Temp. 3 LSBs are '0'. Default = +60°C. LT-L10 LT-L9 LT-L8 LT-L7 LT-L6 LT-L5 LT-L4 LT-L3 8 MSBs of lower-bound threshold of the out-of-range detection of Local-Temp. 3 LSBs are '0'. Default = 0°C. LT-T10 LT-T9 LT-T8 LT-T7 LT-T6 LT-T5 LT-T4 LT-T3 0x0B Remote-Temp-DATA-HByte R 0x80 0x14 Local-High-Temp-Limit R/W 0x3C 0x15 Local-Low-Temp-Limit R/W 0x00 0x16 Local-THERM-Limit R/W 0x46 8 MSBs of local THERM temperature limit. 3 LSBs are '0'. When local temperature is equal to or above this limit, L-THERM is detected. Default = +70°C. RT-H10 RT-H9 RT-H8 RT-H7 RT-H6 RT-H5 RT-H4 RT-H3 The 8 MSBs of the upper-bound threshold of the out-of-range detection of Remote-Temp. 3 LSBs are '0'. Default = +80°C. RT-L10 RT-L9 RT-L8 RT-L7 RT-L6 RT-L5 RT-L4 RT-L3 The 8 MSBs of the lower-bound threshold of the out-of-range detection of Remote-Temp. 3 LSBs are '0'. Default = 0°C. RT-T10 RT-T9 RT-T8 RT-T7 RT-T6 RT-T5 RT-T4 RT-T3 0x18 Remote-High-Temp-Limit R/W 0x50 0x19 Remote-Low-Temp-Limit R/W 0x00 0x1A Remote-THERM-Limit R/W 0x64 8 MSBs of Remote THERM temperature limit. 3 LSBs are '0'. When remote temperature is equal to or above this limit, R-THERM is detected. Default = +100°C. LT-C10 LT-C9 LT-C8 LT-C7 LT-C6 LT-C5 LT-C4 LT-C3 0x1B Local-Critical-Temp R/W 0x50 The 8 MSBs of Local Critical temperature shutdown threshold. 3 LSBs are '0'. When the Local-Temp is equal to or above this limit, the LTC interrupt occurs and OVR goes low. Default = +80°C. 0 0 PSV8 PSV7 PSV6 PSV5 PSV4 PSV3 0x1C PSV-Temp R/W 0x00 Passive Cooling Temperature threshold. 3 LSBs and two MSBs are '0'. When the active control-temperature is equal to or below this threshold in Auto Temp-Fan Control, the PWM duty cycle is 0 and the Fan stops. Default = 0°C. Submit Documentation Feedback 29 PRODUCT PREVIEW 0 0 0 0 1 0 AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 REGISTER MAP (continued) Table 7. Memory Map (continued) ADDR NAME R/W DEFAULT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEMPERATURE MONITORING (continued) RT-C10 0x1D Remote-Critical-Temp R/W 0x69 RT-C9 RT-C8 RT-C7 RT-C6 RT-C5 RT-C4 RT-C3 The 8 MSBs of Remote Critical temperature shutdown threshold. 3 LSBs are '0'. When the Remote-Temp is equal to or above this limit, an RCRT interrupt occurs and OVR goes low. Default = +105°C. PWM CONTROLLER FSPD 0x20 FAN-Characteristics R/W 0x1D Spin Dis L-DCY7 0x21 DCY-Low-Temp R/W 0x55 L-DCY6 PWM Frequency Setting L-DCY5 L-DCY4 L-DCY3 L-DCY2 Spin-Up Time Setting L-DCY1 L-DCY0 0 PWM2 PWM1 PWM0 STIME2 STIME1 STIME0 The duty cycle of PWM when the temperature is equal to or below Low-Temp in Auto Temp-Fan Control mode. Default = 0x55, 33.2%. DCY7 (MSB) DCY6 DCY5 DCY4 DCY3 DCY2 DCY1 DCY0 0x22 DCY (Duty Cycle) R/W 0x55 Actual Duty cycle of PWM output. The duty cycle changes immediately after new data is written into this register. 8-bit, 0.39%/bit, range 0%-100%. Default = 33%. In read operation, the returned data is the actual DCY value driving the PWM-Out pin. In write operation, the data written is the actual DCY driving the PWM-Out pin in Software-DCY control mode. In all other control modes, the data is not used to drive the PWM. Instead, it is stored in a temporary register, and is used to control the PWM immediately after the control mode is changed to software-DCY control. RAMPE STEP1 STEP0 RATE2 RATE1 RATE0 THRE1 THRE0 0x23 DCY-RAMP R/W 0x52 Ramp Enable L-TEMP4 DCY Adjustment Step in Auto Fan Control L-TEMP3 L-TEMP2 DCY Update Rate in Auto Temp-Fan Control L-TEMP1 L-TEMP0 L-SLP2 Adjustment Threshold in Auto Temp-Fan Control L-SLP1 L-SLP0 PRODUCT PREVIEW 0x24 Local Temp-Fan Control R/W 0x41 Low Temperature in Auto Local Temp-Fan control. R-TEMP4 R-TEMP3 R-TEMP2 R-TEMP1 R-TEMP0 Slope in Auto Local Temp-Fan control. R-SLP2 R-SLP1 R-SLP0 0x25 Remote Temp-Fan Control R/W 0x61 Low Temperature in Auto Remote Temp-Fan control. Slope in Auto Remote Temp-Fan control. TACH (RPM) MEASUREMENT TACH-DATA7 0x08 TACH-DATA-LByte R 0x00 TACHDATA15 TACHDATA6 TACHDATA5 TACHDATA4 TACHDATA3 TACHDATA2 TACHDATA1 TACHDATA0 Low byte of TACH measurement. 0x09 TACH-DATA-HByte R 0x00 TACHDATA14 TACHDATA13 TACHDATA12 TACHDATA11 TACHDATA10 TACHDATA9 TACHDATA8 High byte of TACH measurement. TACH-LowLimit7 0x10 TACH-Low-Limit-LByte R/W 0xFF TACH-LowLimit6 TACH-LowLimit5 TACH-LowLimit4 TACH-LowLimit3 TACH-LowLimit2 TACH-LowLimit1 TACH-LowLimit0 Low byte of TACH count limit corresponding to minimum allowed RPM. Since the TACH circuit counts between TACH pulses, a slow fan results in a larger measured value. When the measured value is larger than TACH-Low-Limit, the fan runs below the allowed minimum speed limit. TACH-LowLimit15 TACH-LowLimit14 TACH-LowLimit13 TACH-LowLimit12 TACH-LowLimit11 TACH-LowLimit10 TACH-LowLimit9 TACH-LowLimit8 0x11 TACH-Low-Limit-HByte R/W 0xFF High byte of TACH Limit corresponding to minimum allowed RPM. TACH-HighLimit7 0x12 TACH-High-Limit-LByte R/W 0x00 TACH-HighLimit6 TACH-HighLimit5 TACH-HighLimit4 TACH-HighLimit3 TACH-HighLimit2 TACH-HighLimit1 TACH-HighLimit0 Low byte of TACH count Limit corresponding to maximum allowed RPM. Since the TACH circuit counts between TACH pulses, a fast fan results in a small measured value. When the measurement is less than this limit, the fan runs above the allowed maximum speed limit. TACH-HighLimit15 TACH-HighLimit14 TACH-HighLimit13 TACH-HighLimit12 TACH-HighLimit11 TACH-HighLimit10 TACH-HighLimit9 TACH-HighLimit8 0x13 TACH-High-Limit-HByte R/W 0x00 High byte of TACH limit corresponding to maximum allowed RPM. TACHSETTING7 0x1E TACH-SETTING-LByte R/W 0xFF Low byte of TACH value corresponding to the predetermined target fan speed. TACH-SETTING must be not greater than the value corresponding to the RPM for 30% duty cycle when the TACH-MODE bit is cleared ('0'). TACHSETTING15 0x1F TACH-SETTING-HByte R/W 0xFF High byte of TACH value corresponding to the predetermined fan speed. TACH-SETTING must be not greater than the value corresponding to the RPM for 30% duty cycle when the TACH-MODE bit is cleared ('0'). 0x3A 0x3B Reserved Reserved R R 0x00 0x00 Always read '0'. Always read '0'. TACHSETTING14 TACHSETTING13 TACHSETTING12 TACHSETTING11 TACHSETTING10 TACHSETTING9 TACHSETTING8 TACHSETTING6 TACHSETTING5 TACHSETTING4 TACHSETTING3 TACHSETTING2 TACHSETTING1 TACHSETTING0 30 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 REGISTER DESCRIPTION In this section, all interrupts are the interrupt signal through the SMBALERT pin, unless otherwise noted. DEVICE CONFIGURATION REGISTERS Configuration Register 1 (Address 0x00, Value After Power-On Reset = 0xD4) BIT 7 6 5 4 NAME THERMOVIE FDRC1 FDRC0 FAN-Fault-EN R/W R/W R/W R/W R/W DEFAULT 1 1 0 1 DESCRIPTION THERM interrupt enable. When this bit is set, the THERM interrupt is enabled. L-THERM = 1 or R-THERM = 1 causes an interrupt. When this bit is cleared ('0'), the THERM interrupt is disabled. When disabled, L-THERM = 1 or R-THERM = 1 does not assert the SMBALERT pin, but forces the THERM pin low. Power-on default = 1. Fan driver control bit 1. Power-on default = 1. Refer to Table 8. Fan driver control bit 0. Power-on default = 0. Refer to Table 8. Setting this pin to '1' enables the FAN-FAULT pin. Clearing this pin ('0') disables the FAN-FAULT pin (always in Hi-Z). Power-on default = 1. PWM invert bit. When PWMINV = 0 (default), the PWM-Out pin goes low for 100% duty cycle (suitable for driving the fan using a PMOS device). Setting PWMINV to '1' makes the PWM-Out pin go high (with an external pull-up resistor) for 100% duty cycle (suitable for driving the fan using a NMOS device). Power-on default = 0. Fan RPM interrupt enable bit. Power-on default = 1. When FANIE = 1, the FAN-RPM interrupt is enabled. FANS = 1 or RPM-ALARM = 1 generates a FANORN interrupt, making the SMBALERT pin go low. When FANIE = 0, a FAN-RPM interrupt is disabled. FANORN = 1 does not generate an interrupt. Setting this bit to '1' enables the interrupt from the SMBALERT pin. Clearing this bit ('0') disables the interrupt. Power-on default = 0. '1' enables monitoring (temperatures and RPM) and PWM outputs. '0' disables monitoring and PWM output. All registers should be programmed by BIOS before setting this bit to 1. Power-on default = 0. 3 PWMINV R/W 0 1 0 INT-EN START R/W R/W 0 0 Table 8. Fan Driver Control Bits FDRC1 1 1 0 0 FDRC0 1 0 0 1 FUNCTION Maximum fast speed calculated by the local temperature-fan control and the remote temperature-fan control. Auto remote-temperature-fan control. The PWM duty cycle is controlled by the remote temperature. Power-on default mode. Software DCY control. Host writes DCY register to set the PWM duty cycle. Software RPM control. Host writes the TACH setting register with the value corresponding to the desired RPM. The device measures the actual RPM and adjusts the PWM duty cycle to maintain the fan speed to the desired value. Submit Documentation Feedback 31 PRODUCT PREVIEW 2 FANIE R/W 1 AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Configuration Register 2 (Address 0x01, Value After Power-On Reset = 0x3D) BIT 7 6 NAME RST PSVIE R/W R/W R/W DEFAULT 0 0 DESCRIPTION Reset bits. RST = 1 resets the device. Self-clears after reset. Always read '0'. Power-on default = 0. LPSV enable bit. Power-on default = 0. When LPSVIE = 1, the LPSV interrupt is enabled and an interrupt is generated when LPSV = 1. When LPSVIE = 0, LPSV is disabled and LPSV = 1 does not cause an interrupt. Remote temperature interrupt enable bit. When RTIE = 1, the remote temperature interrupt is enabled and RTO = 1 causes an interrupt. When RTIE = 0, the remote temperature interrupt is disabled and RTO = 1 does not generate an interrupt. Power-on default = 1, except when a remote sensor failure is detected at power-on. Local temperature interrupt enable bit. Power-on default = 1. When LTIE = 1, the local temperature interrupt is enabled and LTO = 1 causes an interrupt. When LTIE = 0, the local temperature interrupt is disabled and LTO = 1 does not generate an interrupt. Remote sensor failure interrupt enable bit. Power-on default = 1. When RTFIE = 1, the remote sensor failure interrupt is enabled and RTF = 1 causes an interrupt through the SMBALERT pin. When RTFIE = 0, the remote sensor failure interrupt is disabled and RTF = 1 does not generate an interrupt. Setting this bit to '1' enables the TACH input. Clearing ('0') disables the TACH input. Power-on default = 1. When the TACH-MODE bit is cleared ('0'), the PWM-Out pin is forced ON during RPM measurement, and internal correction circuitry is enabled to correct the error caused by this extra duty cycle. Making TACH-MODE = 0 for the fans that are switched ON/OFF directly by the PWM requires PWM ON to provide TACH pulses. In the software RPM mode, the PWM-Out is forced to 30% duty cycle if the calculated duty cycle is less than 30% when TACH-MODE = 0. In all other modes the PWM-Out is forced to 0% if the calculated duty cycle is less than 7%. When the TACH mode is set ('1'), the internal correction circuit is disabled and PWM-Out is not forced ON. Instead, the PWM-Out pin is completely controlled by the value of the DCY register, just as in normal operation. Setting the TACH-MODE bit ('1') when the fans can provide TACH pulses output regardless the status of the PWM-Out pin. The TACH mode must be '1' for any fan which is powered directly by dc power, such as a four-wire fan. Power-on default = 0. (See the TACH-DATA Register section for details.) Setting this bit to '1' enables the PWM-Out pin. Clearing ('0') disables the PWM-Out pin (H-Z). Power-on default = 1. 5 RTOIE R/W 1 4 LTOIE R/W 1 3 RTFIE R/W 1 2 TACH-EN R/W 1 PRODUCT PREVIEW 1 TACH-MODE R/W 0 0 PWM-EN R/W 1 Configuration Register 3 (Address 0x3F, Value After Power-On Reset = 0x82) BIT NAME R/W DEFAULT DESCRIPTION Setting this bit to 1 enables the fan to run at full-speed when the THERM pin (as an output) is asserted low. This configuration allows the system to be run in performance mode. Clearing this bit to '0' disables the fan from running at full-speed whenever the THERM pin (as an output) is asserted low. This configuration allows the system to run in silent mode. Note that this bit has no effect whenever THERM is pulled low as an input. The fan always runs at full speed when the THERM pin is pulled low as an input. Power-on default = 1. Read-back '0'. Read-back '0'. Read-back '0'. 0, bit 3 (MSB) of 4-bit revision number. 0, bit 2 of revision number. 0, bit 1 of revision number. 0, bit 0 (LSB) of revision number. 7 THERM-FAN-EN R/W 1 6 5 4 3 2 1 0 Reserved Reserved Reserved Part Revision Number Part Revision Number Part Revision Number Part Revision Number R R R R R R R 0 0 0 0 0 1 0 32 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Configuration Register 4 (Address 0x04, Value After Power-On Reset = 0x08) BIT NAME R/W DEFAULT DESCRIPTION TODIS = 0, SMBus timeout enabled (default); TODIS = 1, SMBus timeout disabled. The AMC6821 includes an SMBus timeout feature. Timeout is enabled (TODIS = 0) if a single clock is held low longer than 30ms (±10%). When this timeout occurs, the AMC6821 releases the bus (stops driving the bus and lets SCLK and SDA float high), resets the communication, and is able to receive new START conditions. When TODIS = 1, timeout is disabled. In this case, when the clock resumes after being held low for longer than 30ms, the AMC6821 continues the bus communication at the current point. Number of pulses per revolution of the fan. Power-on default = 0. PLSPR = 0 for two pulses/revolution (default), PLSPR = 1 for four pulses per revolution. When TACH-FAST = 1, the TACH data reading is updated every 250ms. This monitor is the fast RPM monitor. When TACH-FAST = 0, the TACH data reading is updated every second. Default = 0, power-on default = 0. Setting this bit to '1' enables the OVR pin. Clearing this bit ('0') disables the OVR pin (high-impedance). Default = 0. Read back '1'. Reading this bit returns 1, not 0. Read-back '0'. Read-back '0'. Read-back '0'. 7 TODIS R/W 0 6 5 4 3 2 1 0 PSPR TACH-FAST OVREN Reserved Reserved Reserved Reserved R/W R/W R/W R R R R 0 0 0 1 0 0 0 Submit Documentation Feedback 33 PRODUCT PREVIEW Writing the reserved bit has no effect. AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 DEVICE STATUS REGISTERS Reading the status registers clears the appropriate status bit. Status register bits are sticky (except the RTF bit). Whenever a status bit is set, indicating an out-of-limit condition, it remains set until the event that caused it is resolved and the status register is read. The status bit can only be cleared by reading the status register after the event is resolved. All bits are cleared when reading the register, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle, unless otherwise noted. Status Register 1 (Address 0x02, Value After Power-On or Reset = 0x00) BIT 7 NAME LTL R/W R DEFAULT 0 DESCRIPTION LTL = 1 when the local temperature is less than or equal to the value of the Local-Low-Temp-Limit register. Otherwise, LTL = 0. If the local temperature is still outside the local temperature low limit, this bit reasserts on the next monitoring cycle. LTH = 1 when the local temperature is greater than or equal to the value of the Local-High-Temp-Limit register. Otherwise, LTH = 0. If the local temperature is still outside the local temperature high limit, this bit reasserts on the next monitoring cycle. Remote sensor-failure interrupt. RTF = 1 when the remote temperature sensor fails (short- or open-circuit). RTF = 0 when the remote sensor is in normal condition. When RTF = 1, the OVR.RTF pin is asserted and the remote temperature data register is set to 0x800 (–128°C). RTF = 1 also generates an interrupt through the SMBALERT pin if an interrupt is enabled (RTFIE = 1). Once RTF is set ('1'), it always remains ('1') until power-on reset or software reset occurs, whether or not the failure condition continues. Reading the status register does not clear the RTF bit. Remote temperature over the remote THERM limit flag. R-THERM = 1 when the temperature is greater than the value of the Remote-THERM-Limit register. Otherwise, R-THERM = 0. When R-THERM = 1, the THERM pin goes low. It also generates a THERM interrupt if THERMOVIE = 1. This bit is cleared on a read of Status Register 1. Once cleared, this bit is not reasserted until the remote temperature falls 5°C below this THERM limit, even if the THERM condition persists. Refer to the THERM Pin and External Hardware Control section. RTL = 1 when the remote temperature is less than or equal to the value of the Remote-Low-Temp-Limit register. Otherwise, RTL = 0. If the remote temperature is still beyond the remote temperature low limit, this bit reasserts on the next monitoring cycle. RTH = 1 when the remote temperature is greater than or equal to the value of Remote-High-Temp-Limit register. Otherwise, RTH = 0. If the remote temperature is still beyond the remote temperature high limit, this bit reasserts on the next monitoring cycle. Fan-slow flag. FANS = 1 if the TACH data are greater than or equal to the value of the TACH-Low-Limit register. This bit indicates if the fan becomes stuck or goes under the minimum speed. FANS = 0 if the TACH data are smaller than the TACH low limit. This bit is cleared ('0') only after reading this register, and reasserts '1' in the next monitoring if a fan-slow is detected. After spin-up, FANS is set ('1') even if the TACH data are less than the TACH low limit until the register is read. FANS = 1 generates a FAN-ORN interrupt through the SMBALERT pin if FANORN is enabled (FANIE = 1). Five consecutive fan-slow returns results in a FAN FAILURE status; which asserts the FAN-FAULT pin low. This interrupt is a non-maskable interrupt (see the FAN-FAULT PIN section for details). Note that a no-FANS (fan-slow) detection is made during spin-up. RPM-ALARM = 1 when the TACH data are less than or equal to the value of the TACH-High-Limit register. This means the RPM is over the maximum limit defined by the TACH high limit. Otherwise, RPM-ALARM = 0. This bit is cleared when reading this register. Once cleared, this bit is not reasserted on the next monitoring cycle even if the condition still persists. This bit may be reasserted only if the RPM drops below the allowed maximum speed. RPM-ALARM = 1 generates a FANORN (fan-out-of-range) interrupt through the SMBALERT pin if FANORN is enabled (FANIE = 1), but does not cause an interrupt through the FAN-FAULT pin. 6 LTH R 0 5 RTF R 0 PRODUCT PREVIEW 34 4 R-THERM R 0 3 RTL R 0 2 RTH R 0 1 FANS R 0 0 RPM-ALARM R 0 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Status Register 2 (Address 0x03, Value After Power-On or Reset = 0x00) BIT 7 NAME THERM-IN R/W R DEFAULT 0 DESCRIPTION Status of the THERM pin as an input. When this input is pulled low, THERM-IN = 1, and the fan is driven at full speed. This bit is cleared when reading this register. Local temperature over the local THERM limit flag. L-THERM = 1 when the local temperature is greater than the value of the Local-THERM-Limit register. Otherwise, L-THERM = 0. When L-THERM = 1, the THERM pin goes low. It also generates a THERM interrupt through the SMBALERT pin, if enabled (THERMOVIE = 1). This bit is cleared on a read of Status Register 1. Once cleared, this bit is not reasserted until the temperature falls 5°C below the THERM limit, even if the THERM condition persists. Refer to the THERM Pin and External Hardware Control section. Active control temperature below the PSV (passive cooling) temperature flag. This bit is set to '1' when the active control temperature is equal to or below the PSV temperature. Otherwise, this bit is cleared ('0'). LPSV = 1 generates a PSV interrupt on the SMBALERT pin, if enabled (PSVIE = 1). This bit is cleared when reading this register. If the active control temperature remains equal to or below the PSV temperature, this bit reasserts on the next monitoring cycle. Local temperature over the local critical temperature flag. This bit is set ('1') when the local temperature is equal to or above the local critical temperature. LTC = 0 if the local critical temperature is below this value. LTC = 1 asserts the OVR pin low and generates an LTC interrupt (non-maskable) though the SMBALERT pin. This bit is cleared when reading this register. If the over-critical limit condition persists, this bit reasserts on the next monitoring cycle. Remote temperature over the remote critical temperature flag. This bit is set to '1' when the remote temperature is equal to or above the remote critical temperature. RTC = 0 if the remote critical temperature is below this value. RTC = 1 asserts the OVR pin low and generates an RTC interrupt (non-maskable) though the SMBALERT pin. This bit is cleared when reading this register. If the over-critical limit condition persists, this bit reasserts on next monitoring cycle. Reserved. Reading returns '0'. Reserved. Reading returns '0'. Reserved. Reading returns '0'. 6 L-THERM R 0 5 LPSV R 0 4 LTC R 0 3 RTC R 0 2 1 0 Reserved Reserved Reserved R R R 0 0 0 FAN CONTROLLER REGISTERS DCY (Duty Cycle) Register (Address 0x22, Value After Power-On or Reset = 0x55) BIT 7 (MSB) 6 5 4 3 2 1 0 NAME DCY7 (MSB) DCY6 DCY5 DCY4 DCY3 DCY2 DCY1 DCY0 DEFAULT 0 1 0 1 0 1 0 1 DESCRIPTION DCY CODE 0x00 0x01 ... ... 0x40 ... ... 0x80 ... ... 0xFF DUTY CYCLE 0% 0.392% ... ... 25% ... ... 50% ... ... 100% The DCY register stores the value of the PWM duty cycle, 0x00 corresponds to 0%, and 0xFF to 100%. 1LSB corresponds to 0.392%. Power-on default = 0x55, 33.2%. In reading operation, the returned data are the actual duty cycle (DCY) value driving the PWM-Out pin. In writing operation, the data written is the actual DCY driving the PWM-Out pin in the software DCY control mode. However, in all other control modes, the data being written are not used to drive the PWM. Instead, it is stored in a temporary register, and controls the PWM immediately after the control mode is changed to the software DCY control mode. Submit Documentation Feedback 35 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Fan Characteristics Register (Address 0x20, Value After Power-On or Reset = 0x1D) BIT 7 NAME FSPD DEFAULT 0 DESCRIPTION Fast Spin Disable Bit When FSPD = 1, the fan spin-up process is disabled. When FSPD = 0, the fan spin-up process is enabled. Reserved PWM Frequency Bits PWM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 2 1 0 STIME2 STIME1 STIME0 1 0 1 Spin-Up Time Bit STIME2 0 0 0 0 1 1 1 1 STIME1 0 0 1 1 0 0 1 1 STIME0 0 1 0 1 0 1 0 1 Spin-Up Time (in Seconds) 0.2 0.4 0.6 0.8 1 2 (Default) 4 8 PWM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PWM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PWM Frequency 10Hz 15Hz 23Hz 30Hz (Default) 38Hz 47Hz 62Hz 94Hz 1kHz 10kHz 20kHz 25kHz (Default) 30kHz 40kHz 40kHz 40kHz When PWM-MODE pin is floating or tied to VDD 6 5 4 3 0 PWM2 PWM1 PWM0 0 0 1 1 When PWM-MODE pin is tied to GND PRODUCT PREVIEW 36 This register specifies the PWM frequency and the fan spin-up functions. Fan Spin Disable Bit: FSPD This bit enables or disables the spin-up function. PWM Frequency Bits: [PWM2:PWM0] These bits specify the PWM frequency; the high range (1kHz–40kHz) has a default value of 25kHz, and the low range (10Hz–94Hz) has a default value of 30Hz. The clock frequency is 12.8MHz. The PWM-MODE pin determines which range is selected. When the PWM mode is tied to ground, the high range is selected; otherwise, the low range is selected. Spin-Up Time Bits: [STIME2:STIME0] These bits specify a predetermined time period, or spin-up time, during which the 100% duty cycle is applied to start the fan spinning. These bits are ignored when FSPD = 1. Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 DCY-LOW-TEMP Register (Address 0x21, Value After Power-On or Reset = 0x55, 33.2%) Bit 7 (MSB) L-DCY 7 Bit 6 L-DCY 6 Bit 5 L-DCY 5 Bit 4 L-DCY 4 Bit 3 L-DCY 3 Bit 2 L-DCY 2 Bit 1 L-DCY 1 Bit 0 (LSB) L-DCY 0 This register specifies the duty cycle in Auto Temp-Fan Control mode when the control temperature is less than or equal to the value of the Low Temperature bits in the TEMP-FAN Control Regsiter. Local TEMP-FAN Control Register (Address 0x24, Value After Power-On or Reset = 0x41) BIT 7 6 5 4 3 NAME L-TEMP4 L-TEMP3 L-TEMP2 L-TEMP1 L-TEMP0 DEFAUL T DESCRIPTION 0 1 0 0 0 Low Temperature Bit of Local Sensor L-TEMP4 L-TEMP3 L-TEMP2 L-TEMP1 L-TEMP0 0 0 0 0 ... 0 ... 1 1 2 1 0 L-SLP2 L-SLP1 L-SLP0 0 0 1 L-SLP2 0 0 0 0 1 L-SLP1 0 0 1 1 0 L-SLP0 0 1 0 1 0 32 16 8 4 2 Slope Bits of Local Sensor Slope LSB/°C %/°C 12.55 6.27 3.14 1.57 0.78 Temp Range in °C (DCY 33.3% to 100%) 10.63 (Default) 21.25 42.5 85 0 0 0 0 ... 1 ... 1 1 0 0 0 0 ... 0 ... 1 1 0 0 1 1 ... 0 ... 1 1 0 1 0 1 ... 0 ... 0 1 Low Temp 0°C 4°C 8°C 12°C ... 32°C (Default) ... 120°C 124°C This register specifies the parameters of the local Temperature-Fan Control mode. Low Temperature Bits: [L-TEMP4:L-TEMP0] These bits specify the low temperature of the auto local temperature fan control. In this control mode, the duty cycle is equal to the value of the DCY-LOW-TEMP register when the local temperature is less than or equal to the value defined by bits [L-TEMP4:L-TEMP0]. Slope Bits: [L-SLP2:L-SLP0] These bits define the increment of the duty cycle when the local temperature rises every 1°C in the auto local temperature fan control. Submit Documentation Feedback 37 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Remote TEMP-FAN Control Register (Address 0x25, Value After Power-On or Reset = 0x61) BIT 7 6 5 4 3 NAME R-TEMP4 R-TEMP3 R-TEMP2 R-TEMP1 R-TEMP0 DEFAUL T DESCRIPTION 0 1 1 0 0 Low Temperature Bit of Remote Sensor R-TEMP4 R-TEMP3 R-TEMP2 R-TEMP1 R-TEMP0 0 0 0 0 ... 0 ... 1 1 2 1 0 R-SLP2 R-SLP1 R-SLP0 0 0 1 R-SLP2 0 0 0 0 1 R-SLP1 0 0 1 1 0 R-SLP0 0 1 0 1 0 32 16 8 4 2 0 0 0 0 ... 1 ... 1 1 0 0 0 0 ... 1 ... 1 1 0 0 1 1 ... 0 ... 1 1 Slope LSB/°C %/°C 12.55 6.27 3.14 1.57 0.78 0 1 0 1 ... 0 ... 0 1 Low Temp 0°C 4°C 8°C 12°C ... 48°C (Default) ... 120°C 124°C Slope Bits of Remote Sensor Temp Range in °C (DCY 33.3% to 100%) 10.63 (Default) 21.25 42.5 85 PRODUCT PREVIEW This register specifies the parameters of the Remote Temperature-Fan Control mode. Low Temperature Bits: [R-TEMP 4:R-TEMP0] These bits specify the low temperature of the auto remote temperature fan control. In this control mode, the duty cycle is equal to the value of the DCY-LOW-TEMP register when the remote temperature is less than or equal to the value defined by bits [R-TEMP4:R-TEMP0]. Slope Bits: [R-SLP2:R-SLP0] These bits define the increment of the duty cycle when the remote temperature rises every 1°C in the auto remote temperature fan control. 38 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 DCY-RAMP Register (Address 0x23, Value After Power-On or Reset = 0x52) BIT 7 NAME RAMPE DEFAULT 0 DESCRIPTION Ramp Enable Bit. Ignored in software-RPM control. When RAMPE = 1, Ramp is enabled. The DCY changes to the desired value gradually according to STEP bits and RATE bits. When RAMPE = 0, Ramp is disabled. DCY changes to the desired target value immediately. Default = 0. Adjustment Step Bits. STEP1 0 0 1 1 4 3 2 RATE2 RATE1 RATE0 1 0 RATE2 0 0 0 0 0 1 1 1 1 1 0 THRE1 THRE0 1 0 THRE1 0 0 1 1 RATE1 0 0 1 1 0 0 1 1 THRE0 0 1 0 1 RATE0 0 1 0 1 0 1 0 1 Threshold 1/256 2/256 3/256 (Default) 4/256 STEP0 0 1 0 1 Max Adjustment 1/256 2/256 4/256 (Default) 8/256 DCY Updates/Sec (Auto Temp-Fan CTR) 0.0625 0.125 0.25 1 (Default) 2 4 8 0.5 6 5 STEP1 STEP0 1 0 DCY Updating Rate Bits in Auto Temp-Fan Control Mode. Adjustment Threshold Bits in Auto Temp-Fan Control Mode. This register is ignored in the software DCY control mode. This register determines how fast the PWM duty cycle is adjusted to the desired value when the temperature changes in the automatic temperature-fan control, or when the fan speed varies from the predetermined value in the software RPM control mode. RAMPE: Ramp Enable bit. This bit is ignored in the software RPM control mode. Adjustment Step Bits: [STEP1:STEP0] In the software RPM control, these bits specify the amount that duty cycle changes each time. In the auto fan temperature control mode, these bits are ignored when RAMPE = 0. When RAMPE = 1, these bits define the maximum amount that the duty cycle can change each time if the duty cycle needs to be adjusted. For example, if the current value of the duty cycle is 50% and the desired value is 75%, the total required increment is 25%. If the step is 1/256 (bits [STEP1:STEP0] = '00'), then the duty cycle increases by 1/256 (0.39%) each time the duty cycle is updated, and the duty cycle reaches the desired value (75%) after 64 updates. This takes eight seconds if the update rate is 8/sec (bits [RATE2:RATE0] = '111'), and takes 64 seconds if the update rate is 1/sec. (bits [RATE2:RATE0] = '100'). However, if the step is 2/256, then the time reduces to half. If the required adjustment is less than the value specified by step bits, the actual required value is used. For example, if the current duty cycle is 50%, the required value is 73%, and the step is 4/256, a total of 15 updates are needed. The duty cycle increases 21.875% after the first 14 updates, and increases 1.125% in the last update. Submit Documentation Feedback 39 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Updating Rate Bits: [RATE2:RATE0] These bits define the rate (time/sec) that the duty cycle is recalculated in the auto temp-fan control mode. The value of [RATE2:RATE0] does not affect the ADC conversion rate. Both external and local temperature readings are updated continuously, even if the DCY is updated slowly. The RPM monitoring rate and DCY updating rate in the software RPM control mode are specified by the TACH-FAST bit of Configuration Register 3. The [RATE2:RATE0] bits are ignored in this mode. Adjustment Threshold Bits: [THRE1:THRE0] These bits determine the threshold of the duty cycle adjustment in the auto temp-fan control mode, and are ignored in all other modes. When the auto fan temperature control loop is active, the duty cycle is not adjusted if the required adjustment is less than or equal to the threshold defined by bits [THRE1:THRE0]. This provides a hysteresis to improve the control stability. For example, if the current duty cycle is 50% and the desired value is 71%, the total required increment is 21%. If the step is 4/256 and the threshold is 2/256 (0.78%), the duty cycle reaches 70.31% after 13 updates, 0.6875% less than the desired value. This difference is less than the threshold (0.78%); therefore, the adjustment stops. However, if the threshold is 1/256 (0.39%), then one more update occurs, and the duty cycle increases by 0.39% (1LSB) because 0.39% (1LSB) < 0.6875% < 0.78% (2LSB). Finally, the duty cycle reaches 70.7%, 0.3% less than the desired value because of the limitation of 8-bit resolution. Note that bits [THRE1:THRE0] are ignored in the software RPM control. In this mode, the DCY adjustment stops when the difference between the TACH data and TACH setting is less than or equal to 0x000A. TEMPERATURE DATA REGISTERS Local Temperature Data Register Bits: [LT10:LT0] Bits [LT10:LT0] are the newest local temperature reading. Remote Temperature Register Bits: [RT10:RT0] Bits [RT10:RT0] are the newest remote temperature reading. Temp-DATA-LByte Register (Address 0x06, Value After Power-On or Reset = 0x00) Bit 7 (MSB) LT2 Bit 6 LT1 Bit 5 LT0 (LSB) Bit 4 0 Bit 3 0 Bit 2 RT2 Bit 1 RT1 Bit 0 (LSB) RT0 PRODUCT PREVIEW Bits [LT2:LT0] are the three LSBs of the newest local temperature reading. Bits [RT2:RT0] are the three LSBs of the newest remote temperature reading. Local-Temp-DATA-HByte Register (Address 0x0A, Value After Power-On or Reset = 0x80, –128°C) Bit 7 (MSB) LT10 (MSB) Bit 6 LT9 Bit 5 LT8 Bit 4 LT7 Bit 3 LT6 Bit 2 LT5 Bit 1 LT4 Bit 0 (LSB) LT3 Bits [LT10:LT3] are the eight MSBs of the newest local temperature reading. 40 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Remote-Temp-DATA-HByte Register (Address 0x0B, Value After Power-On or Reset = 0x80, –128°C) Bit 7 (MSB) RT10 (MSB) Bit 6 RT9 Bit 5 RT8 Bit 4 RT7 Bit 3 RT6 Bit 2 RT5 Bit 1 RT4 Bit 0 (LSB) RT3 Bits [RT10:RT3] are the eight MSBs of the newest remote temperature reading. It is important to note that temperature can be read as an 8-bit value (with 1°C resolution) from the Temp-DATA-Hbyte register, or as an 11-bit value (with 0.125°C resolution) from the Temp-DATA-LByte and Temp-DATA-HByte registers. If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order. If the 11-bit measurement is required, this involves a two-register read for each measurement. The Temp-DATA-LByte register (0x06) should be read first. This condition causes all temperature reading registers to be frozen until the Remote-Temp-DATA-HByte Register (0x0B) is read. This architecture also prevents an MSB reading from being updated while the 3LSBs are being read, and vice versa. TEMPERATURE LIMIT REGISTERS Local High Temperature Limit Register: [LT-H10:LT-H0] Local Low Temperature Limit Register: [LT-L10:LT-L0] Local-High-Temp-Limit Register (Address 0x14, Value After Power-On or Reset = 0x3C, +60°C) Bit 7 (MSB) LT-H10 (MSB) Bit 6 LT-H9 Bit 5 LT-H8 Bit 4 LT-H7 Bit 3 LT-H6 Bit 2 LT-H5 Bit 1 LT-H4 Bit 0 (LSB) LT-H3 These bits are the upper bounds of the local temperature. Bits [LT-H2:LT-H0] are always '0'. Local-Low-Temp-Limit Register (Address 0x15, Value After Power-On or Reset = 0x00, 0°C) Bit 7 (MSB) LT-L10 (MSB) Bit 6 LT-L9 Bit 5 LT-L8 Bit 4 LT-L7 Bit 3 LT-L6 Bit 2 LT-L5 Bit 1 LT-L4 Bit 0 (LSB) LT-L3 These bits are the lower bounds of the local temperature. Bits [LT-L2:LT-L0] are always '0'. Local-THERM-Limit Register (Address 0x16, Value After Power-On or Reset = 0x46, +70°C) Bit 7 (MSB) LT-T10 (MSB) Bit 6 LT-T9 Bit 5 LT-T8 Bit 4 LT-T7 Bit 3 LT-T6 Bit 2 LT-T5 Bit 1 LT-T4 Bit 0 (LSB) LT-T3 These bits are the thermal threshold of the local temperature. Bits [LT-T2:LT-T0] are always '0'. Remote-High-Temp-Limit Register (Address 0x18, Value After Power-On or Reset = 0x50, +80°C) Bit 7 (MSB) RT-H10 (MSB) Bit 6 RT-H9 Bit 5 RT-H8 Bit 4 RT-H7 Bit 3 RT-H6 Bit 2 RT-H5 Bit 1 RT-H4 Bit 0 (LSB) RT-H3 These bits are the upper bounds of the remote temperature. Bits [RT-H2:RT-H0] are always '0'. Submit Documentation Feedback 41 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 Remote-Low-Temp-Limit Register (Address 0x19, Value After Power-On or Reset = 0x00, 0°C) Bit 7 (MSB) RT-L10 (MSB) Bit 6 RT-L9 Bit 5 RT-L8 Bit 4 RT-L7 Bit 3 RT-L6 Bit 2 RT-L5 Bit 1 RT-L4 Bit 0 (LSB) RT-L3 These bits are the lower bounds of the remote temperature. Bits [RT-L2:RT-L0] are always '0'. Remote-THERM-Limit Register (Address 0x1A, Value After Power-On or Reset = 0x64, +100°C) Bit 7 (MSB) RT-T10 (MSB) Bit 6 RT-T9 Bit 5 RT-T8 Bit 4 RT-T7 Bit 3 RT-T6 Bit 2 RT-T5 Bit 1 RT-T4 Bit 0 (LSB) RT-T3 These bits are the thermal threshold of the remote temperature. Bits [RT-T2:RT-T0] are always '0'. Local-Critical-Temp Register (Address 0x1B, Value After Power-On or Reset = 0x50, +80°C) Bit 7 (MSB) LT-C10 Bit 6 LT-C9 Bit 5 LT-C8 Bit 4 LT-C7 Bit 3 LT-C6 Bit 2 LT-C5 Bit 1 LT-C4 Bit 0 (LSB) LT-C3 These bits are the critical threshold of the local temperature. Bits [LT-C2:LT-C0] are always '0'. PSV-Temp Register (Address 0x1C, Value After Power-On or Reset = 0x00, 0°C) Bit 7 (MSB) Bit 6 0 Bit 5 PSV8 Bit 4 PSV7 Bit 3 PSV6 Bit 2 PSV5 Bit 1 PSV4 Bit 0 (LSB) PSV3 PRODUCT PREVIEW 0 Bits [PSV10:PSV0] are the passive cooling temperature threshold. Bits PSV10, PSV9, and [PSV2:PSV0] are always '0'. The PSV ranges from 0°C to +64°C. In the auto fan temperature loop, the fan stops and the duty cycle is forced to 0% when the active temperature is equal to or below the PSV temperature. Remote-Critical-Temp Register (Address 0x1D, Value After Power-On or Reset = 0x69, +105°C) Bit 7 (MSB) RT-C10 Bit 6 RT-C9 Bit 5 RT-C8 Bit 4 RT-C7 Bit 3 RT-C6 Bit 2 RT-C5 Bit 1 RT-C4 Bit 0 (LSB) RT-C3 Bits [RT-C10:RT-C0] are the critical threshold of the remote temperature. [Bits RT-C2:RT-C0] are always '0'. 42 Submit Documentation Feedback AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 TACH-DATA Register TACH-DATA-LByte Register (Address 0x08, Power-On Default = 0x00) Bit 7 (MSB) TACH-DATA7 Bit 6 TACH-DATA6 Bit 5 TACH-DATA5 Bit 4 TACH-DATA4 Bit 3 TACH-DATA3 Bit 2 TACH-DATA2 Bit 1 TACH-DATA1 Bit 0 (LSB) TACH-DATA0 TACH-DATA-HByte Register (Address 0x09, Power-On Default = 0x00) Bit 7 (MSB) TACH-DATA15 Bit 6 TACH-DATA14 Bit 5 TACH-DATA13 Bit 4 TACH-DATA12 Bit 3 TACH-DATA11 Bit 2 TACH-DATA10 Bit 1 TACH-DATA9 Bit 0 (LSB) TACH-DATA8 Bits [TACH-DATA15:TACH-DATA0] are the number of clock pulses counted during one fan revolution and represents the period of the fan revolution (refer to the Fan Speed Measurement section). Reading the TACH data register involves a two-register read. The low byte should be read first. This method causes the high byte to be frozen until both the high and low byte registers have been read from, preventing erroneous TACH readings. TACH Setting Register TACH-SETTING-LByte Register (Address 0x1E, Power-On Default = 0xFF) Bit 7 (MSB) Bit 6 Bit 5 TACH-SETTING5 Bit 4 TACH-SETTING4 Bit 3 Bit 2 Bit 1 TACH-SETTING1 Bit 0 (LSB) TACH-SETTING0 TACH-SETTING7 TACH-SETTING6 TACH-SETTING3 TACH-SETTING2 TACH-SETTING-HByte Register (Address 0x1F, Power-On Default = 0xFF) Bit 7 (MSB) TACHSETTING15 Bit 6 TACHSETTING14 Bit 5 TACHSETTING13 Bit 4 TACHSETTING12 Bit 3 TACHSETTING11 Bit 2 TACHSETTING10 Bit 1 TACHSETTING9 Bit 0 (LSB) TACHSETTING8 Bits [TACH-SETTING15:TACH-SETTING0] represent the period of the target fan RPM (in the number of clock pulses counted during one fan revolution). Refer to the Fan Speed Measurement section. Software writes this register to set the target RPM in the Software-RPM Control mode. When the TACH-MODE bit (bit 1, 0x02) is cleared ('0'), the TACH setting must be not greater than the value corresponding to the RPM for a 30% duty cycle. When the TACH mode is equal to '1', the TACH setting must be not greater than the value corresponding to the allowed minimum RPM at which the fan properly runs. Submit Documentation Feedback 43 PRODUCT PREVIEW AMC6821 www.ti.com SBAS386A – MAY 2006 – REVISED MAY 2006 TACH Low Limit Register TACH-Low-Limit-LByte Register (Address 0x10, Power-On Default = 0xFF) Bit 7 (MSB) TACH-Low-Limit7 Bit 6 TACH-Low-Limit6 Bit 5 TACH-Low-Limit5 Bit 4 TACH-Low-Limit4 Bit 3 TACH-Low-Limit3 Bit 2 TACH-Low-Limit2 Bit 1 TACH-Low-Limit1 Bit 0 (LSB) TACH-Low-Limit0 TACH-Low-Limit-HByte Register (Address 0x11, Power-On Default = 0xFF) Bit 7 (MSB) TACH-LowLimit15 Bit 6 TACH-LowLimit14 Bit 5 TACH-LowLimit13 Bit 4 TACH-LowLimit12 Bit 3 TACH-LowLimit11 Bit 2 TACH-LowLimit10 Bit 1 TACH-LowLimit9 Bit 0 (LSB) TACH-LowLimit8 Bits [TACH-Low-Limit15:TACH-Low-Limit0] are the value that corresponds to the predetermined minimum allowable fan speed (RPM). If the value of the TACH data register is greater than this bound, the fan speed is below the minimum allowed RPM. TACH High Limit Register TACH-High-Limit-LByte Register (Address 0x12, Power-On Default = 0x00) Bit 7 (MSB) TACH-HighLimit7 Bit 6 TACH-HighLimit6 Bit 5 TACH-HighLimit5 Bit 4 TACH-HighLimit4 Bit 3 TACH-HighLimit3 Bit 2 TACH-HighLimit2 Bit 1 TACH-HighLimit1 Bit 0 (LSB) TACH-HighLimit0 PRODUCT PREVIEW TACH-High-Limit-HByte Register (Address 0x13, Power-On Default = 0x00) Bit 7 (MSB) TACH-HighLimit15 Bit 6 TACH-HighLimit14 Bit 5 TACH-HighLimit13 Bit 4 TACH-HighLimit12 Bit 3 TACH-HighLimit11 Bit 2 TACH-HighLimit10 Bit 1 TACH-HighLimit9 Bit 0 (LSB) TACH-HighLimit8 Bits [TACH-High-Limit15:TACH-High-Limit0] are the value that corresponds to the predetermined maximum allowable fan speed (RPM). If the value of the TACH data register is smaller than this bound, the fan speed is above the maximum allowed RPM. 44 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 12-May-2006 PACKAGING INFORMATION Orderable Device AMC6821SDBQ AMC6821SDBQR (1) Status (1) PREVIEW PREVIEW Package Type SSOP/ QSOP SSOP/ QSOP Package Drawing DBQ DBQ Pins Package Eco Plan (2) Qty 16 16 100 2500 TBD TBD Lead/Ball Finish Call TI Call TI MSL Peak Temp (3) Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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