AMC7812BSPAP

AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors Check for Samples: AMC7812B FEATURES DESCRIPTION • 12, 12-Bit DACs with Programmable Outputs: – 0 V to 5 V – 0 V to 12.5 V • DAC Shutdown to User-Defined Level • 12-Bit, 500-kSPS ADC with 16 Inputs: – 16 Single-Ended or Two Differential + 12 Single-Ended • Two Remote Temperature Sensors: – ±2°C Accuracy, –40°C to +150°C • One Internal Temperature Sensor: – ±2.5°C Accuracy, –40°C to +125°C • Input Out-of-Range Alarms • 2.5-V Internal Reference • Eight General-Purpose Inputs and Outputs • Configurable I2C-Compatible and SPI™ Interface with 5-V and 3-V Logic • Power-Down Mode • Wide Operating Temperature Range: –40°C to +125°C • Small Packages: 9-mm × 9-mm QFN-64, and 10-mm × 10-mm HTQFP-64 The AMC7812B is a complete analog monitoring and control solution that includes a 16-channel, 12-bit, analog-to-digital converter (ADC), twelve 12-bit digital-to-analog converters (DACs), eight generalpurpose inputs and outputs (GPIOs), two remote temperature sensor channels, and one local temperature sensor channel. 1 2345 The device has an internal +2.5-V reference that can configure the DAC output voltage to a range of either 0 V to +5 V or 0 V to +12.5 V. An external reference can be used as well. Typical power dissipation is 95 mW. The AMC7812B is ideal for multichannel applications where board space, size, and low power are critical. The device is available in either a QFN-64 or HTQFP64 PowerPAD™ package and is fully specified from –40°C to +105°C and operational over the full –40°C to +125°C temperature range. For applications that require a different channel count, additional features, or converter resolutions, Texas Instruments offers a complete family of analog monitor and control (AMC) products. Refer to www.ti.com/amc for more information. Single-Ended/ Differential ADC-REF-IN/CMP RF Power Amplifier Control in Base Stations Test and Measurement Industrial Control General Analog Monitoring and Control Reference (2.5V) REF-OUT REF-DAC Trigger DAC0-OUT DAC-0 ADC DAC1-OUT DAC2-OUT D1+ GPIO-5 D1- GPIO-4 D2+ GPIO-7 DAC3-OUT Control/Limits/Status Registers DAC4-OUT DAC5-OUTDAC6-OUT TEMP/GPIO • • • • Single-Ended APPLICATIONS AMC7812B CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 GPIO D2- DAC7-OUTDAC8-OUT Local Temperature Sensor Remote Temperature Sensor Driver DAC9-OUTDAC10-OUT DAC11-OUT GPIO-6 DAC-11 GPIO-3 GPIO Controller GPIO-0 LOAD-DAC ALARM Out-of-Range Alarms DACs Clear Logic DAC-CLR-0 DAC-CLR-1 RESET AGND3 AGND4 AGND1 AGND2 AVDD2 AVCC AVDD1 A2 CS/A0 SDO/A1 SDI/SDA SPI/I2C IOVDD CNVT DVDD DGND SCLK/SCL Serial Interface Register and Control (SPI/I2C) Control Logic DAV 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Incorporated. SPI, QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT AVDD to GND –0.3 to +6 V DVDD to GND –0.3 to +6 V IOVDD to GND –0.3 to +6 V AVCC to GND –0.3 to +18 V DVDD to DGND –0.3 to +6 V –0.3 to AVDD + 0.3 V Analog input voltage to GND ALARM, GPIO-0, GPIO-1, GPIO-2, GPIO-3, SCLK/SCL, and SDI/SDA to GND –0.3 to +6 V D1+/GPIO-4, D1–/GPIO-5, D2+/GPIO-6, D2–/GPIO-7 to GND –0.3 to AVDD + 0.3 V Digital input voltage to DGND –0.3 to IOVDD + 0.3 V SDO and DAV to GND –0.3 to IOVDD + 0.3 V Operating temperature range –40 to +125 °C Storage temperature range –40 to +150 °C Junction temperature range (TJ max) Electrostatic discharge (ESD) ratings (1) +150 °C Human body model (HBM) 2.5 kV Charged device model (CDM) 1.0 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. THERMAL INFORMATION AMC7812B THERMAL METRIC (1) RGC (QFN) PAP (HTQFP) 64 PINS 64 PINS θJA Junction-to-ambient thermal resistance 24.1 33.7 θJCtop Junction-to-case (top) thermal resistance 8.1 9.5 θJB Junction-to-board thermal resistance 3.2 9.0 ψJT Junction-to-top characterization parameter 0.1 0.3 ψJB Junction-to-board characterization parameter 3.3 8.9 θJCbot Junction-to-case (bottom) thermal resistance 0.6 0.2 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V, internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC PERFORMANCE DAC DC ACCURACY Resolution INL Relative accuracy DNL Differential nonlinearity TUE Total unadjusted error Offset error 12 ±1 LSB TA = –40°C to +125°C, measured by line passing through codes 020h and FFFh ±1.25 LSBs ±1 LSB TA = +25°C, DAC output = 5.0 V ±10 mV TA = +25°C, DAC output = 12.5 V ±30 mV TA = +25°C, DAC output = 0 V to +5 V, code 020h ±2 mV TA = +25°C, DAC output = 0 V to +12.5 V, code 020h ±5 mV TA = –40°C to +125°C, measured by line passing through codes 020h and FFFh ±0.3 Offset error temperature coefficient Gain error Bits TA = –40°C to +105°C, measured by line passing through codes 020h and FFFh ±1 ppm/°C TA = –40°C to +125°C, external reference, output = 0 V to +5 V ±0.025 ±0.15 %FSR TA = –40°C to +125°C, external reference, output = 0 V to +12.5 V –0.15 ±0.3 %FSR Gain temperature coefficient ±2 ppm/°C DAC OUTPUT CHARACTERISTICS Output voltage range (1) Output voltage settling time (2) TA = –40°C to +125°C, VREF = 2.5 V, gain = 2 0 5 V TA = –40°C to +125°C, VREF = 2.5 V, gain = 5 0 12.5 V DAC output = 0 V to +5 V, code 400h to C00h, to 1/2 LSB, from CS rising edge, RL = 2 kΩ, CL = 200 pF 3 Slew rate (2) Short-circuit current (2) Load current µs 1.5 V/µs 30 mA Source within 200 mV of supply, TA = +25°C +10 mA Sink within 300 mV of supply, TA = +25°C –10 mA Full-scale current shorted to ground DAC output = 0 V to +5 V, code B33h. Source and sink with voltage drop < 25 mV, TA = –40°C to +95°C ±8 Capacitive load stability (2) RL = infinite 10 DC output impedance (2) Code 800h Power-on overshoot AVCC 0 V to 5 V, 2-ms ramp Digital-to-analog glitch energy Digital feedthrough Output noise TA = +25°C, at 1 kHz, code 800h, gain = 2, excludes reference mA nF Ω 0.3 5 mV Code changes from 7FFh to 800h, 800h to 7FFh 0.15 nV-s Device is not accessed 0.15 nV-s f = 0.1 Hz to 10 Hz, excludes reference 81 nV/√Hz 8 µVPP DAC REFERENCE INPUT (1) (2) Reference voltage input range TA = –40°C to +125°C, REF-DAC pin Input current (2) VREF = 2.5 V 1 2.6 170 V µA The output voltage must not be greater than AVCC. See the DAC Output section for further details. Sampled during initial release to ensure compliance; not subject to production testing. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 3 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V, internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 2.495 2.5 2.505 UNIT INTERNAL REFERENCE Output voltage TA = +25°C, REF-OUT pin Output impedance Reference temperature coefficient TA = –40°C to +125°C 10 Output current (sourcing and sinking) Output voltage noise TA = +25°C, f = 1 kHz f = 0.1 Hz to 10 Hz V Ω 0.4 25 ppm/°C ±5 mA 260 nV/√Hz 13 µVPP ADC PERFORMANCE ADC DC ACCURACY (for AVDD = 5 V) Resolution 12 Bits INL Integral nonlinearity TA = –40°C to +125°C ±0.5 ±1 LSB DNL Differential nonlinearity TA = –40°C to +125°C ±0.5 ±1 LSB ±1 ±3 LSB Single-Ended Mode Offset error Offset error match Gain error ±0.4 External reference ±1 Gain error match LSB ±5 ±0.4 LSB LSB Differential Mode Gain error External reference, 0 V to (2 × VREF) mode, VCM = 2.5 V ±2 ±5 LSB External reference, 0 V to VREF mode, VCM = 1.25 V ±1 ±5 LSB Gain error match ±0.5 Zero code error ±1 ±3 LSB External reference, 0 V to VREF mode, VCM = 1.25 V ±1 ±3 LSB Zero code error match Common-mode rejection LSB 0 V to (2 × VREF) mode, VCM = 2.5 V ±0.5 At dc, 0 V to (2 × VREF) mode LSB 67 dB External single analog channel, auto mode 500 kSPS External single analog channel, direct mode 167 kSPS SAMPLING DYNAMICS Conversion rate Conversion time (3) External single analog channel Autocycle update rate (3) All 16 single-ended inputs enabled Throughput rate SPI clock, 12 MHz or greater, single channel 2 µs 32 µs 500 kSPS ANALOG INPUT (4) Full-scale input voltage Absolute input voltage Input capacitance (3) DC input leakage current TA = –40°C to +125°C, single-ended, 0 V to VREF 0 VREF V TA = –40°C to +125°C, single-ended, 0 V to (2 × VREF) 0 2 × VREF V TA = –40°C to +125°C, VIN+ – VIN–, fully-differential, 0 V to VREF –VREF +VREF V TA = –40°C to +125°C, VIN+ – VIN–, fully-differential, 0 V to (2 × VREF) –2 × VREF 2 × VREF V TA = –40°C to +125°C GND – 0.2 0 V to VREF mode AVDD + 0.2 118 0 V to (2 × VREF) mode 73 Unselected ADC input V pF pF ±10 µA ADC REFERENCE INPUT (3) (4) 4 Reference input voltage range TA = –40°C to +125°C Input current VREF = 2.5 V 1.2 AVDD 145 V µA Sampled during initial release to ensure compliance; not subject to production testing. VIN+ or VIN– must remain within GND – 0.2 V and AVDD + 0.2 V; see the Analog Inputs section. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V, internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL ADC REFERENCE BUFFER Offset TA = +25°C ±5 mV +125 °C ±2.5 °C ±1.5 °C INTERNAL TEMPERATURE SENSOR Operating range Accuracy –40 AVDD = 5 V, TA = –40°C to +125°C ±1.25 AVDD = 5 V, TA = 0°C to +100°C Resolution Per LSB Conversion rate External temperature sensors are disabled 0.125 °C 15 ms EXTERNAL TEMPERATURE SENSOR (Using 2N3906 external transistor) Operating range Accuracy (5) (6) Resolution Conversion rate per sensor Limited by external diode –40 AVDD = 5 V, TA = 0°C to +100°C, TD = –40°C to +150°C AVDD = 5 V, TA = –40°C to +100°C, TD = –40°C to +150°C Per LSB +150 °C ±1.5 °C ±2 °C 0.125 °C With resistance cancellation (RC bit = '1') 72 93 100 ms Without resistance cancellation (RC bit = '0') 33 44 47 ms IOVDD = +5 V 2.1 0.3 + IOVDD V TA = –40°C to +125°C, IOVDD = +3.3 V 2.2 0.3 + IOVDD V IOVDD = +5 V –0.3 0.8 V TA = –40°C to +125°C, IOVDD = +3.3 V –0.3 0.7 V TA = –40°C to +125°C, IOVDD = +5 V, sinking 5 mA 0.4 V TA = –40°C to +125°C, IOVDD = +3.3 V, sinking 2 mA 0.4 V DIGITAL LOGIC: GPIO (7) (8) and ALARM VIH VIL VOL Input high voltage Input low voltage Output low voltage High-impedance leakage High-impedance output capacitance 5 µA 10 pF DIGITAL LOGIC: All Except SCL, SDA, ALARM, and GPIO VIH VIL Input high voltage Input low voltage IOVDD = +5 V 2.1 0.3 + IOVDD V TA = –40°C to +125°C, IOVDD = +3.3 V 2.2 0.3 + IOVDD V IOVDD = +5 V –0.3 0.8 V TA = –40°C to +125°C, IOVDD = +3.3 V –0.3 0.7 V ±1 µA 5 pF Input current Input capacitance VOH VOL (5) (6) (7) (8) Output high voltage IOVDD = +5 V, sourcing 3 mA 4.8 IOVDD = +3.3 V, sourcing 3 mA 2.9 V V IOVDD = +5 V, sinking 3 mA 0.4 V IOVDD = +3.3 V, sinking 3 mA 0.4 V High-impedance leakage ±5 µA High-impedance output capacitance 10 pF Output low voltage TD is the external diode temperature. Auto conversion mode disabled. For pins GPIO0 to GPIO3, the external pull-up resistor must be connected to a voltage less than or equal to 5.5 V. For pins GPIO4 to GPIO7, the external pull-up resistor must be connected to a voltage less than or equal to AVDD. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 5 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V, internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL LOGIC: SDA, SCL (I2C-Compatible Interface) VIH VIL Input high voltage Input low voltage IOVDD = +5 V 2.1 0.3 + IOVDD V TA = –40°C to +125°C, IOVDD = +3.3 V 2.2 0.3 + IOVDD V IOVDD = +5 V –0.3 0.8 V TA = –40°C to +125°C, IOVDD = +3.3 V –0.3 0.7 V ±5 µA Input current Input capacitance VOL 5 pF IOVDD = +5 V, sinking 3 mA 0 0.4 V TA = –40°C to +125°C, IOVDD = +3.3 V, sinking 3 mA 0 0.4 V High-impedance leakage ±5 µA High-impedance output capacitance 10 pF 100 250 µs 70 µs 100 250 µs Output low voltage TIMING REQUIREMENTS Power-on delay From AVDD , DVDD ≥ 2.7 V and AVCC ≥ 4.5 V to normal operation Power-down recovery time From CS rising edge Reset delay Delay to normal operation from any reset Convert pulse width 20 ns Reset pulse width 20 ns POWER-SUPPLY REQUIREMENTS AVDD AVDD must be ≥ (VREF + 1.2 V) AIDD TA = –40°C to +125°C, AVDD and DVDD combined, normal operation, no DAC load +2.7 7.9 AVCC V 12.5 mA 1.6 IVCC +4.5 AVCC, no load, DACs at code 800h Power dissipation +5.5 TA = –40°C to +125°C, normal operation (9), AVDD = DVDD = 5 V, AVCC = 15 V 95 mA +18 V 6.5 mA 120 mW DVDD +2.7 +5.5 V IOVDD +2.7 +5.5 V Specified performance –40 +105 °C Operating range –40 +125 °C TEMPERATURE RANGE (9) 6 No DAC load, all DACs at 800h and both ADCs at the fastest auto conversion rate. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 FUNCTIONAL BLOCK DIAGRAM Single-Ended Single-Ended/ Differential ADC-REF-IN/CMP AMC7812B CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 Reference (2.5V) REF-OUT REF-DAC Trigger DAC0-OUT DAC-0 ADC DAC1-OUT DAC2-OUT D1+ GPIO-5 DAC3-OUT Control/Limits/Status Registers DAC4-OUT TEMP/GPIO DAC5-OUTDAC6-OUT D1- GPIO-4 D2+ GPIO-7 GPIO D2- DAC7-OUTDAC8-OUT Local Temperature Sensor Remote Temperature Sensor Driver DAC9-OUTDAC10-OUT DAC11-OUT GPIO-6 DAC-11 GPIO-3 GPIO Controller GPIO-0 LOAD-DAC ALARM Out-of-Range Alarms DACs Clear Logic DAC-CLR-0 DAC-CLR-1 RESET AGND4 AGND3 AGND2 AGND1 AVDD2 AVDD1 AVCC A2 SDO/A1 CS/A0 SDI/SDA SCLK/SCL IOVDD CNVT DGND DVDD SPI/I2C Serial Interface Register and Control (SPI/I2C) Control Logic DAV Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 7 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com PIN CONFIGURATIONS DAC7-OUT DAC6-OUT AVDD2 AVDD1 52 51 50 49 AGND1 DAC8-OUT 54 53 AVCC1 AGND2 56 55 REF-DAC REF-OUT 58 57 DAC10-OUT DAC9-OUT 60 59 ALARM DAC11-OUT 62 61 DGND2 DAC-CLR-1 64 63 RGC PACKAGE QFN-64 (TOP VIEW) 41 CH8 CS/A0 9 40 CH7 SDO/A1 10 39 CH6 A2 11 38 CH5 SPI/I2C 12 37 CH4 GPIO-0 13 36 CH3 GPIO-1 14 35 CH2 GPIO-2 15 34 CH1 GPIO-3 16 33 CH0 ADC-GND ADC-REF-IN/CMP D1-/GPIO-4 D1+/GPIO-5 D2-/GPIO-6 D2+/GPIO-7 DAC1-OUT DAC0-OUT AVCC2 DAC2-OUT AGND3 31 8 32 CH9 DVDD 29 42 30 7 27 CH10 IOVDD 28 43 25 6 26 CH11 DGND 23 44 24 5 21 CH12 SCLK/SCL 22 45 AGND4 4 19 CH13 SDI/SDA 20 46 DAC4-OUT 3 DAC3-OUT CH14 CNVT 17 CH15 47 18 48 2 DAC5-OUT 1 DAV DAC-CLR-0 RESET 8 DAC7-OUT DAC6-OUT AVDD2 AVDD1 52 51 50 49 AGND1 DAC8-OUT 54 53 AVCC1 AGND2 56 55 REF-DAC REF-OUT 58 57 DAC10-OUT DAC9-OUT 60 59 ALARM DAC11-OUT 62 61 DGND2 DAC-CLR-1 64 63 PAP PACKAGE HTQFP-64 (TOP VIEW) 12 37 CH4 GPIO-0 13 36 CH3 GPIO-1 14 35 CH2 GPIO-2 15 34 CH1 GPIO-3 16 33 CH0 31 CH5 SPI/I2C 32 38 ADC-GND 11 ADC-REF-IN/CMP CH6 A2 29 39 30 10 D1-/GPIO-4 CH7 SDO/A1 D1+/GPIO-5 40 27 9 28 CH8 CS/A0 D2-/GPIO-6 41 D2+/GPIO-7 8 25 CH9 DVDD 26 42 DAC1-OUT 7 DAC0-OUT CH10 IOVDD 23 43 24 6 AVCC2 CH11 DGND DAC2-OUT 44 21 5 22 CH12 SCLK/SCL AGND4 45 AGND3 4 19 CH13 SDI/SDA 20 46 DAC4-OUT 3 DAC3-OUT CH14 CNVT 17 CH15 47 18 48 2 DAC5-OUT 1 DAV DAC-CLR-0 RESET Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 PIN DESCRIPTIONS NAME NO. A2 11 Slave address selection A2 for I2C when the SPI/I2C pin is low. DESCRIPTION ADC-GND 32 ADC ground. Must be connected to AGND. ADC-REF-IN/CMP 31 External ADC reference input when external VREF is used to drive the ADC. A compensation capacitor connection (connect a 4.7-µF capacitor between this pin and AGND) when internal VREF is used to drive the ADC. AGND1 54 Analog ground AGND2 55 Analog ground AGND3 22 Analog ground AGND4 21 Analog ground ALARM 62 Global alarm. Open-drain output. An external 10-kΩ, pull-up resistor is required. This pin goes low (active) when one (or more) analog channels are out of range. AVCC1 56 Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, and DAC11-OUT, must be tied to AVCC2 AVCC2 23 Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, and DAC5-OUT, must be tied to AVCC1 AVDD1 49 Positive analog power supply AVDD2 50 Positive analog power supply CH0 to CH15 33-48 Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be programmed as differential or single-ended. CNVT 3 External conversion trigger, active low. The falling edge initiates the sampling and conversion of the ADC. CS/A0 9 Chip-select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I2C when the SPI/I2C pin is low. D1–/GPIO4 29 Remote sensor D1 negative input when D1 is enabled; GPIO-6 when D1 is disabled. Pull-up resistor required for output. D1+/GPIO-5 30 Remote sensor D1 positive input when D1 is enabled; GPIO-7 when D1 is disabled. Pull-up resistor required for output. D2–/GPIO-6 27 Remote sensor D2 negative input when D2 is enabled; GPIO-6 when D2 is disabled. Pull-up resistor required for output. D2+/GPIO-7 28 Remote sensor D2 positive input when D2 is enabled; GPIO-7 when D2 is disabled. Pull-up resistor required for output. DAC0-OUT 26 DAC channel 0 output DAC1-OUT 25 DAC channel 1 output DAC2-OUT 24 DAC channel 2 output DAC3-OUT 20 DAC channel 3 output DAC4-OUT 19 DAC channel 4 output DAC5-OUT 18 DAC channel 5 output DAC6-OUT 51 DAC channel 6 output DAC7-OUT 52 DAC channel 7 output DAC8-OUT 53 DAC channel 8 output DAC9-OUT 59 DAC channel 9 output DAC10-OUT 60 DAC channel 10 output DAC11-OUT 61 DAC channel 11 output 17 DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter a clear state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DACdata register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation. DAC-CLR-1 63 DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter a clear state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DACdata register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation. DAV 2 Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion ends. In auto mode, a 1-µs pulse (active low) appears on this pin when a conversion cycle completes (see the Primary ADC Operation and Registers sections for details). DAV stays high when deactivated. DAC-CLR-0 DGND 6 Digital ground DGND2 64 Digital ground DVDD 8 Digital power supply (+3 V to +5 V). Must be the same value as AVDD. GPIO-0 13 GPIO-1 14 GPIO-2 15 GPIO-3 16 General-purpose digital inputs and outputs. These pins are bidirectional open-drain, digital input and output pins, and require an external pull-up resistor. See the General Purpose Input/Output Pins section for more details. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 9 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com PIN DESCRIPTIONS (continued) 10 NAME NO. IOVDD 7 Interface power supply DESCRIPTION REF-DAC 58 DAC reference Input REF-OUT 57 Internal reference output RESET 1 Reset input, active low. A logic low on this pin causes the device to perform a hardware reset. SCLK/SCL 5 Serial clock input of the main serial interface. This pin functions as the SPI clock when the SPI/I2C pin is high. This pin functions as the I2C clock when the SPI/I2C pin is low. SDI/SDA 4 Serial interface data. This pin functions as SDI for the serial peripheral interface (SPI) when the SPI/I2C pin (pin 12) is high. This pin functions as SDA for the I2C interface when the SPI/I2C pin is low. SDO/A1 10 SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I2C when the SPI/I2C pin is low. SPI/I2C 12 Interface selection pin; digital input. When this pin is tied to IOVDD, the SPI is enabled and the I2C interface is disabled. When this pin is tied to ground, the SPI is disabled and the I2C interface is enabled. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 I2C-COMPATIBLE TIMING DIAGRAMS S Sr P S SDA tSU, STA tSU, DAT tBUF tHD, STA tHD, DAT tLOW SCL tSU, STO tHIGH tHD,STA tR tF S = START Condition Sr = Repeated START Condition P = STOP Condition = Resistor Pull-Up Figure 1. Timing for Standard and Fast Mode Devices on the I2C Bus TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes (1) At –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 2.7 V to 5.5 V, unless otherwise noted. STANDARD MODE PARAMETER fSCL (2) MAX MIN MAX UNIT kHz 0 100 0 400 tLOW Low period of the SCL clock 4.7 — 1.3 — µs tHIGH High period of the SCL clock 4.0 — 0.6 — µs tSU, STA Set-up time for a repeated start condition 4.7 — 0.6 — µs tHD, Hold time (repeated) start condition. After this period, the first clock pulse is generated 4.0 — 0.6 — µs Data set-up time 250 — 100 — ns 0 3.45 0 0.9 µs 4.0 — 0.6 — µs — 1000 20 + 0.1 CB (3) 300 ns — (3) STA tSU, DAT tHD, DAT SCL clock frequency FAST MODE MIN 2 Data hold time for I C-bus devices tSU, STO Set-up time for stop condition tR Rise time of both SDA and SCL signals tF Fall time of both SDA and SCL signals tBUF Bus-free time between a stop and start condition CB Capacitive load for each bus line tSP Pulse duration of spike suppressed (1) (2) (3) 300 ns 4.7 300 20 + 0.1 CB — 1.3 — µs — 400 — 400 pF N/A N/A 0 50 ns All values refer to VIHmin and VILmax levels. An SCL operating frequency of at least 1 kHz is recommended to avoid activating the I2C timeout function. See the Timeout Function section for details. CB = total capacitance of one bus line in pF. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 11 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Sr Sr P tFDA tRDA SDA tHD, DAT tSU, STA tHD, STA tSU, STO tSU, DAT SCL tFCL tRCL1(1) tHIGH tLOW tRCL1(1) tRCL tLOW tHIGH = Current Source Pull-Up = Resistor Pull-Up (1) Sr = Repeated START Condition P = STOP Condition First rising edge of the SCL signal after Sr and after each acknowledge bit. Figure 2. Timing for High-Speed (Hs) Mode Devices on the I2C Bus TIMING CHARACTERISTICS: SDA and SCL for Hs Mode (1) At –40°C to +105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 2.7 V to 5.5 V, unless otherwise noted. CB = 10 pF to 100 pF PARAMETER CB = 400 pF MIN MAX MIN MAX UNIT 0 3.4 0 1.7 MHz fSCL (2) SCL clock frequency tSU, STA Setup time for (repeated) start condition 160 — 160 — ns tHD, Hold time (repeated) start condition 160 — 160 — ns tLOW Low period of the SCL clock 160 — 320 — ns tHIGH High period of the SCL clock 60 — 120 — ns tSU, DAT Data setup time 10 — 10 — ns tHD, Data hold time 0 70 0 150 ns STA DAT tRCL Rise time of SCL signal 10 40 20 80 ns tRCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit 10 80 20 160 ns tFCL Fall time of SCL signal 10 40 20 80 ns tRDA Rise time of SDA signal 10 80 20 160 ns tFDA Fall time of SDA signal 10 80 20 160 ns tSU, STO Set-up time for stop condition 160 — 160 — ns 10 100 — 400 pF 0 10 0 10 ns CB tSP (1) (2) (3) 12 (3) Capacitive load for SDA and SCL lines Pulse width of spike suppressed All values refer to VIHmin and VILmax levels. An SCL operating frequency of at least 1 kHz is recommended to avoid activating the I2C timeout function. See the Timeout Function section for details. For bus line loads where CB is between 100 pF and 400 pF, the timing parameters must be linearly interpolated. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 SPI TIMING DIAGRAMS t8 t10 t4 CS t1 t7 t3 SCLK t2 tR tF t5 SDI t6 Bit 23 Bit 0 Bit 1 -- Don’t Care Bit 23 = MSB Figure 3. SPI Single-Chip Write Operation t1 t7 t4 CS t1 SCLK t3 t2 tF t5 t6 Bit 22 Bit 23 SDI tR Bit 0 Bit 23 Read Command Bit 22 t9 SDO Bit 1 Bit 0 Any Command Bit 23 Bit 22 Bit 1 Bit 0 Data Read from the Register Selected in the Previous Read Operation Figure 4. SPI Single-Chip Read Operation t8 t4 CS t1 SCLK t3 t2 tF t5 SDI t7 t6 Bit 23 (A) tR (Command to B) (Command to A) Bit 0 (A) Bit 23 (B) Bit 0 (B) t9 Bit 23 (A) SDO Bit 0 (A) Figure 5. Daisy-Chain Operation: Two Devices Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 13 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TIMING CHARACTERISTICS: SPI Bus (1) (2) At –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 3.0 V to 5.5 V, unless otherwise noted. LIMIT AT TMIN, TMAX PARAMETER fSCLK MIN MAX UNIT Clock frequency, TA = –40°C to +105°C 50 MHz Clock frequency, TA = –40°C to +125°C 25 MHz t1 SCLK cycle time 20 ns t2 SCLK high time 8 ns t3 SCLK low time 8 ns t4 CS falling edge to SCLK rising edge setup time 5 ns t5 Input data setup time 5 ns t6 Input data hold time 4 ns t7 SCLK falling edge to CS rising edge 10 ns t8 Minimum CS high time 30 ns t9 Output data valid time 3 t10 CS rising to next SCLK rising edge 3 (1) (2) 14 20 ns ns Specified by design; not production tested. SDO loaded with 10-pF load capacitance for SDO timing specifications, tR = tF ≤ 5 ns. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) At +25°C, unless otherwise noted. 0 −0.2 −0.4 −0.2 −0.4 −0.6 −0.6 TA = −40°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 0 0 512 1024 1536 2048 Code 2560 3072 3584 TA = −40°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 4096 0 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 −0.2 −0.4 2560 3072 3584 4096 0 −0.2 0 512 1024 1536 2048 Code 2560 3072 3584 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 4096 0 Figure 8. DIFFERENTIAL LINEARITY ERROR vs CODE 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 −0.2 −0.4 512 1024 1536 2048 Code 2560 3072 3584 4096 Figure 9. LINEARITY ERROR vs CODE INL (LSB) DNL (LSB) 2048 Code −0.6 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.8 0 −0.2 −0.4 −0.6 TA = +105°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 1536 −0.4 −0.6 −1 1024 Figure 7. LINEARITY ERROR vs CODE INL (LSB) DNL (LSB) Figure 6. DIFFERENTIAL LINEARITY ERROR vs CODE 512 0 512 1024 1536 2048 Code 2560 3072 3584 4096 −0.6 TA = +105°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 0 Figure 10. DIFFERENTIAL LINEARITY ERROR vs CODE 512 1024 1536 2048 Code 2560 3072 3584 Figure 11. LINEARITY ERROR vs CODE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 4096 15 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC (continued) 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) At +25°C, unless otherwise noted. 0 −0.2 −0.4 −0.2 −0.4 −0.6 −0.6 TA = +25°C Gain = 5 VREF = 2.5V, Internal −0.8 −1 0 0 512 1024 1536 2048 Code 2560 3072 3584 TA = +25°C Gain = 5 VREF = 2.5V, Internal −0.8 −1 4096 0 Figure 12. DIFFERENTIAL LINEARITY ERROR vs CODE 1 1 0.8 0.6 0.6 INL (LSB) DNL (LSB) 1536 0 DNL Min −0.4 3072 3584 4096 INL Max 0.2 0 −0.2 −0.6 Gain = 2 VREF = 2.5V, Internal −0.8 −1 −40 −25 −10 5 20 35 50 65 80 95 INL Min −0.8 −1 −40 110 −25 −10 5 Gain = 2 VREF = 2.5V, Internal 20 TA (°C ) 1 0.8 0.8 0.6 0.6 INL (LSB) 0 −0.2 DNL Min Gain = 5 VREF = 2.5V, Internal −0.8 −10 5 95 110 INL Max 0.2 0 −0.2 INL Min −0.6 −25 80 −0.4 −0.6 −1 −40 65 0.4 DNL Max 0.2 −0.4 50 Figure 15. LINEARITY ERROR vs TEMPERATURE 1 0.4 35 TA (°C ) Figure 14. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DNL (LSB) 2560 −0.4 −0.6 20 35 50 65 80 95 110 Gain = 5 VREF = 2.5V, Internal −0.8 −1 −40 TA (°C ) −25 −10 5 20 35 50 65 80 95 110 TA (°C ) Figure 16. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 16 2048 Code 0.4 DNL Max 0.2 −0.2 1024 Figure 13. LINEARITY ERROR vs CODE 0.8 0.4 512 Figure 17. LINEARITY ERROR vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. 1 1 Ch0 Ch1 Ch2 Ch3 0.8 Ch8 Ch9 Ch10 Ch11 0.6 0.4 0.4 0.2 0.2 0 −0.2 −0.4 −0.2 0 512 1024 1536 2048 Code 2560 3072 3584 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 4096 0 512 1024 1536 2048 Code 2560 3072 3584 4096 Figure 19. LINEARITY ERROR vs CODE 50 60 TA = +25°C Gain = 2 10884 Channels TA = +25°C Gain = 5 10368 Channels 50 Population (%) 40 30 20 10 40 30 20 0.3 0.22 0.26 0.18 0.1 0.14 0.02 0.06 -0.02 -0.1 Gain Error (%FSR) Gain Error (%FSR) Figure 20. GAIN ERROR Figure 21. GAIN ERROR 0.15 0.3 Gain = 5 VREF = 2.5V, Internal 0.2 Gain Error (%FSR) 0.1 0.05 0 −0.05 −0.1 −0.15 −40 -0.06 -0.14 -0.22 -0.18 -0.3 0 0.15 0.11 0.13 0.09 0.05 0.07 0.01 0.03 -0.01 -0.03 -0.05 -0.07 -0.11 -0.09 -0.13 -0.15 10 -0.26 Population (%) Ch9 Ch10 Ch11 0 Figure 18. DIFFERENTIAL LINEARITY ERROR vs CODE Gain Error (%FSR) Ch6 Ch7 Ch8 −0.6 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.8 0 Ch3 Ch4 Ch5 −0.4 −0.6 −1 Ch0 Ch1 Ch2 0.8 INL (LSB) DNL (LSB) 0.6 Ch4 Ch5 Ch6 Ch7 Gain = 2 VREF = 2.5V, Internal −25 −10 5 20 35 50 65 80 95 110 0.1 0 −0.1 −0.2 −0.3 −40 −25 TA (°C ) −10 5 20 35 50 65 80 95 110 TA (°C ) Figure 22. GAIN ERROR vs TEMPERATURE Figure 23. GAIN ERROR vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 17 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC (continued) 0.15 0.3 0.1 0.2 Gain Error (%FSR) 0.05 0 −0.05 0.1 0 −0.1 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.1 −0.15 4.5 6 7.5 9 10.5 12 AVCC (V) 13.5 15 16.5 TA = +25°C Gain = 5 VREF = 2.5V, Internal −0.2 −0.3 18 12 13 Figure 24. GAIN ERROR vs SUPPLY 16 17 18 35 Offset Error (mV) 1.4 1.6 1 1.2 0.8 0.4 0 0.2 -0.2 -0.4 -0.6 -1 0.6 0.5 0.3 0.4 -0.2 0.2 0 0 0 0.1 5 -0.1 5 -0.3 10 -0.4 10 -0.8 15 -1.4 15 20 -1.6 Population (%) 25 20 -0.5 TA = +25°C Gain = 5 VREF = 2.5V, Internal Code = 020h 10884 Channels 30 0.6 TA = +25°C Gain = 2 VREF = 2.5V, Internal Code = 020h 2220 Channels -0.6 Population (%) 25 15 Figure 25. GAIN ERROR vs SUPPLY 35 30 14 AVCC (V) -1.2 Gain Error (%FSR) At +25°C, unless otherwise noted. Offset Error (mV) Figure 26. OFFSET VOLTAGE Figure 27. OFFSET VOLTAGE 2 5 1.5 4 3 Offset Error (mV) Offset Error (mV) 1 0.5 0 −0.5 2 1 0 −1 −2 −1 Gain = 2 VREF = 2.5V, Internal Code = 020h −1.5 −2 −40 −25 −10 5 20 35 50 65 80 95 110 −3 Gain = 5 VREF = 2.5V, Internal Code = 020h −4 −5 −40 TA (°C ) −10 5 20 35 50 65 80 95 110 TA (°C ) Figure 28. OFFSET VOLTAGE vs TEMPERATURE 18 −25 Figure 29. OFFSET VOLTAGE vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. 3 5 3 Offset Error (mV) Offset Error (mV) 2 1 0 −1 TA = +25°C Gain = 2 VREF = 2.5V, Internal Code = 020h −2 −3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 1 −1 TA = +25°C Gain = 5 VREF = 2.5V, Internal Code = 020h −3 −5 18 12 13 14 AVCC (V) 17 18 Figure 31. OFFSET VOLTAGE vs SUPPLY VOLTAGE 3 5 TA = +25°C AVCC = 15V Gain = 2 VREF = 2.5V, Internal Code = 800h 2.7 FFFh FF0h FE0h FC0h F80h 4.95 Voltage Output (V) 2.8 Voltage Output (V) 16 Figure 30. OFFSET VOLTAGE vs SUPPLY VOLTAGE 2.9 2.6 2.5 2.4 2.3 2.2 4.9 4.85 4.8 TA = +25°C AVCC = 5V Gain = 2 VREF = 2.5V, Internal 4.75 2.1 2 −40 −30 −20 −10 0 10 20 30 4.7 40 0 2 4 ILOAD (mA) 10 12 4.9 080h 040h 020h 010h 000h 300 4.7 4.5 IVCC (mA) 250 200 150 50 8 Figure 33. OUTPUT VOLTAGE vs SOURCE CURRENT CAPABILITY 350 100 6 ILOAD (mA) Figure 32. OUTPUT VOLTAGE vs OUTPUT CURRENT Voltage Output (mV) 15 AVCC (V) TA = +25°C AVCC = 15V Gain = 2 VREF = 2.5V, Internal 0 −12 −11 −10 −9 −8 4.3 4.1 3.9 TA = +25°C Gain = 2 VREF = 2V, External Code = 800h 3.7 3.5 −7 −6 −5 −4 −3 −2 −1 0 3.3 4.5 ILOAD (mA) 6 7.5 9 10.5 12 13.5 15 16.5 18 AVCC (V) Figure 34. OUTPUT VOLTAGE vs SINK CURRENT CAPABILITY Figure 35. DAC SUPPLY CURRENT vs DAC SUPPLY VOLTAGE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 19 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. 6.5 6 6.1 5.5 5.8 5 5.1 IVCC (mA) 4.7 4.4 4.5 4 4 All DAC Channels TA = +25°C Gain = 2 VREF = 2.5V, Internal 3.7 3.4 3 0 512 1024 1536 2048 Code 2560 3072 3584 3 −40 4096 −25 −10 5 20 50 65 80 95 110 Figure 37. SUPPLY CURRENT vs TEMPERATURE 60 1400 TA = +25°C 30 Units 50 TA = +25°C Gain = 2 VREF = 2.5V, Internal 1200 1000 Noise (nV/ Hz) 40 30 20 800 600 400 6.5 6.1 6.3 5.9 5.5 5.7 5.1 5.3 4.9 4.5 4.7 4.1 4.3 0 3.9 0 3.5 200 3.7 10 10 100 1k 10k Frequency (Hz) AICC (mA) Figure 38. DAC SUPPLY CURRENT 100k 1M Figure 39. DAC NOISE VOLTAGE vs FREQUENCY 2 20 10 5 0 −5 16 TA = +25°C Gain = 2 VREF = 2.5V, Internal RL= 2KΩ, CL = 250pF DAC Out SS DAC Out LS CS 1.5 1 Small Signal (LSB) TA = +25°C Gain = 2 VREF = 2.5V, Internal Code = 800h 15 VNOISE (µV) 35 TA (°C ) Figure 36. SUPPLY CURRENT vs DAC CODE Population (%) Gain = 2 VREF = 2.5V, Internal Code = 800h 3.5 0.5 14 12 10 0 8 −0.5 6 −1 4 −1.5 2 Large Signal (V) IVCC (mA) 5.4 −10 −15 −2 −20 0 4 8 12 16 −3 20 0 3 6 9 12 0 Time (µs) Time (s) Figure 40. DAC NOISE (0.1 Hz to 10 Hz) 20 Submit Documentation Feedback Figure 41. SETTLING TIME RISING EDGE Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. 2 16 1.5 Small Signal (LSB) 1 0.5 14 12 10 0 8 −0.5 6 −1 4 −1.5 2 −2 −3 0 3 6 9 12 Large Signal (V) TA = +25°C Gain = 2 VREF = 2.5V, Internal RL= 2KΩ, CL = 250pF DAC Out SS DAC Out LS CS 0 Time (µs) Figure 42. SETTLING TIME FALLING EDGE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 21 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: ADC 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) At +25°C, unless otherwise noted. 0 −0.2 −0.4 −0.8 −1 −0.4 TA = +25°C 0V to VREF Mode VREF = 2.5V, Internal Single−Ended Mode −0.6 0 512 1024 1536 2048 Code 2560 3072 3584 0 −0.2 TA = +25°C 0V to VREF Mode VREF = 2.5V, Internal Single−Ended Mode −0.6 −0.8 −1 4096 0 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 −0.2 −0.4 −0.8 −1 0 512 1024 1536 2048 Code 2560 3072 3584 −1 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) 0.8 0.6 −0.8 −1 0 512 1024 1536 2048 Code 2560 3072 3584 4096 0 512 1024 1536 2048 Code 2560 3072 3584 4096 0 −0.2 −0.4 TA = +25°C 0V to VREF Mode VREF = 2.5V, Internal Differential Mode −0.6 −0.8 −1 0 Figure 47. DIFFERENTIAL LINEARITY ERROR vs CODE 22 4096 Figure 46. LINEARITY ERROR vs CODE 0.8 TA = +25°C 0V to VREF Mode VREF = 2.5V, Internal Differential Mode 3584 TA = +25°C 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Single−Ended Mode −0.8 1 −0.6 3072 0 1 −0.4 2560 −0.2 Figure 45. DIFFERENTIAL LINEARITY ERROR vs CODE −0.2 2048 Code −0.6 4096 0 1536 −0.4 TA = +25°C 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Single−Ended Mode −0.6 1024 Figure 44. LINEARITY ERROR vs CODE INL (LSB) DNL (LSB) Figure 43. DIFFERENTIAL LINEARITY ERROR vs CODE 512 Submit Documentation Feedback 512 1024 1536 2048 Code 2560 3072 3584 4096 Figure 48. LINEARITY ERROR vs CODE Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: ADC (continued) 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) At +25°C, unless otherwise noted. 0 −0.2 −0.4 −0.8 −1 0 512 1024 1536 2048 Code 2560 3072 3584 −0.2 −0.4 TA = +25°C 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Differential Mode −0.6 0 TA = +25°C 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Differential Mode −0.6 −0.8 −1 4096 0 Figure 49. DIFFERENTIAL LINEARITY ERROR vs CODE 1 1 0.8 0.6 0.6 1536 0.2 0 −0.2 −0.4 3584 4096 0 −0.2 5 20 35 50 65 80 95 DNL Min 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Single−Ended Mode −0.6 0V to VREF Mode VREF = 2.5V, Internal Single−Ended Mode −1 −40 −25 −10 −0.8 −1 −40 −25 −10 110 125 5 20 TA (°C ) 1 0.8 0.8 80 95 110 125 DNL Max 0.4 DNL (LSB) 0.4 0.2 0 −0.2 0.2 0 −0.2 −0.4 DNL Min −0.6 0V to VREF Mode VREF = 2.5V, Internal Differential Mode −0.8 20 65 0.6 DNL Max 5 50 Figure 52. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 −1 −40 −25 −10 35 TA (°C ) Figure 51. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DNL (LSB) 3072 0.2 −0.4 DNL Min −0.8 −0.4 2560 0.4 DNL (LSB) 0.4 0.6 2048 Code DNL Max DNL Max DNL (LSB) 1024 Figure 50. LINEARITY ERROR vs CODE 0.8 −0.6 512 35 50 65 80 95 110 125 DNL Min 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Differential Mode −0.6 −0.8 −1 −40 −25 −10 TA (°C ) 5 20 35 50 65 80 95 110 125 TA (°C ) Figure 53. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE Figure 54. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 23 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. 1 1 0.8 0.8 0.6 INL Max 0.4 0.4 0.2 0.2 INL (LSB) INL (LSB) 0.6 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Single−Ended Mode 0 −0.2 −0.4 INL Max 0 −0.2 −0.4 −0.6 −0.8 −1 −40 −25 −10 5 20 35 50 65 80 95 INL Min −0.6 0V to VREF Mode VREF = 2.5V, Internal Single−Ended Mode INL Min −0.8 −1 −40 −25 −10 110 125 5 20 TA (°C ) 1 1 0.8 0.6 INL (LSB) INL (LSB) 0 −0.2 −0.4 INL Min 0 −0.2 INL Min −0.6 0V to VREF Mode VREF = 2.5V, Internal Differential Mode −0.8 20 35 50 65 80 95 −0.8 −1 −40 −25 −10 110 125 5 20 TA (°C ) 3 2.5 2 2 1.5 1.5 Gain Error (LSB) Gain Error (LSB) 3 1 0.5 0 −0.5 −1 65 80 95 110 125 1 0.5 0 −0.5 −1 −1.5 −1.5 TA = +25°C VREF = 2.5V, Internal Single−Ended Mode 0V to VREF Mode 0V to (2 ⋅ VREF) Mode 3.1 3.5 3.9 4.3 4.7 5.1 5.5 −2 0V to VREF Mode 0V to (2 ⋅ VREF) Mode −2.5 −3 −40 −25 −10 AVDD (V) 5 20 35 VREF = 2.5V, Internal Single−Ended Mode 50 65 80 95 110 125 TA (°C ) Figure 59. GAIN ERROR vs SUPPLY 24 50 Figure 58. LINEARITY ERROR vs TEMPERATURE 2.5 −3 2.7 35 TA (°C ) Figure 57. LINEARITY ERROR vs TEMPERATURE −2.5 110 125 0.2 −0.4 −2 95 0.4 0.2 5 80 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Differential Mode INL Max 0.6 INL Max −1 −40 −25 −10 65 Figure 56. LINEARITY ERROR vs TEMPERATURE 0.8 −0.6 50 TA (°C ) Figure 55. LINEARITY ERROR vs TEMPERATURE 0.4 35 Figure 60. GAIN ERROR vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. 20 5 4 0V to VREF Mode 0V to (2 ⋅ VREF) Mode 972 Units VREF = 2.5V, Internal Single−Ended Mode 15 2 Population (%) Offset Error (LSB) 3 1 0 −1 −2 10 5 −3 −5 −40 −25 −10 0 5 20 35 50 65 80 95 110 125 480 482 484 486 488 490 492 494 496 498 500 502 504 506 508 510 512 514 516 518 520 −4 TA (dB) Conversion Frequency (kHz) Figure 62. CONVERSION FREQUENCY 540 540 530 530 Conversion Frequency (kHz) Conversion Frequency (kHz) Figure 61. OFFSET vs TEMPERATURE 520 510 500 490 480 520 510 500 490 480 470 470 TA = +25°C 460 2.7 3.1 3.5 3.9 4.3 4.7 5.1 460 −40 −25 −10 5.5 5 20 AVDD (V) 35 50 65 80 95 110 125 TA (°C ) Figure 63. CONVERSION FREQUENCY vs SUPPLY Figure 64. CONVERSION FREQUENCY vs TEMPERATURE 12 12 11 11 AIDD (mA) AIDD (mA) 10 9 8 10 9 7 8 6 TA = +25°C 5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 7 −40 −25 −10 AVDD (V) 5 20 35 50 65 80 95 110 125 TA (°C ) Figure 65. SUPPLY CURRENT vs SUPPLY VOLTAGE Figure 66. SUPPLY CURRENT vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 25 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. 50 8 TA = +25°C 864 Units 7 40 AIDD (mA)) 12 500 11.5 400 11 200 300 Frequency (kHz) 10.5 100 10 0 0 Figure 67. SUPPLY CURRENT vs CONVERSION RATE 26 10 9 Auto Convert Mode Direct Mode With Nap Direct Mode Without Nap 9.5 0 Single Channel all DACs at code 800h 8.5 1 8 2 20 7.5 3 30 7 4 6.5 5 6 Population (%) AIDD (mA) 6 Figure 68. COMBINED AVDD AND DVDD SUPPLY CURRENT Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: INTERNAL REFERENCE At +25°C, unless otherwise noted. 2.505 2.501 10 Units 2.503 Voltage Output (V) Voltage Output (V) 2.5005 2.501 2.499 2.5 2.4995 2.497 TA = +25°C 2.495 −40 −25 −10 5 20 35 50 65 80 95 2.499 2.7 110 125 3.1 3.5 3.9 TA (°C ) 4.3 4.7 5.1 5.5 AVDD (V) Figure 69. OUTPUT VOLTAGE vs TEMPERATURE Figure 70. OUTPUT VOLTAGE vs SUPPLY 50 2.505 TA = -40°C to +105°C 30 Units 40 Population (%) Output Voltage (V) 2.503 2.501 2.499 30 20 10 2.497 Figure 71. OUTPUT VOLTAGE vs OUTPUT CURRENT 25 20 15 10 10 8 5 6 0 4 -5 −2 0 2 ILOAD (mA) -10 −4 -15 −6 -25 0 −8 -20 TA = +25°C 2.495 −10 Temperature Drift (ppm/°C ) Figure 72. OUTPUT VOLTAGE DRIFT 1000 20 TA = +25°C Gain = 2 VREF = 2.5V, Internal 800 TA = +25°C 15 VNOISE (µV) Noise (nV/ Hz) 10 600 400 5 0 −5 −10 200 −15 0 100 1k 10k Frequency (Hz) 100k 1M −20 0 4 8 12 16 20 Time (s) Figure 73. INTERNAL REFERENCE NOISE vs FREQUENCY Figure 74. INTERNAL REFERENCE NOISE (0.1 Hz to 10 Hz) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 27 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: TEMPERATURE SENSOR At +25°C, unless otherwise noted. 2.5 Local Temperature Error (°C ) Remote Temperature Error (°C ) 10 Units QFN Package 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 −40 −25 −10 5 20 35 50 65 80 95 1.5 1 0.5 0 −0.5 −1 −1.5 −2 5 20 35 50 65 80 95 110 125 TA (°C ) G001 Figure 75. LOCAL TEMPERATURE ERROR vs TEMPERATURE Figure 76. REMOTE TEMPERATURE ERROR vs TEMPERATURE 2.5 2.5 Remote Temperature Error (°C) 16 units TQFP Package 2 Local Temperature Error (°C) 10 Units QFN Package Auto Conversion Mode Disabled −2.5 −40 −25 −10 110 125 TA (°C ) 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 −40 −25 −10 5 20 35 50 TA (°C) 65 80 95 110 125 2.0 1.5 16 units TQFP Package Auto Conversion Mode Disabled 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −40 −25 −10 5 20 G000 Figure 77. LOCAL TEMPERATURE ERROR vs TEMPERATURE 35 50 TA (°C) 65 80 95 110 125 G000 Figure 78. REMOTE TEMPERATURE ERROR vs TEMPERATURE TYPICAL CHARACTERISTICS: DIGITAL INPUTS At +25°C, unless otherwise noted. 1.8 TA = +25°C Digital Input = CS 1.6 1.4 IOVDD (mA) 1.2 1 IOVDD = 2.7V IOVDD = 5V 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 Logic Input Voltage (V) 4 4.5 5 Figure 79. SUPPLY CURRENT vs INPUT VOLTAGE 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 THEORY OF OPERATION ADC OVERVIEW The AMC7812B has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary ADC features a 16-channel multiplexer, an on-chip track-and-hold, and a successive approximation register (SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at 500 kSPS and converts the analog channel inputs, CH0 to CH15. The analog input range for the device can be selected as 0 V to VREF or 0 V to (2 × VREF). The analog input can be configured for either single-ended or differential signals. The device has an on-chip 2.5-V reference that can be disabled when an external reference is preferred. If the internal ADC reference is to be used elsewhere in the system, the output must first be buffered. The various monitored and uncommitted input signals are multiplexed into the ADC. The secondary ADC is a part of the temperaturesensing function that converts the analog temperature signals. ANALOG INPUTS The device has 16 uncommitted analog inputs; 12 of these inputs (CH4 to CH15) are single-ended. The inputs for CH0 to CH3 can be configured as four single-ended inputs or two fully-differential channels, depending on the setup of the ADC channel registers, ADC Channel Register 0 and ADC Channel Register 1. See the Registers section for details. Figure 80 shows the device equivalent input circuit. The (peak) input current through the analog inputs depends on the sample rate, input voltage, and source impedance. The current into the device charges the internal capacitor array during the sample period. After this capacitance is fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance to a 12-bit settling level within the acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. AVDD 50W 40W 40pF CH0 AVDD 50W CH3 AVDD 50W Device in Hold Mode CH4 AVDD 50W CH15 50W 40W 40pF ADC-GND Figure 80. Equivalent Input Circuit Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 29 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Single-Ended Analog Input In applications where the signal source has high impedance, TI recommends buffering the analog input before applying it to the ADC. The analog input range can be programmed to be either 0 V to VREF or 0 V to (2 × VREF). In 2 × VREF mode, the input is effectively divided by two before the conversion takes place. Note that the voltage with respect to GND on the ADC analog input pins cannot exceed AVDD. Fully-Differential Input When the device is configured as a differential input, the differential signal is defined as VDM, as shown in Figure 81(a). The differential signal is the equivalent of the difference between the V1 and V2 signals, as shown in Figure 81(b). The common-mode input VCOMMON is equal to (V1 + V2) / 2. When the conversion occurs, only the differential mode voltage (VDM) is converted; the common-mode voltage (VCOMMON) is rejected. This process results in a virtually noise-free signal with a maximum amplitude of –VREF to +VREF for the VREF range, or (–2 × VREF) to (+2 × VREF) for the (2 × VREF) range. The results are stored in straight binary or twos complement format. VDM 2 VCOMMON VIN+ VIN+ V1 VDM 2 VIN- VINV2 (a) (b) Figure 81. Fully-Differential Analog Input PRIMARY ADC OPERATION This section describes the operation of the primary ADC. ADC Trigger Signals (see AMC configuration register 0) The ADC can be triggered externally by the falling edge of the external trigger CNVT, or internally by writing to the ICONV bit in AMC Configuration Register 0. The ADC channel registers specify which external analog channel is converted. When a new trigger activates, the ADC stops any existing conversion immediately and starts a new cycle. For example, the ADC is programmed to sample channel 0 to channel 3 repeatedly (auto-mode). During the conversion of channel 1, an external trigger is activated. The ADC stops converting channel 1 immediately and starts converting channel 0 again, instead of proceeding to convert channel 2. 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Conversion Mode Two types of ADC conversions are available: direct mode and auto mode. The conversion mode (CMODE) bit of the AMC configuration 0 register specifies the conversion mode. In direct mode, each analog channel within the specified group is converted a single time. After the last channel is converted, the ADC enters an idle state and waits for a new trigger. Auto mode is a continuous operation. In auto mode, each analog channel within the specified group is converted sequentially and repeatedly. The flow chart of the ADC conversion sequence in Figure 82 shows the conversion process. Start (Reset) Wait for ADC Trigger First Conversion Yes New Trigger Occurred or CMODE Changed? No Stop Current Conversion Yes Has Input Channel Register been Rewritten? No Yes Has Input Threshold Register been Rewritten? No Yes Is this the Last Conversion? No Yes Direct Mode? Convert Next Channel No Figure 82. ADC Conversion Sequence Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 31 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com The current conversion cycle stops immediately if: • A new trigger is issued. • The conversion mode changes. • Either ADC channel register is rewritten. • Any of the analog input threshold registers are rewritten. When a new external or internal trigger activates, the ADC starts a new conversion cycle. The internal trigger should not be issued at the same time the conversion mode is changed. If a '1' is simultaneously written to the ICONV bit when changing the CMODE bit to '0' or '1', the current conversion stops and immediately returns to the wait for ADC trigger state. Double-Buffered ADC Data Registers Single-Ended Single-Ended/ Differential The host can access all 16, double-buffered ADC data registers, as shown in Figure 83. The conversion result from the analog input with channel address n (where n = 0 to 15) is stored in the ADC-n-data register. When the conversion of an individual channel completes, the data are immediately transferred into the corresponding ADCn temporary (TMPRY) register, the first stage of the data buffer. When the conversion of the last channel completes, all data in the ADC-n TMPRY registers are simultaneously transferred into the corresponding ADC-ndata registers, the second stage of the data buffer. However, if a data transfer is in progress between any ADCn-data register and the AMC shift register, no ADC-n-data registers are updated until the data transfer is complete. The conversion result from channel address n is stored in the ADC-n-data register. For example, the result from channel 0 is stored in the ADC-0-data register, and the result from channel 3 is stored in the ADC-3data register. CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 Out-of-Limit Alarm ADC ADC-0 Temporary ADC-0 Data ADC-7 Temporary ADC-7 Data ADC-15 Temporary ADC-15 Data To Shift Register Input Range Selection ICONV (Internal Trigger) OR CONVERT (External Trigger) DAVF Bit DAV Pin Figure 83. Double-Buffered ADC Structure 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ADC Data Format For a single-ended input, the conversion result is stored in straight binary format. For a differential input, the results are stored in twos complement format. SCLK Clock Noise Reduction To avoid noise caused by the bus clock, TI recommends that no bus clock activity occur for at least the conversion process time immediately after the ADC conversion starts. Programmable Conversion Rate The maximum conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 1. The conversion rate is programmable through the CONV-RATE-[1:0] bits of the AMC configuration register 1. When more than one channel is selected, the conversion rate is divided by the number of channels selected in ADC channel register 0 and ADC channel register 1. In auto mode, the CONV-RATE-[1:0] bits determine the actual conversion rate. In direct mode, the CONV-RATE-[1:0] bits limit the maximum possible conversion rate. The actual conversion rate in direct mode is determined by the rate of the conversion trigger. Note that when a trigger is issued, there may be a delay of up to 4 µs to internally synchronize and initiate the start of the sequential channel conversion process. In both direct and auto modes, when the CONV-RATE-[1:0] bits are set to a value other than the maximum rate ('00'), nap mode is activated between conversions. By activating nap mode, the AIDD supply current is reduced; see Figure 67. Table 1. ADC Conversion Rate CONV-RATE-1 CONV-RATE-0 tACQ (µs) 0 0 0.375 0 1 2.375 1 0 1 1 tCONV (µs) NAP ENABLED THROUGHPUT (Single-Channel Auto Mode) 1.625 No 500 kSPS (default) 1.625 Yes 250 kSPS 6.375 1.625 Yes 125 kSPS 14.375 1.625 Yes 62.5 kSPS Handshaking with the Host (see AMC configuration register 0) The DAV pin and the DAVF (data available flag) bit in AMC configuration register 0 provide handshaking with the host. Pin and bit status depend on the conversion mode (direct or auto); see Figure 84 and Figure 85. In direct mode, after ADC-n-data registers of all selected channels are updated, the DAVF bit in AMC configuration register 0 is set immediately to '1', and the DAV pin is active (low) to signify that new data are available. By reading the ADC-n-data register or restarting via the external CNVT pin, the ADC clears the DAVF bit to '0' and deactivates the DAV pin (high). If an internal convert start (ICONV bit) is used to start the new ADC conversion, an ADC-n-data register must be read after the current conversion completes before a new conversion can be started in order to reset the DAV status. In auto-mode, after the ADC-n-data registers of the selected channels are updated, a pulse of 1 µs (low) appears on the DAV pin to signify that new data are available. However, the DAVF bit is always cleared to '0' in automode. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 33 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com a) External Trigger, Direct Mode: a) Internal Trigger, Direct Mode: SS CNVT Set ICONV bit to ‘1’ First Internal Trigger Read Data Set ICONV bit to ‘1’ Second Internal Trigger DATA SDI First Trigger Read Data Second Trigger Third Trigger DATA DAV DAV Second Conversion of the Channels Specified in the ADC Channel Register First Conversion of the Channels Specified in the ADC Channel Register Second Conversion of the Channels Specified in the ADC Channel Register First Conversion of the Channels Specified in the ADC Channel Register Third Conversion of the Channels Specified in the ADC Channel Register b) External Trigger, Auto Mode: b) Internal Trigger, Auto Mode: CNVT First Trigger SS Set ICONV bit to ‘1’ Internal Trigger 1ms DAV SDI 1m s First Conversion of the Channels Specified in the ADC Channel Register DAV First Conversion of the Channels Specified in the ADC Channel Register Second Conversion Third Conversion Second Conversion of the Channels Specified in the ADC Channel Register Third Conversion of the Channels Specified in the ADC Channel Register Figure 85. ADC External Trigger Figure 84. ADC Internal Trigger Data Available Pin (DAV) DAV is an output pin that indicates the completion of ADC conversions. The DAVF bit in AMC configuration register 0 determines the status of the DAV pin. In direct mode, after the selected group of input channels are converted and the ADC is stopped, the DAVF bit is set to '1' and the DAV pin is driven to logic low (active). In ADC auto mode, each time the group of input channels are sequentially converted, a 1-µs pulse (low) appears on the DAV pin. Convert Pin (CNVT) CNVT is the input pin for the external ADC trigger signal. ADC channel conversions begin on the falling edge of the CNVT pulse. If a CNVT pulse occurs when the ADC is already converting, then the ADC continues converting the current channel. After the current channel completes, the existing conversion cycle finishes and a new conversion cycle starts. The selected channels specified in the ADC channel registers are converted sequentially in order of enabled channels. Analog Input Out-of-Range Detection (see the Analog Input Out-of-Range Alarm Section) The CH0 to CH3 analog inputs and the temperature inputs are implemented with out-of-range detection. When any of these inputs is out of the preset range, the corresponding alarm flag in the status register is set. If any inputs are out of range, the global out-of-range pin (ALARM) goes low. To avoid a false alarm, the device is implemented with false-alarm protection. See the Alarm Operation section for more details. Full-Scale Range of the Analog Input The gain bit of the ADC gain register determines the full-scale range of the analog input. Full-scale range is VREF when ADGn = 0, or (2 × VREF) when ADGn = 1. If a channel pair is configured for differential operation, the input ranges are either ±VREF or ±(2 × VREF). In (2 × VREF) mode, the input is effectively divided by two before the conversion takes place. Each input must not exceed the supply value of AVDD + 0.2 V or AGND – 0.2 V. When the REF-OUT pin is connected to the REF-ADC pin, the internal reference is used as the ADC reference. When an external reference voltage is applied to the REF-ADC pin, the external reference is used as the ADC reference. 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 SECONDARY ADC AND TEMPERATURE SENSOR OPERATION The AMC7812B contains one local and two remote temperature sensors. The temperature sensors continuously monitor the three temperature inputs, and new readings are automatically available every cycle. The on-chip integrated temperature sensor (shown in Figure 86) is used to measure the device temperature. Two remote diode sensor inputs are used to measure the two external temperatures. All analog signals are converted by the secondary ADC that runs in the background at a lower speed. The measurement relies on the characteristics of a semiconductor junction operation at a fixed current level. The forward voltage of the diode (VBE) depends on the current passing through the diode and the ambient temperature. The change in VBE when the diode operates at two different currents (a low current of ILOW and a high current of IHIGH) is shown in Equation 1: IHIGH hkT VBE_HIGH - VBE_LOW = ln q ILOW ( ) where: • • • • k is Boltzmann's constant, q is the charge of the carrier, T is the absolute temperature in Kelvin (K), and η is the ideality of the transistor as a sensor. (1) IHIGH ILOW SW2 SW1 Mux LPF and Signal Conditioning Local Temperature Registers Second ADC and Signal Processing Diode Temperature Sensor Figure 86. Integrated Local Temperature Sensor The remote sensing transistor can be a discrete, small-signal type transistor or a substrate transistor built within the microprocessor. This architecture is shown in Figure 87. An internal voltage source biases the D– terminal above ground to prevent the ground noise from interfering with measurement. An external capacitor (up to 330 pF) may be placed between D+ and D– to further reduce noise interference. ILOW SW1 Remote Temperature Registers IHIGH SW2 D+ Mux D- LPF and Signal Conditioning Second ADC and Signal Processing VBIAS Figure 87. Remote Temperature Sensor Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 35 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com The device has three temperature sensors: two remote (D1 and D2) and one on-chip (LT). If any sensor is not used, it can be disabled by clearing the corresponding enable bit (bits D2EN, D1EN, and LTEN of the temperature configuration register). When disabled, the sensors are not converted. The device continuously monitors the selected temperature sensors in the background, leaving the user free to perform conversions on the other channels. When one monitor cycle finishes, a signal passes to the control logic to automatically initiate a new conversion. The analog sensing signal is preprocessed by a low-pass filter and signal-conditioning circuitry, and then digitized by the ADC. The resulting digital signal is further processed by the digital filter and processing unit. The final result is stored in the LT-temperature-data register, the D1-temperature-data register, and the D2temperature-data register, respectively. The format of the final result is in twos complement, as shown in Table 2. Note that the device measures the temperature from –40°C to +150°C. Table 2. Temperature Data Format 36 TEMPERATURE (°C) DIGITAL CODE +255.875 011111111111 +150 010010110000 +100 001100100000 +50 000110010000 +25 000011001000 +1 000000001000 0 000000000000 –1 111111111000 –25 111100111000 –50 111001110000 –100 110011100000 –150 101101010000 –256 100000000000 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Remote Sensing Diode Errors in remote temperature sensor readings are typically the consequence of the ideality factor and current excitation used by the device versus the manufacturer-specified operating current for a given transistor. Some manufacturers specify a low-level (ILOW) and high-level (IHIGH) current for the temperature-sensing substrate transistors. The AMC7812B uses 6 μA for ILOW and 120 μA for IHIGH. The device is designed to function with discrete transistors, such as the 2N3904 and 2N3906. If an alternative transistor is used, the device operates as specified, as long as the following conditions are met: 1. Base-emitter voltage is greater than 0.25 V at 6 μA, at the highest sensed temperature. 2. Base-emitter voltage is less than 0.95 V at 120 μA, at the lowest sensed temperature. 3. Base resistance is less than 100 Ω. 4. Tight control of VBE characteristics indicated by small variations in hFE (that is, 50 to 150). Ideality Factor The ideality factor (η) is a measured characteristic of a remote temperature sensor diode as compared to an ideal diode. The device allows for different η-factor values, according to Table 3. The device is trimmed for a power-on reset (POR) value of η = 1.008. If η is different, the η-factor correction register can be used. The value (NADJUST) written in this register must be in twos complement format, as shown in Table 3. This value is used to adjust the effective η-factor according to Equation 2 and Equation 3. Table 3. η-Factor Range (Single Byte) NADJUST HEX DECIMAL ηEFF 0111 1111 7F 127 1.747977 0000 1010 0A 10 1.042759 0000 1000 08 8 1.035616 0000 0110 06 6 1.028571 0000 0100 04 4 1.021622 0000 0010 02 2 1.014765 0000 0001 01 1 1.011371 0000 0000 00 0 1.008 1111 1111 FF –1 1.004651 1111 1110 FE –2 1.001325 1111 1100 FC –4 0.994737 1111 1010 FA –6 0.988235 1111 1000 F8 –8 0.981818 1111 0110 F6 –10 0.975484 1000 0000 80 –128 0.706542 BINARY heff = 1.008 ´ 300 300 - NADJUST NADJUST = 300 - (2) 300 ´ 1.008 heff where: • • ηEFF is the actual ideality of the transistor used and NADJUST is the corrected ideality used in the calculation. (3) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 37 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Filtering Figure 88(a) and Figure 88(b) show the connection of recommended NPN or PNP transistors, respectively. Remote junction temperature sensors are usually implemented in a noisy environment. Noise is most often created by fast digital signals, and can corrupt measurements. The AMC7812B has a built-in 65-kHz filter on the D+ and D– inputs to minimize the effects of noise. However, a bypass capacitor placed differentially across the inputs of the remote temperature sensor can make the application more robust against unwanted coupled signals. If filtering is required, the capacitance between D+ and D– should be limited to 330 pF or less for optimum measurement performance. This capacitance includes any cable capacitance between the remote temperature sensor and the device. 2N3906 2N3904 D+ D+ D- D- (a) NPN (b) PNP Figure 88. Remote Temperature Sensor Using Transistor Series Resistance Cancellation Parasitic resistance (in series with the remote diode) to the D+ and D– inputs of the device is caused by a variety of factors, including printed circuit board (PCB) trace resistance and trace length. This series resistance appears as a temperature offset in the remote sensor temperature measurement, and causes more than 0.45°C error per ohm. The device implements a technology to automatically cancel out the effect of this series resistance, thus providing a more accurate result without requiring user characterization of this resistance. With this technology, the device is able to reduce the effects of series resistance to typically less than 0.0075°C per ohm. The resistance cancellation is disabled when the RC bit in the temperature configuration register is cleared ('0'). Reading Temperature Data Temperature is always read as 12-bit data. When the conversion finishes, the temperature is sent to the corresponding temperature-data register. However, if a data transfer is in progress between the temperature-data register and the AMC shift register, the temperature-data register is frozen until data transfer completes. Conversion Time The conversion time depends on the type of sensor and configuration, as shown in Table 4. Table 4. Conversion Times MONITORING CYCLE TIME (ms) PROGRAMMABLE DELAY RANGE (s) Local sensor is active, remote sensors are disabled or in power-down 15 0.48 to 3.84 One remote sensor is active and RC = 0, local sensor and one remote sensor are disabled or in power-down 44 1.40 to 11.2 One remote sensor is active and RC = 1, local sensor and one remote sensor are disabled or in power-down 93 2.97 to 23.8 One remote sensor and local sensor are active and RC = 0, one remote sensor is disabled or in power-down 59 1.89 to 15.1 One remote sensor and local sensor are active and RC = 1, one remote sensor is disabled or in power-down 108 3.45 to 27.65 Two remote sensors are active and RC = 0, local sensor is disabled or in power-down 88 2.81 to 22.5 Two remote sensors are active and RC = 1, local sensor is disabled or in power-down 186 5.95 to 47.6 All sensors are active and RC is '0' 103 3.92 to 26.38 All sensors are active and RC is '1' 201 6.43 to 51.45 TEMPERATURE SENSOR 38 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 REFERENCE OPERATION This section describes the operation of the internal and external references. Internal Reference The device includes a 2.5-V internal reference. The internal reference is externally available at the REF-OUT pin. A 100-pF to 10-nF capacitor is recommended between the reference output and GND for noise filtering. The internal reference is a bipolar transistor-based, precision band-gap voltage reference. The output current is limited by design to approximately 100 mA. The internal reference drives all temperature sensors. When connecting the REF-OUT pin to the REF-DAC pin, the internal reference functions as the DAC reference. The ADC-REF-IN/CMP pin has a dual function. When an external reference is connected to this pin, the external reference is used as the ADC reference. When a compensation capacitor (4.7 µF, typical) is connected between this pin and AGND, the internal reference is used as the ADC reference. When using an external reference to drive the ADC, the ADC-REF-INT bit in AMC configuration register 0 must be cleared ('0') to turn off the ADC reference buffer. When using the internal reference to drive the ADC, the ADC-REF-INT bit in AMC configuration register 0 must be set to '1' to turn on the ADC reference buffer. External Reference Figure 89 shows how the external reference is used as the DAC reference when applied on the DAC-REF pin, and as the ADC reference when applied on the ADC-REF pin. Figure 90 shows the use of the internal reference. CH0 CH1 CH0 CH1 ADC ADC CH14 CH15 Ext. Ref. CH14 CH15 ADC-REF-IN/CMP ADC-REF-IN/CMP Control Logic: Bit ADC-REF-INT = ‘0’ REF-OUT Reference (2.5V) Control Logic: Bit PREF = ‘0’ DAC-0 REF-DAC REF-OUT Reference (2.5V) Control Logic: Bit PREF = ‘1’ Ext. Ref. DAC0-OUT Figure 89. Use of the External Reference Control Logic: Bit ADC-REF-INT = ‘1’ C > 470nF (Minimize Inductance to Pin) DAC-0 REF-DAC DAC0-OUT Figure 90. Use of the Internal Reference Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 39 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com DAC OPERATION The device contains 12 DACs that provide digital control with 12 bits of resolution using an internal or external reference. The DAC core is a 12-bit string DAC and output buffer. The DAC drives the output buffer to provide an output voltage. Refer to the DAC configuration register for details. Figure 91 shows a function block diagram of the DAC architecture. The DAC latch stores the code that determines the output voltage from the DAC string. The code is transferred from the DAC-n-data register to the DAC latch when the internal DAC-load signal is generated. DAC Data Register DAC Latch 12-Bit Resistor String VOUT DAC Load(1) Gain Logic Gain Bits (1) Gain Internal DAC load is generated by writing '1' to the ILDAC bit in synchronous mode. In asynchronous mode, the DAC latch is transparent. Figure 91. DAC Block Diagram Resistor String The resistor string structure is shown in Figure 92. The resistor string consists of a string of resistors, each of value R. The code loaded to the DAC latch determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. This architecture is inherently monotonic, voltage out, and low glitch. The resistor string architecture is also linear because all the resistors are of equal value. R R R To Output Amplifier R R Figure 92. Resistor String 40 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 DAC Output The output range is programmable from 0 V to (2 × VREF) or from 0 V to (5 × VREF), depending on the gain bits in the DAC gain register. The maximum output is AVCC. The output buffer amplifier is capable of generating rail-torail voltages on its output, giving an output range of 0 V to AVCC. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.5 V/μs with a typical 1/4 to 3/4 scale settling time of 3 μs with the output unloaded. Double-Buffered DAC Data Registers There are 12 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data register. Data are initially written to an individual DAC-n-data register and then transferred to the corresponding DAC-n latch. When the DAC-n latch is updated, the output of DAC-n changes to the newly set value. When the host reads the register memory map location labeled DAC-n-data, the value held in the DAC-n latch is returned (not the value held in the input DAC-n-data register). Full-Scale Output Range The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain of the DAC output buffer (VREF × gain). The gain bits of the DAC gain register set the output range of the individual DAC-n. The full-scale output range of each DAC is limited by the analog power supply. The maximum output from the DAC must not be greater than AVCC, and the minimum output must not be less than AGND. DAC Output After Power-On Reset After power-on, the DAC output buffer is in power-down mode. The output buffer is in a Hi-Z state and the DACxOUT (where x = 0 to 11) output pin connects to the analog ground through an internal 10-kΩ resistor. After power-on or a hardware reset, all DAC-n-data registers, DAC-n latches, and the DAC output are set to default values (000h). Load DAC Latch See Figure 91 for the structure of the DAC register and DAC latch. The contents of the DAC-n latch determine the output level of the DAC-n pin. After writing to the DAC-n-data register, the DAC latch can be loaded either in asynchronous or synchronous mode. In asynchronous mode (SLDAC-n bit = '0'), data are loaded into the DAC-n latch immediately after the write operation. In synchronous mode (SLDAC-n bit = '1'), the DAC latch updates when the synchronous DAC loading signal occurs. Setting the ILDAC bit in AMC configuration register 0 generates the loading signal. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 41 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Synchronous Load, Asynchronous Load, and Output Updating The SLDA-n (synchronous load) bit of the DAC configuration register determines the DAC updating mode, as shown in Table 5. When SLDA-n is cleared to '0', asynchronous mode is active, the DAC latch updates immediately after writing to the DAC-n-data register, and the output of DAC-n changes accordingly. Table 5. DAC-n Output Update Summary for Manual Mode Update SLDA-n BIT WRITING TO ILDAC BIT 0 Don't care 1 1 OPERATION Update DAC-n individually. The DAC-n latch and DAC-n output are immediately updated after writing to the DAC-n-data register. Simultaneously update all DACs by internal trigger. Writing '1' to the ILDAC bit generates an internal load DAC trigger signal that updates the DAC-n latches and DAC-n outputs with the contents of the corresponding DAC-n-data register. When the SLDA-n bit is set to '1', synchronous mode is selected. The value of the DAC-n-data register is transferred to the DAC-n latch only after an active DAC synchronous loading signal (ILDAC) occurs, which immediately updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n-data register changes only the value in that register, but not the content of DAC-n latch nor the output of DAC-n, until the synchronous load signal occurs. The DAC synchronous load is triggered by writing '1' to the ILDAC bit in AMC configuration register 0. When this DAC synchronous load signal occurs, all DACs with the SLDA-n bit set to '1' are simultaneously updated with the value of the corresponding DAC-n-data register. By setting the SLDA-n bit properly, several DACs can be updated at the same time. For example, to update DAC0 and DAC1 synchronously, set bits SLDA-0 and SLDA-1 to '1' first, and then write the proper values into the DAC-0-data and DAC-1-data registers, respectively. After this presetting, set the ILDAC bit to '1' to simultaneously load DAC0 and DAC1. The outputs of DAC0 and DAC1 change at the same time. The device updates the DAC latch only if the latch was accessed from the last time ILDAC was issued, thereby eliminating any unnecessary glitches. Any DAC channels that are not accessed are not reloaded again. When the DAC latch is updated, the corresponding output changes to the new level immediately. NOTE When DACs are cleared by an external DAC-CLR-n or by the internal CLR bit, the DAC latch is loaded with the predefined value of the DAC-n-CLR-setting register and the output is set to the corresponding level immediately, regardless of the SLDA-n bit value. However, the DAC data register does not change. 42 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Clear DACs DAC-n can be cleared with hardware or software, as shown in Figure 93. When DAC-n goes to a clear state, it is immediately loaded with predefined code in the DAC-n-CLR-setting register, and the output is set to the corresponding level to shut down the external LDMOS device. However, the DAC-n-data register does not change. When the DAC goes back to normal operation, DAC-n is immediately loaded with the previous data from the DAC-n-data register and the output of DACn-OUT is set back to the previous level to restore LDMOS to the status before shutdown, regardless of the SLDAC-n bit status. DAC Data Register DAC Latch 0 DAC 1 DAC CLR-Setting Register DAC-CLR-n Pin CLR-n Bit in HW-DAC-CLR-n Register CLR-n Bit in SW-DAC-CLR-n Register ACLR-n Bit Alarm Source Figure 93. Clearing DAC-n The device is implemented with two external control lines, the DAC-CLR-0 and DAC-CLR-1 pins, to clear the DACs. When either pin goes low, the corresponding user-selected DACs are in a cleared state. The HW_DACCLR-0 register determines which DAC is cleared when the DAC-CLR-0 pin is low. The register contains 12 clear bits (CLR-n), one per DAC. If the CLR-n bit is '1', DAC-n is in a cleared state when the DAC-CLR-0 pin is low. However, if the CLR-n bit is '0', DAC-n does not change when the pin is low. Likewise, the HW-DAC-CLR-1 register determines which DAC is cleared when the DAC-CLR-1 pin is low. Writing directly to the SW_DAC_CLR register puts the selected DACs in a cleared state. DACs can also be forced into a clear state by alarm events. The AUTO-DAC-CLR-SOURCE register specifies which alarm events force the DACs into a clear state, and the AUTO-DAC-CLR-EN register defines which DACs are forced into a clear state. Refer to the AUTO-DAC-CLR-SOURCE register and AUTO-DAC-CLR-EN register for further details. DAC Output Thermal Protection A significant amount of power can be dissipated in the DAC outputs. The AMC7812B is implemented with a thermal protection circuit that sets the THERM-ALR bit in the status register if the die temperature exceeds +150°C. The THERM-ALR bit can be used in combination with THERM-ALR-CLR (bit 2 in the AUTO-DAC-CLRSOURCE register) and ACLR-n (bits[14:3] in the AUTO-DAC-CLR-EN register) to set the DAC output to a predefined code when this condition occurs. Note that this feature is disabled when the local temperature sensor powers down. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 43 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Alarm Operation The device continuously monitors all analog inputs and temperatures in normal operation. When any input is out of the specified range, an alarm triggers. When an alarm state occurs, the corresponding individual alarm bit in the status register is set ('1'). The global alarm bit (GALR) in AMC configuration register 0 is the OR of individual alarms, see Figure 94. When the ALARM-LATCH-DIS bit in the alarm control register is cleared ('0'), the alarm is latched. The global alarm bit (GALR) maintains '1' until the corresponding error conditions subside and the alarm status is read. The alarm bits are referred to as being latched because they remain set until read by software. This design ensures that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the status register, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle, unless otherwise noted. CH0-ALR Alarm Status Bits GALR Bit THERM-ALR Figure 94. Global Alarm Bit When the ALARM-LATCH-DIS bit in the alarm control register is set ('1'), the alarm bit is not latched. The alarm bit in the status register goes to '0' when the error condition subsides, regardless of whether the bit is read or not. When GALR is '1', the ALARM pin goes low. When the GALR bit is '0', the ALARM is high (inactive). 44 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Analog Input Out-of-Range Alarm The device provides out-of-range detection for four individual analog inputs (CH0, CH1, CH2, and CH3), as shown in Figure 95. When the measurement is out-of-range, the corresponding alarm bit in the status register is set to '1' to flag the out-of-range condition. The value in the high-threshold register defines the upper bound threshold of the Nth analog input, while the value in the low-threshold register defines the lower bound. These two bounds specify a window for the out-of-range detection. High-Threshold-n Register (upper bound) CHn-ALR Bit nth Analog Input (n = 0 to 3) Low-Threshold-n Register (lower bound) Figure 95. CHn Out-of-Range Alarm The device also has high-limit or low-limit detection for the temperature sensors (D1, D2, and LT), as shown in Figure 96. To implement single, upper-bound threshold detection for analog input CHn, the host processor can set the upper-bound threshold to the desired value and the lower-bound threshold to the default value. For lowerbound threshold detection, the host processor can set the lower-bound threshold to the desired value and the upper-bound threshold to the default value. Note that the value of the high-threshold register must not be less than the value of the low-threshold register; otherwise, ALR-n is always set to '1' and the alarm indicator is always active. Each temperature sensor has two alarm bits: High-ALR (high-limit alarm) and Low-ALR (low-limit alarm). High-Threshold (upper bound) High-ALR Bit Temperature Data (D1, D2, LT) Low-ALR Bit Low-Threshold (lower bound) Figure 96. Temperature Out-of-Range Alarm Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 45 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ALARM pin The ALARM pin is a global alarm indicator. ALARM is an open-drain pin, as Figure 97 illustrates; an external pull-up resistor is required. When the pin is activated, it goes low. When the pin is inactive, it is in Hi-Z status. The ALARM pin functions as an interrupt to the host so that it may query the status register to determine the alarm source. Any alarm event (including analog inputs, temperatures, diode status, and device thermal condition) activates the pin if the alarm is not masked (the corresponding EALR bit in the alarm control register is '1'). When the alarm pin is masked (EN-ALARM bit is '0'), the occurrence of the event sets the corresponding status bit in status register to '1', but does not activate the ALARM pin. CH0-ALR Bit ALARM EALR-CH0 Bit G1 D2-FAIL-ALR Bit EALR-D2-FAIL Bit THERM-ALR Bit EN-ALARM Bit Figure 97. ALARM Pin When the ALARM-LATCH-DIS bit in the alarm control register is cleared ('0'), the alarm is latched. Reading the status register clears the alarm status bit. Whenever an alarm status bit is set, indicating an alarm condition, the bit remains set until the event that caused the alarm is resolved and the status register is read. The alarm bit can only be cleared by reading the status register after the event is resolved, or by a hardware reset, software reset, or power-on reset (POR). All bits are cleared when reading the status register, and all bits are reasserted if the out-of-limit condition still exists after the next conversion cycle, unless otherwise noted. When the ALARMLATCH-DIS bit in the alarm control register is set ('1'), the ALARM pin is not latched. The alarm bit clears to '0' when the error condition subsides, regardless of whether the bit is read or not. 46 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Hysteresis The device continuously monitors the analog input channels and temperatures. If any alarms are out of range and the alarm is enabled, the alarm bit is set ('1'). However, the alarm condition is cleared only when the conversion result returns to a value of at least hys below the value of the high threshold register, or hys above the value of low threshold register. The hysteresis registers store the value for each analog input (CH0, CH1, CH2, and CH3) and temperature (D1, D2, and LT). hys is the value of hysteresis that is programmable: 0 LSB to 127 LSB for analog inputs, and 0°C to +31°C for temperatures. For the THERM-ALR bit, the hysteresis is fixed at 8°C. The hysteresis behavior is shown in Figure 98. High Threshold Hysteresis Input Hysteresis Low Threshold Over High Alarm Below Low Alarm Figure 98. Hysteresis False-Alarm Protection As noted previously, the device continuously monitors all analog inputs and temperatures in normal operation. When any input is out of the specified range in N consecutive conversions, the corresponding alarm bit is set ('1'). If the input returns to the normal range before N consecutive times, the alarm bit remains clear ('0'). This design avoids false alarms. The number N is programmable by the CH-FALR-CT-[2:0] bits in AMC configuration register 1 for analog input CHn as shown in Table 6, or by the TEMP-FALR-CT-[1:0] bits for temperature monitors as shown in Table 7. Table 6. Consecutive Sample Number for False Alarm Protection for CHn CH-FALR-CT-2 CH-FALR-CT-1 CH-FALR-CT-0 N CONSECUTIVE SAMPLES BEFORE ALARM IS SET 0 0 0 1 0 0 1 4 0 1 0 8 0 1 1 16 (default) 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 Table 7. Consecutive Sample Number for False Alarm Protection for Temperature Channels TEMP-FALR-CT-1 TEMP-FALR-CT-0 N CONSECUTIVE SAMPLES BEFORE ALARM IS SET 0 0 1 0 1 2 1 0 4 (default) 1 1 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 47 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com GENERAL-PURPOSE INPUT AND OUTPUT PINS (GPIO-0 to GPIO-7) The device has eight GPIO pins. The GPIO-0, -1, -2 and -3 pins are dedicated to general, bidirectional, digital I/O signals. GPIO-4, GPIO-5, GPIO-6, and GPIO-7 are dual-function pins and can be programmed as either bidirectional digital I/O pins or remote temperature sensors D1 and D2. When D1 or D2 is disabled, the pins function as GPIOs. These pins can receive an input or produce an output. When the GPIO-n pin functions as an output, it has an open-drain and the status is determined by the corresponding GPIO-n bit of the GPIO register. The output state is high impedance when the GPIO-n bit is set to '1', and is logic low when the GPIO-n bit is cleared ('0'). Note that a 10-kΩ pull-up resistor is required when using the GPIO-n pin as an output, see Figure 99. The dual-function GPIO-4, -5, -6, and -7 pins should not be tied to a pull-up voltage that exceeds the AVDD supply. The dedicated GPIO-0, -1, -2, and -3 pins are only restricted by the absolute maximum voltage. To use the GPIO-n pin as an input, the corresponding GPIO-n bits in the GPIO register must be set to '1'. When the GPIO-n pin functions as an input, the digital value on the pin is acquired by reading the corresponding GPIO-n bit. After a power-on reset or any forced hardware or software reset, all GPIO-n bits are set to '1', and the GPIOn pin goes to a high-impedance state. V+ GPIO-n GPIO-n Bit (when writing) ENABLE GPIO-n Bit (when reading) Figure 99. GPIO Pins HARDWARE RESET Pulling the RESET pin low performs a hardware reset. When the RESET pin is low, the device enters a reset state and all registers are set to the default values (including the power-down register). Therefore, all function blocks (except the internal temperature sensor) are in power-down mode. On the RESET rising edge, the device returns to the normal operating mode. After returning to this mode, all registers remain set to the default value until a new value is written. Note that after reset, the power-down register must be properly written in order to activate the device. Hardware reset should only be issued when DVDD reaches the minimum specification of 2.7 V or above. SOFTWARE RESET Software reset returns all register settings to their default values and can be performed by writing to the software reset register. In the case of I2C communication, any value written to this register results in a reset condition. In the case of SPI communications, only writing the specific value of 6600h to this register resets the device. See the Registers section for details. During reset, all communication is blocked. After issuing the reset, wait at least 30 µs before attempting to resume communication. POWER-ON RESET (POR) When powered on, the internal POR circuit invokes a power-on reset, which performs the equivalent function of the RESET pin. To ensure a POR, DVDD must start from a level below 750 mV. 48 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 POWER-SUPPLY SEQUENCE The preferred (not required) order for applying power is IOVDD, DVDD/AVDD, and then AVCC. All registers initialize to the default values after these supplies are established. Communication with the device is valid after a 250-µs maximum power-on reset delay. The default state of all analog blocks is off as determined by the powerdown register (6Bh). Before writing to this register, a hardware reset should be issued to ensure specified device operation. Device communication is valid after a maximum 250-µs reset delay from the RESET rising edge. If DVDD falls below 2.7 V, the minimum supply value of DVDD, either issue a hardware or power-on reset in order to resume proper operation. To avoid activating the device ESD protection diodes, do not apply the GPIO-4, GPIO-5, GPIO-6, and GPIO-7 inputs before the AVDD is established. Also, if using the external reference configuration of the ADC, do not apply ADC-REF-IN/CMP before AVDD. PRIMARY COMMUNICATION INTERFACE The device communicates with the system controller through the primary communication interface, which can be configured as either an I2C-compatible two-wire bus or an SPI bus. When the SPI/I2C pin is tied to ground, the I2C interface is enabled and the SPI is disabled. When the SPI/I2C pin is tied to IOVDD, the I2C interface is disabled and the SPI is enabled. I2C-Compatible Interface This device uses a two-wire serial interface compatible with the I2C-bus specification, version 2.1. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All I2C-compatible devices connect to the I2C bus through open-drain I/O pins SDA and SCL. A master device, usually a microcontroller or a digital signal processor (DSP), controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the start and stop of data transfers. A slave device receives and transmits data on the bus under control of the master device. The AMC7812B functions as a slave and supports the following data transfer modes, as defined in the I2C-bus specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S mode in this document. The protocol for high-speed mode is different from the F/S mode, and is referred to as Hs mode. The device supports 7-bit addressing. However 10-bit addressing and general-call addressing are not supported. The device slave address is determined by the status of pins A0, A1, and A2, as shown in Table 8. Table 8. Slave Addresses A0 A1 A2 SLAVE ADDRESS GND GND GND 1100001 GND GND IOVDD 0101100 GND IOVDD GND 1100100 GND IOVDD IOVDD 0101110 IOVDD GND GND 1100010 IOVDD GND IOVDD 0101101 IOVDD IOVDD GND 1100101 IOVDD IOVDD IOVDD 0101111 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 49 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com F/S-Mode Protocol The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high; see Figure 2. All I2C-compatible devices must recognize a start condition. The master then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit (R/W) on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition requires that the SDA line is stable during the entire high period of the clock pulse (see Figure 2). All devices recognize the address sent by the master and compare the address to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 2) by pulling the SDA line low during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the master recognizes that a communication link is established with a slave. The master generates further SCL cycles to either transmit data to the slave (R/W bit is '1') or receive data from the slave (R/W bit is '0'). In either case, the receiver must acknowledge the data sent by the transmitter. Therefore, an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-tohigh while the SCL line is high (see Figure 2). This action releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition. When a stop condition is received, all devices recognize that the bus is released and wait for a start condition followed by a matching address. Hs-Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing Hs master code 00001xxx. This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the Hs master code, but all devices must recognize the Hs master code and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as for F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends Hs mode and switches all internal settings of the slave devices to support F/S mode. Note that instead of using a stop condition, repeated start conditions are used to secure the bus in Hs mode. Address Pointer The AMC7812B address pointer register is an 8-bit register. Each register has an address and, when accessed, the address pointer points to the register address. All AMC7812B registers are 16 bits, consisting of a high byte (D[15:8]) and a low byte (D[7:0]). The high byte is always accessed first, and the low byte accessed second. When the register is accessed, the entire register is frozen until the operation on the low byte is complete. During a write operation, the new content does not take effect until the low byte is written. In read operation, the whole register value is frozen until the low byte is read. The address pointer does not change after the current register is accessed. To change the pointer, the master issues a slave address byte with the R/W bit low, followed by the pointer register byte; no additional data are required. Timeout Function The device resets the serial interface if either SCL or SDA are held low for 32.8 ms (typical) between a START and STOP condition. If the device is holding the bus low, the device releases the bus and waits for a START condition. To avoid activating the timeout function, a communication speed of at least 1 kHz for the SCL operating frequency must be maintained. 50 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Device Communication Protocol for I2C The device uses the following I2C protocols: writing a single word of data to a 16-bit register, writing multiple words to different registers, reading a single word from any register, and reading the same register multiple times. This section discusses these I2C protocols. Writing a Single Word of Data to a 16-Bit Register (Figure 100) Figure 100 shows a diagram of this protocol. Steps for this protocol are: 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a write operation. 3. The AMC7812B asserts an acknowledge signal on SDA. 4. The master sends a register address. 5. The AMC7812B asserts an acknowledge signal on SDA. 6. The master sends a data byte of the high byte of the register (D[15:8]). 7. The AMC7812B asserts an acknowledge signal on SDA. 8. The master sends a data byte of the low byte of the register (D[7:0]). 9. The AMC7812B asserts an acknowledge signal on SDA. 10. The master asserts a stop condition to end the transaction. S Device Slave Address From Master to Slave From Slave to Master 0 A Register Pointer (Register Address) A High Byte to Device Register A Low Byte to Device Register A P A = Acknowledge N = Not Acknowledge S = START Condition P = Stop Condition Sr = Repeated START Condition Figure 100. Write Single Byte Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 51 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Writing Multiple Words to Different Registers (Figure 101) A complete word must be written to a register (high byte and low byte) for proper operation, as shown in Figure 101. Steps for this process are: 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a write operation. 3. The AMC7812B asserts an acknowledge signal on SDA. 4. The master sends the first register address. 5. The AMC7812B asserts an acknowledge signal on SDA. 6. The master sends the high byte of the data word to the first register. 7. The AMC7812B asserts an acknowledge signal on SDA. 8. The master sends the low byte of the data word to the first register. 9. The AMC7812B asserts an acknowledge signal on SDA. 10. The master sends a second register address. 11. The AMC7812B asserts an acknowledge signal on SDA. 12. The master then sends the high byte of the data word to the second register. 13. The AMC7812B asserts an acknowledge on SDA. 14. The master sends the low byte of the data word to the second register. 15. The AMC7812B asserts an acknowledge signal on SDA. 16. The master and the AMC7812B repeat steps 4 to 15 until the last data are transferred. 17. The master then asserts a stop condition to end the transaction. S Device Slave Address From Master to Slave From Slave to Master 0 A Register Pointer (1st Register Address) A High Byte of Data to 1st Register A Low Byte of Data to 1st Register A Register Pointer (2nd Register Address) A High Byte of Data to 2nd Register A Low Byte of Data to 2nd Register A Register Pointer (Last Register Address) A High Byte of Data to Last Register A Low Byte of Data to Last Register A P A = Acknowledge N = Not Acknowledge S = START Condition P = Stop Condition Sr = Repeated START Condition Figure 101. Write to Multiple 16-Bit Registers 52 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Reading a Single Word from Any Register (Figure 102) Figure 102 shows a diagram of this protocol. Steps for this protocol are: 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a write operation. 3. The AMC7812B asserts an acknowledge signal on SDA. 4. The master sends a register address. 5. The AMC7812B asserts an acknowledge signal on SDA. 6. The master device asserts a restart condition. 7. The master then sends the 7-bit AMC7812B slave address followed by a '1' for the direction bit, indicating a read operation. 8. The AMC7812B asserts an acknowledge signal on SDA. 9. The AMC7812B then sends the high byte of the register (D[15:8]). 10. The master asserts an acknowledge signal on SDA. 11. The AMC7812B sends the low byte of the register (D[7:0]). 12. The master asserts a not acknowledge signal on SDA. 13. The master then asserts a stop condition to end the transaction. S Device Slave Address From Master to Slave From Slave to Master 0 A Register Pointer (Register Address) A A From High Byte of Device Register A Device Slave Address Sr From Low Byte of Device Register 1 N P A = Acknowledge N = Not Acknowledge S = START Condition P = Stop Condition Sr = Repeated START Condition Figure 102. Read a Single Word Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 53 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Reading the Same Register Multiple Times (Figure 103 and Figure 104) Figure 103 and Figure 104 illustrate the process for this protocol. Steps for this protocol are: 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a write operation. 3. The AMC7812B asserts an acknowledge signal on SDA. 4. The master sends a register address. 5. The AMC7812B asserts an acknowledge signal on SDA. 6. The master device asserts a restart condition. 7. The master then sends the 7-bit AMC7812B slave address followed by a '1' for the direction bit, indicating a read operation. 8. The AMC7812B asserts an acknowledge signal on SDA. 9. The AMC7812B then sends the high byte of the register (D[15:8]). 10. The master asserts an acknowledge signal on SDA. 11. The AMC7812B sends the low byte of the register (D[7:0]). 12. The master asserts an acknowledge signal on SDA. 13. The AMC7812B and the master repeat steps 9 to 12 until the low byte of last reading is transferred. 14. After receiving the low byte of the last register, the master asserts a not acknowledge signal on SDA. 15. The master then asserts a stop condition to end the transaction. S Device Slave Address From Master to Slave From Slave to Master 0 A Register Pointer (Register Address) A A High Byte of Register; 1st Reading A Low Byte of Register; 1st Reading A High Byte of Register; Last Reading A Low Byte of Register; Last Reading N Sr Device Slave Address 1 P A = Acknowledge N = Not Acknowledge S = START Condition P = Stop Condition Sr = Repeated START Condition Figure 103. Read Multiple Words 54 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 S S S Device Slave Address Device Slave Address Device Slave Address From Master to Slave From Slave to Master 0 0 0 A Register Pointer (1st Register Address) A A High Byte of 1st Register A A Register Pointer (2nd Register Address) A A High Byte of 2nd Register A A Register Pointer (Last Register Address) A A High Byte of the Last Register being Read A Sr Device Slave Address Low Byte of 1st Register Sr N Device Slave Address Low Byte of 2nd Register Sr 1 1 N Device Slave Address Low Byte of the Last Register being Read P P 1 N P A = Acknowledge N = Not Acknowledge S = START Condition P = Stop Condition Sr = Repeated START Condition Figure 104. Read Multiple Registers Using the Reading Single Word from Any Register Method Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 55 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Serial Peripheral Interface (SPI) The AMC7812B can be controlled over a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. The SPI communication command consists of a read or write (R/W) bit, seven register address bits, and 16 data bits (as shown in Table 9), for a total of 24 bits. The timing for this operation is shown in the SPI timing diagrams (Figure 3, Figure 4, and Figure 5). SPI Shift Register The SPI shift register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK. The CS falling edge starts the communication cycle. Data are latched into the SPI shift register on the SCLK falling edge, while CS is low. When CS is high, the SCLK and SDI signals are blocked out and the SDO line is in a high-impedance state. The contents of the SPI shift register are loaded into the device internal register on the CS rising edge (with delay). During the transfer, the command is decoded and new data are transferred into the proper registers. The serial interface functions with both a continuous and non-continuous serial clock. A continuous SCLK source can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and CS must be taken high after the final clock to latch the data. AMC7812B Communications Command for SPI The AMC7812B is entirely controlled by registers. Reading from and writing to these registers is accomplished by issuing a 24-bit operation word shown in Table 9. Table 9. 24-Bit Word Structure for Read/Write Operation OPERATION Write Read frame 1 Read frame 2 Bit 23 I/O BIT 23 (MSB) BIT22:BIT16 BIT15:BIT0 SDI 0 (R/W) Addr[6:0] Data to be written SDO Data are undefined Data are undefined Undefined or data depending on the previous frame SDI 1 (R/W) Addr[6:0] Don't care SDO Data are undefined Data are undefined Undefined or data depending on the previous frame SDI 1 (R/W) Addr[6:0] Don't care SDO Data are undefined Data are undefined Data for address specified in frame 1 R/W. Indicates a read from or a write to the addressed register. 0 = The write operation is set and data are written to the specified register 1 = A read operation where bits Addr[6:0] select the register to be read. The remaining bits are don't care. Data read from the selected register appear on the SDO pin in the next SPI cycle. Bits[22:16] Addr6:Addr0. Register address; specifies which register is accessed. Bits[15:0] DATA. 16-bit data bits. In a write operation, these bits are written to bits[15:0] of the register with the address of (Addr[6:0]). In a read operation, these bits are determined by the previous operation. If the previous operation is a read, these bits are from bits[15:0] of the internal register specified in previous read operation. If the previous operation is a write, these data bits are don’t care (undefined). Data read from the current read operation appear on SDO in the next operation cycle. 56 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Standalone Operation SDO SDI SCLK CS In standalone mode, as shown in Figure 105, each device has its own SPI bus. The serial clock can be continuous or gated. The first CS falling edge starts the operation cycle. Exactly 24 falling clock edges must be applied before CS is brought high again. If CS is brought high before the 24th falling SCLK edge, or if more than 24 SCLK falling edges are applied before CS is brought high, then the input data are incorrect. The device input register is updated from the shift register on the CS rising edge, and data are automatically transferred to the addressed registers as well. In order for another serial transfer to occur, CS must be brought low again. Figure 106 and Figure 107 show write and read operations in standalone mode. Figure 105. Standalone Operation CS SDI W0 SDO W1 XX W3 W2 XX XX XX Wn = Write Command for Register N XX = Don’t care, undefined Figure 106. Write Operation in Standalone Mode CS SDI SDO R0 R1 D0 XX R2 D1 Any Command R3 D3 D2 Rn = Read Command for Register N Dn = Data from Register N XX = Don’t care, undefined Figure 107. Read Operation in Standalone Mode Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 57 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Daisy-Chain Operation For systems that contain several AMC7812Bs, the SDO pin can be used to daisy-chain multiple devices together. This daisy-chain feature is useful in reducing the number of serial interface lines. The first CS falling edge starts the operation cycle. SCLK is continuously applied to the input shift register when CS is low. If more than 24 clock pulses are applied, data ripple out of the shift register and appear on the SDO line. These data are clocked out on the SCLK rising edge and are valid on the falling edge. By connecting the SDO output of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AMC7812Bs in the daisy chain. When the serial transfer to all devices is complete, CS is taken high. This action transfers data from the SPI shifter registers to the internal register of each AMC7812B in the daisy-chain and prevents any further data from being clocked in. The serial clock can be continuous or gated. A continuous SCLK source can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and CS must be taken high after the final clock in order to latch the data. Figure 108 to Figure 111 illustrate the daisychain operation. B C SDI SDI-C SDO-C SDI-B A SDO-B SDO-A SDI-A SDO CS SCLK Figure 108. Three AMC7812Bs in a Daisy-Chain Configuration Cycle 0 CS Cycle 1 Cycle 2 Cycle 3 SDI-C RA0 RB0 RC0 RA1 RB1 RC1 RA2 RB2 RC2 RA3 RB3 RC3 SDO-C XX RA0 RB0 CD0 RA1 RB1 CD1 RA2 RB2 CD2 RA3 RB3 SDI-B XX RA0 RB0 CD0 RA1 RB1 CD1 RA2 RB2 CD2 RA3 RB3 SDO-B XX XX RA0 BD0 CD0 RA1 BD1 CD1 RA2 BD2 CD2 RA3 SDI-A XX XX RA0 BD0 CD0 RA1 BD1 CD1 RA2 BD2 CD2 RA3 SDO-A XX XX XX AD0 BD0 CD0 AD1 BD1 CD1 AD2 BD2 CD2 RAn (RBn, RCn) = Read Command for Register N of device A (B,C) ADn (BDn, CDn) = Data from Register N of device A (B, C) XX = Don’t care, undefined Figure 109. Reading Multiple Registers 58 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Cycle 0 CS Cycle 1 Cycle 2 Cycle 3 SDI-C RA0 WB0 RC0 RA1 WB1 WC1 RA2 RB2 RC2 RA3 RB3 RC3 SDO-C XX RA0 WB0 CD0 RA1 WB1 XX RA2 RB2 CD2 RA3 RB3 SDI-B XX RA0 WB0 CD0 RA1 WB1 XX RA2 RB2 CD2 RA3 RB3 SDO-B XX XX RA0 XX CD0 RA1 XX XX RA2 BD2 CD2 RA3 SDI-A XX XX RA0 XX CD0 RA1 XX XX RA2 BD2 CD2 RA3 SDO-A XX XX XX AD0 XX CD0 AD1 XX XX AD2 BD2 CD2 WBn (WCn) = Write Command for Register N of device A (B,C) RAn (RBn, RCn) = Read Command for Register N of device A (B, C) ADn (BDn, CDn) = Data from Register N of device A (B, C) XX = Don’t care, undefined Figure 110. Mixed Operation: Reading Devices A and C, and Writing to Device B; then Reading A, and Writing to B and C; then Reading A, B, and C Twice Cycle 0 CS Cycle 1 Cycle 2 Cycle 3 SDI-C WA0 WB0 RC0 WA1 WB1 RC1 WA2 WB2 RC2 WA3 WB3 RC3 SDO-C XX WA0 WB0 CD0 WA1 WB1 CD1 WA2 WB2 CD2 WA3 WB3 SDI-B XX WA0 WB0 CD0 WA1 WB1 CD1 WA2 WB2 CD2 WA3 WB3 SDO-B XX XX WA0 XX CD0 WA1 XX CD1 WA2 XX CD2 WA3 SDI-A XX XX WA0 XX CD0 WA1 XX CD1 WA2 XX CD2 WA3 SDO-A XX XX XX XX XX CD0 XX XX CD1 XX XX CD2 Figure 111. Writing to Devices A and B, and Reading Device C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 59 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com REGISTERS REGISTER MAP The AMC7812B has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8bit register pointer points to the proper register. The pointer does not change after an operation. Table 10 lists the registers for the AMC7812B. Note that the default values are for SPI operation; see the Register Descriptions section for I2C default values. Table 10. Register Map ADDRESS (HEX) R/W DEFAULT (HEX) 00 R 0000 01 R 02 R 0A R/W 0B (1) 60 ADDRESS (HEX) R/W DEFAULT (HEX) LT-temperature-data 45 R/W 0000 DAC-6-CLR-setting 0000 D1-temperature-data 46 R/W 0000 DAC-7-CLR-setting 0000 D2-temperature-data 47 R/W 0000 DAC-8-CLR-setting 003C (1) Temperature configuration 48 R/W 0000 DAC-9-CLR-setting R/W 0007 (1) Temperature conversion rate 49 R/W 0000 DAC-10-CLR-setting 21 R/W 0000 (1) η-factor correction (for D1) 4A R/W 0000 DAC-11-CLR-setting 22 R/W 0000 (1) η-factor correction (for D2) 4B R/W 00FF GPIO 23 R 0000 ADC-0-data 4C R/W 2000 AMC configuration 0 24 R 0000 ADC-1-data 4D R/W 0070 AMC configuration 1 25 R 0000 ADC-2-data 4E R/W 0000 Alarm control 26 R 0000 ADC-3-data 4F R 0000 Status 27 R 0000 ADC-4-data 50 R/W 0000 ADC channel 0 28 R 0000 ADC-5-data 51 R/W 0000 ADC channel 1 29 R 0000 ADC-6-data 52 R/W FFFF ADC gain 2A R 0000 ADC-7-data 53 R/W 0004 AUTO-DAC-CLR-SOURCE REGISTER REGISTER 2B R 0000 ADC-8-data 54 R/W 0000 AUTO-DAC-CLR-EN 2C R 0000 ADC-9-data 55 R/W 0000 SW-DAC-CLR 2D R 0000 ADC-10-data 56 R/W 0000 HW-DAC-CLR-EN-0 2E R 0000 ADC-11-data 57 R/W 0000 HW-DAC-CLR-EN-1 2F R 0000 ADC-12-data 58 R/W 0000 DAC configuration 30 R 0000 ADC-13-data 59 R/W 0000 DAC gain 31 R 0000 ADC-14-data 5A R/W 0FFF Input-0-high-threshold 32 R 0000 ADC-15-data 5B R/W 0000 Input-0-low-threshold 33 R/W 0000 DAC-0-data 5C R/W 0FFF Input-1-high-threshold 34 R/W 0000 DAC-1-data 5D R/W 0000 Input-1-low-threshold 35 R/W 0000 DAC-2-data 5E R/W 0FFF Input-2-high-threshold 36 R/W 0000 DAC-3-data 5F R/W 0000 Input-2-low-threshold 37 R/W 0000 DAC-4-data 60 R/W 0FFF Input-3-high-threshold 38 R/W 0000 DAC-5-data 61 R/W 0000 Input-3-low-threshold 39 R/W 0000 DAC-6-data 62 R/W 07FF LT-high-threshold 3A R/W 0000 DAC-7-data 63 R/W 0800 LT-low-threshold 3B R/W 0000 DAC-8-data 64 R/W 07FF D1-high-threshold 3C R/W 0000 DAC-9-data 65 R/W 0800 D1-low-threshold 3D R/W 0000 DAC-10-data 66 R/W 07FF D2-high-threshold 3E R/W 0000 DAC-11-data 67 R/W 0800 D2-low-threshold 3F R/W 0000 DAC-0-CLR-setting 68 R/W 0810 Hysteresis-0 40 R/W 0000 DAC-1-CLR-setting 69 R/W 0810 Hysteresis-1 41 R/W 0000 DAC-2-CLR-setting 6A R/W 2108 Hysteresis-2 42 R/W 0000 DAC-3-CLR-setting 6B R/W 0000 Power-down 43 R/W 0000 DAC-4-CLR-setting 6C R 1221 Device ID 44 R/W 0000 DAC-5-CLR-setting 7C R/W N/A Software reset 2 See register descriptions for I C default values. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 REGISTER DESCRIPTIONS Temperature Data Registers (Read-Only) In twos complement format, 0.125°C/LSB. LT-Temperature-Data Register (Address = 00h, Default 0000h, 0°C) Store the local temperature sensor reading in twos complement data format. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 LT-11 LT-5 LT-4 LT-3 LT-2 LT-1 LT-0 0 0 0 0 LT-10 LT-9 LT-8 LT-7 LT-6 D1-Temperature-Data Register (Address = 01h, Default 0000h, 0°C) Store the remote temperature sensor D1 reading in twos complement data format. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 D1-11 D1-5 D1-4 D1-3 D1-2 D1-1 D1-0 0 0 0 0 D1-10 D1-9 D1-8 D1-7 D1-6 D2-Temperature-Data Register (Address = 02h, Default 0000h, 0°C) Store the remote temperature sensor D2 reading in twos complement data format. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 D2-11 D2-5 D2-4 D2-3 D2-2 D2-1 D2-0 0 0 0 0 D2-10 D2-9 D2-8 D2-7 D2-6 Temperature Configuration Register (Read or Write, Address = 0Ah) When using the SPI, the following bit configuration must be used; default = 003Ch. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 0 0 D2EN D1EN LTEN RC 0 0 When using the I2C interface, the following bit configuration must be used; default = 3CFFh. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 D2EN D1EN LTEN RC BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 1 1 1 1 1 1 1 1 Bit descriptions for this register are shown in Table 11. Table 11. Temperature Configuration Register Bit Descriptions NAME DEFAULT R/W DESCRIPTION D2EN 1 R/W Remote temperature sensor D2 enable. 0 = D2 is disabled 1 = D2 is enabled D1EN 1 R/W Remote temperature sensor D1 enable. 0 = D1 is disabled 1 = D1 is enabled LTEN 1 R/W Local temperature sensor enable. 0 = LT is disabled 1 = LT is enabled RC 1 R/W Resistance correction enable. 0 = Correction is disabled 1 = Correction is enabled Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 61 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Temperature Conversion Rate Register (Read or Write, Address = 0Bh) When using the SPI, the following bit configuration must be used; default = 0007h. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 0 0 0 0 0 R2 R1 R0 When using the I2C interface, the following bit configuration must be used; default = 07FFh. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 R2 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 R1 R0 1 1 1 1 1 1 1 1 Bit descriptions for this register are shown in Table 12. Table 12. Temperature Conversion Time R2 R1 R0 CONVERSION TIME 0 0 0 128x minimum 0 0 1 64x minimum 0 1 0 32x minimum 0 1 1 16x minimum 1 0 0 8x minimum 1 0 1 4x minimum 1 1 0 2x minimum 1 1 1 Minimum cycle time Table 13. Temperature Monitoring Cycle Time MONITORING CYCLE TIME (ms) TEMPERATURE SENSOR STATUS Local sensor is active, remote sensors are disabled or in power-down. 15 One remote sensor is active and RC is '0', local sensor and one remote sensor are disabled or in power-down. 44 One remote sensor is active and RC is '1', local sensor and one remote sensor are disabled or in power-down. 93 One remote sensor and local sensor are active and RC is '0', one remote sensor is disabled or in power-down. 59 One remote sensor and local sensor are active and RC is '1', one remote sensor is disabled or in power-down. 108 Two remote sensors are active and RC is '0', local sensor is disabled or in power-down. 88 Two remote sensors are active and RC is '1', local sensor is disabled or in power-down. 186 All sensors are active and RC is '0'. 103 All sensors are active and RC is '1'. 201 62 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 η-Factor Correction Register (Read or Write, Addresses = 21h and 22h) Only the low byte is used; the high byte is ignored. When using the SPI interface, the following bit configuration must be used; default = 0000h. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 BIT 9 BIT 8 0 0 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 NADJUST When using the I2C, the following bit configuration must be used; default = 00FFh. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 NADJUST BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 1 1 1 1 1 1 1 1 The NADJUST value for ideality correction is stored as shown in Table 14. ηEFF is the actual ideality of the transistor being used. Refer to the Ideality Factor section for further details. Table 14. NADJUST and ηEFF Values NADJUST BINARY HEX DECIMAL ηEFF 0111 1111 7F 127 1.747977 0000 1010 0A 10 1.042759 0000 1000 08 8 1.035616 0000 0110 06 6 1.028571 0000 0100 04 4 1.021622 0000 0010 02 2 1.014765 0000 0001 01 1 1.011371 0000 0000 00 0 1.008 (default) 1111 1111 FF –1 1.004651 1111 1110 FE –2 1.001325 1111 1100 FC –4 0.994737 1111 1010 FA –6 0.988235 1111 1000 F8 –8 0.981818 1111 0110 F6 –10 0.975484 1000 0000 80 –128 0.706542 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 63 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ADC-n-Data Registers (Read-Only, Addresses = 23h to 32h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 Bits[11:0] 0 0 A11 A10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADC data. Four ADC data registers are available. The ADC-n-data registers (where n = 0 to 15) store the conversion results of the corresponding analog channel-n, as shown in Table 15. Table 15. ADC Data Register Definitions 64 INPUT CHANNEL INPUT TYPE CONVERSION RESULT STORED IN FORMAT Channel 0 Single-ended ADC-0-data register Straight binary Channel 1 Single-ended ADC-1-data register Straight binary Channel 2 Single-ended ADC-2-data register Straight binary Channel 3 Single-ended ADC-3-data register Straight binary CH0+ or CH1– Differential ADC-0-data register Twos complement CH2+ or CH3– Differential ADC-2-data register Twos complement Channel 4 Single-ended ADC-4-data register Straight binary Channel 5 Single-ended ADC-5-data register Straight binary Channel 6 Single-ended ADC-6-data register Straight binary Channel 7 Single-ended ADC-7-data register Straight binary Channel 8 Single-ended ADC-8-data register Straight binary Channel 9 Single-ended ADC-9-data register Straight binary Channel 10 Single-ended ADC-10-data register Straight binary Channel 11 Single-ended ADC-11-data register Straight binary Channel 12 Single-ended ADC-12-data register Straight binary Channel 13 Single-ended ADC-13-data register Straight binary Channel 14 Single-ended ADC-14-data register Straight binary Channel 15 Single-ended ADC-15-data register Straight binary Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 DAC-n-Data Registers (Read or Write, Addresses = 33h to 3Eh, Default 0000h) Each DAC has a DAC data register to store the data (DAC[11:0]) that are loaded into the DAC latches. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 Bits[11:0] 0 0 D11 D10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC data. DAC-n-CLR-Setting Registers (Read or Write, Addresses = 3Fh to 4Ah, Default 0000h) Each DAC has a DAC-CLR-setting register to store the data to be loaded into the DAC latch when the DAC is cleared. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 DCLR 11 DCLR 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 DCLR 9 DCLR 8 DCLR 7 DCLR 6 DCLR 5 DCLR 4 DCLR 3 DCLR 2 DCLR 1 DCLR 0 GPIO Register (Read or Write, Address = 4Bh, Default = 00FFh) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 For write operations, the GPIO pin operates as an output. Writing a '0' sets the GPIO-n pin to logic low. An external pull-up resistor is required when using the GPIO pin as an output. Writing a '1' to the GPIO-n bit sets the GPIO-n pin to high impedance. For read operations, the GPIO pin operates as an input. Read the GPIO-n bit to receive the status of the GPIO-n pin. Reading a '0' indicates that the GPIO-n pin is low; reading a '1' indicates that the GPIO-n pin is high. After power-on reset, or any forced hardware or software reset, the GPIO-n bit is set to '1' and is in a highimpedance state. When D1 is enabled, GPIO-4 and GPIO-5 are ignored. When D2 is enabled, GPIO-6 and GPIO-7 are ignored. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 65 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com AMC Configuration Register 0 (Read or Write, Address = 4Ch, Default = 2000h) Table 16. AMC Configuration Register 0 BIT NAME DEFAULT R/W DESCRIPTION 15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. ADC conversion mode bit. This bit selects between the two operating conversion modes (direct or auto). 0 = Direct mode. The analog inputs specified in the ADC channel registers are converted sequentially (see the ADC channel registers) one time. When one set of conversions are complete, the ADC is idle and waits for a new trigger. 1 = Auto mode. The analog inputs specified in the AMC channel registers are converted sequentially and repeatedly (see the ADC channel registers). When one set of conversions are complete, the ADC multiplexer returns to the first channel and repeats the process. Repetitive conversions continue until the CMODE bit is cleared ('0'). 13 CMODE 1 R/W 12 ICONV 0 R/W Internal conversion bit. Set this bit to '1' to start the ADC conversion internally. The bit is automatically cleared ('0') after the ADC conversion starts. R/W Load DAC bit. Set this bit to '1' to synchronously load the DAC data registers, which are programmed for synchronous update mode (SLDAC-n = 1). The AMC7812B updates the DAC latch only if the ILDAC bit is set ('1'), thereby eliminating any unnecessary glitches. Any DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output changes to the new level immediately. This bit is cleared ('0') after the DAC data register is updated. 11 ILDAC 0 ADC VREF select bit. 10 ADC-REF-INT 0 R/W 9 EN-ALARM 0 R/W 8 — 0 R 0 = The internal reference buffer is off and the external reference drives the ADC. 1 = The internal buffer is on and the internal reference drives the ADC. Note that a compensation capacitor is required. Enable ALARM pin bit. 0 = The ALARM pin is disabled 1 = The ALARM pin is enabled Reserved. Writing to this bit causes no change. Reading this bit returns '0'. ADC Data available flag bit. For direct mode only. Always cleared (set to '0') in Auto mode. 66 R 0 = The ADC conversion is in progress (data are not ready) or the ADC is in auto mode. 1 = The ADC conversions are complete and new data are available. In direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF is '1', and goes high when DAVF is '0'. In auto mode, DAVF is always cleared to '0'. However, a 1-µs pulse (active low) appears on the DAV pin when the last input specified in the ADC channel registers is converted. DAVF is cleared to '0' in one of three ways: by reading the ADC data register, by starting a new ADC conversion, or by writing '0' to this bit. Reading the status register does not clear this bit. 7 DAVF 6 GALR 0 R Global alarm bit. This bit is the OR function of all individual alarm bits of the status register. This bit is set ('1') when any alarm condition occurs, and remains '1' until the status register is read. This bit is cleared ('0') after reading the status register. 5 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 4 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 3 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 2 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 AMC Configuration Register 1 (Read or Write, Address = 4Dh, Default = 0070h) Table 17. AMC Configuration Register 1 BIT NAME DEFAULT R/W DESCRIPTION 15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 13 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 12 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 11 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 10 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 9 CONV-RATE-1 0 R/W ADC conversion rate bit. See Table 18. 8 CONV-RATE-0 0 R/W ADC conversion rate bit. See Table 18. 7 CH-FALR- CT-2 0 R/W False alarm protection bit for CH0 to CH3. See Table 19. 6 CH-FALR- CT-1 1 R/W False alarm protection bit for CH0 to CH3. See Table 19. 5 CH-FALR- CT-0 1 R/W False alarm protection bit for CH0 to CH3. See Table 19. 4 TEMP-FALR- CT-1 1 R/W False alarm protection bit for temperature monitor. See Table 20. 3 TEMP-FALR- CT-0 0 R/W False alarm protection bit for temperature monitor. See Table 20. 2 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. Table 18. CONV-RATE-[1:0] Bit Settings CONV-RATE-1 CONV-RATE-0 ADC CONVERSION RATE 0 0 500 kSPS, the specified rate (default) 0 1 1/2 of the specified rate 1 0 1/4 of the specified rate 1 1 1/8 of the specified rate Table 19. CH-FALR-CT-[2:0] Bit Settings CH-FALR-CT-2 CH-FALR-CT-1 CH-FALR-CT-0 N CONSECUTIVE SAMPLES BEFORE ALARM IS SET 0 0 0 1 0 0 1 4 0 1 0 8 0 1 1 16 (default for CH0 to CH3) 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 Table 20. TEMP-FALR-CT-[1:0] Bit Settings TEMP-FALR-CT-1 TEMP-FALR-CT-0 N CONSECUTIVE SAMPLES BEFORE ALARM IS SET 0 0 1 0 1 2 1 0 4 (default) 1 1 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 67 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Alarm Control Register (Read or Write, Address = 4Eh, Default = 0000h) The alarm control register determines whether the ALARM pin is accessed when a corresponding alarm event occurs. However, this register does not affect the status bit in the status register. Note that the thermal alarm is always enabled. When the THERM_ALR bit is '1', the ALARM pin goes low if the pin is enabled. Table 21. Alarm Control Register BIT NAME DEFAULT R/W 15 — 0 R DESCRIPTION Reserved. Writing to this bit causes no change. Reading this bit returns '0'. CH0 and (CH0+, CH1–) alarm enable bit. 14 EALR-CH0 0 R/W 0 = The alarm is masked. When the input of CH0 or (CH0+, CH1–) is out of range, the ALARM pin does not go low, but the CH0-ALR bit is set. 1 = The alarm is enabled, the CH0-ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH0 or (CH0+, CH1–) is out of range. CH1 alarm enable bit. 13 EALR-CH1 0 R/W 0 = The alarm is masked. When the input of CH1 is out of range, the ALARM pin does not go low, but the CH1-ALR bit is set. 1 = The alarm is enabled, the CH1-ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH1 is out of range. CH2 and (CH2+, CH3–) alarm enable bit. 12 EALR-CH2 0 R/W 0 = The alarm is masked. When the input of CH2 or (CH2+, CH3–) is out of range, the ALARM pin does not go low, but the CH2-ALR bit is set. 1 = The alarm is enabled, the CH2-ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH2 or (CH2+, CH3–) is out of range. CH3 alarm enable bit. 11 EALR-CH3 0 R/W 0 = The alarm is masked. When the input of CH3 is out of range, the ALARM pin does not go low, but the CH3-ALR bit is set. 1 = The alarm is enabled, the CH3-ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH3 is out of range. Local sensor low alarm enable bit. 10 EALR-LT-Low 0 R/W 0 = The LT-Low alarm is masked. When LT is below the specified range, the ALARM pin does not go low, but the LT-Low-ALR bit is set. 1 = The LT-Low alarm is enabled. When LT is below the specified range, the LT-Low-ALR bit is set ('1') and the ALARM pin goes low (if enabled). Local sensor high alarm enable bit. 9 EALR-LT-High 0 R/W 0 = The LT-High alarm is masked. When LT is above the specified range, the ALARM pin does not go low, but the LT-High-ALR bit is set. 1 = The LT-High alarm is enabled. When LT is above the specified range, the LT-High-ALR bit is set ('1') and the ALARM pin goes low (if enabled). D1 low alarm enable bit. 8 EALR-D1-Low 0 R/W 0 = The D1-Low alarm is masked. When D1 is below the specified range, the ALARM pin does not go low, but the D1-Low-ALR bit is set. 1 = The D1-Low alarm is enabled. When D1 is below the specified range, the D1-Low-ALR bit is set ('1'), and the ALARM pin goes low (if enabled). D1 high alarm enable bit. 7 EALR-D1-High 0 R/W 0 = The D1-High alarm is masked. When D1 is above the specified range, the ALARM pin does not go low, but the D1-High-ALR bit is set. 1 = The D1-High alarm is enabled. When D1 is above the specified range, the D1-HighALR bit is set ('1'), and the ALARM pin goes low (if enabled). D2 low alarm enable bit. 6 EALR-D2-Low 0 R/W 0 = The D2-Low alarm is masked. When D2 is below the specified range, the ALARM pin does not go low, but the D2-Low-ALR bit is set. 1 = The D2-Low alarm is enabled. When D2 is below the specified range, the D2-Low-ALR bit is set ('1'), and the ALARM pin goes low (if enabled). D2 high alarm enable bit. 5 68 EALR-D2-High 0 R/W 0 = The D2-High alarm is masked. When D2 is above the specified range, the ALARM pin does not go low, but the D2-High-ALR bit is set. 1 = The D2-High alarm is enabled. When D2 is above the specified range, the D2-HighALR bit is set ('1'), and the ALARM pin goes low (if enabled). Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Table 21. Alarm Control Register (continued) BIT NAME DEFAULT R/W DESCRIPTION D1 fail alarm enable bit. 4 EALR-D1-FAIL 0 R/W 0 = The D1-FAIL alarm is masked. When D1 fails, the ALARM pin does not go low, but the D1-FAIL-ALR bit is set. 1 = The D1-Fail alarm is enabled. When D1 fails, the D1-FAIL-ALR bit is set ('1'), the ALARM pin goes low (if enabled). D2 fail alarm enable bit. 3 EALR-D2-FAIL 0 R/W 0 = The D2-FAIL alarm is masked. When D2 fails, the ALARM pin does not go low, but the D2-FAIL-ALR bit is set. 1 = The D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is set ('1'), the ALARM pin goes low (if enabled). Alarm latch disable bit. 0 = The status register bits are latched. When an alarm occurs, the corresponding alarm bit is set ('1'). The alarm bit remains '1' until the error condition subsides and the status register is read. Before reading, the alarm bit is not cleared ('0') even if the alarm condition disappears. 1 = The status register bits are not latched. When the alarm condition subsides, the alarm bits are cleared regardless of whether the status register is read or not. 2 ALARMLATCH-DIS 0 R/W 1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 69 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Status Register (Read-Only, Address = 4Fh, Default = 0000h) The AMC7812B continuously monitors all analog inputs and temperatures during normal operation. When any input is out of the specified range for N consecutive times, the corresponding alarm bit is set ('1'). If the input returns to the normal range before N consecutive times, the corresponding alarm bit remains clear ('0'). This configurations avoids any false alarms. When an alarm status occurs, the corresponding alarm bit is set ('1'). When the ALARM-LATCH-DIS bit in the alarm control register is cleared ('0'), the ALARM pin is latched. Whenever an alarm status bit is set, that bit remains set until the event that caused the alarm is resolved and the status register is read. Reading the status registers clears the alarm status bit. The alarm bit can only be cleared by reading the status register after the event is resolved, or by hardware reset, software reset, or power-on reset. All alarm status bits are cleared when reading the status register, and all these bits are reasserted if the out-of-limit condition still exists after the next conversion cycle, unless otherwise noted. When the ALARM-LATCH-DIS bit in the alarm control register is set ('1'), the ALARM pin is not latched. The alarm bit goes to '0' when the error condition subsides, regardless of whether the bit is read or not. Table 22. Status Register BIT NAME DEFAULT R/W 15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. DESCRIPTION 14 CH0-ALR 0 R 0 = The analog input is not out of the specified range. 1 = The single-ended channel 0 or differential input pair (CH0+, CH1–) is out of the range defined by the corresponding threshold registers. 13 CH1-ALR 0 R 0 = The analog input is not out of the specified range. 1 = The single-ended channel 1 is out of the range defined by the corresponding threshold registers. 12 CH2-ALR 0 R 0 = The analog input is not out of the specified range. 1 = The single-ended channel 2 or differential input pair (CH2+, CH3–) is out of the range defined by the corresponding threshold registers. 11 CH3-ALR 0 R 0 = The analog input is not out of the specified range. 1 = The single-ended channel 3 is out of the range defined by the corresponding threshold registers. Local temperature underrange flag. 10 LT-Low-ALR 0 R 0 = The local temperature is not less than the range. 1 = The local temperature is less than the low-bound threshold. This bit is only checked when LT is enabled (EN-LT is '1'); this bit is ignored when EN-LT is '0'. Local temperature overrange flag. 9 LT-High-ALR 0 R 0 = The local temperature is not greater than the range. 1 = The local temperature is greater than the high-bound threshold. This bit is only checked when LT is enabled (EN-LT is '1'); this bit is ignored when EN-LT is '0'. Remote temperature reading of D1 when less than the range flag. 8 D1-Low-ALR 0 R 0 = The local temperature is not less than the range. 1 = The local temperature is less than the low-bound threshold. This bit is only checked when D1 is enabled (EN-D1 is '1'); this bit is ignored when EN-D1 is '0'. Remote temperature reading of D1 when greater than the range flag. 7 D1-High -ALR 0 R 0 = The local temperature is not greater than the range. 1 = The local temperature is greater than the high-bound threshold. This bit is only checked when D1 is enabled (EN-D1 is '1'); this bit is ignored when EN-D1 is '0'. Remote temperature reading of D2 when less than the range flag. 6 70 D2-Low-ALR 0 R 0 = The local temperature is not less than the range. 1 = The local temperature is less than the low-bound threshold. This bit is only checked when D2 is enabled (EN-D2 is '1'); this bit is ignored when EN-D2 is '0'. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Table 22. Status Register (continued) BIT NAME DEFAULT R/W DESCRIPTION Remote temperature reading of D2 when greater than the range flag. 5 D2-High -ALR 0 R 0 = The local temperature is not greater than the range. 1 = The local temperature is greater than the high-bound threshold. This bit is only checked when D2 is enabled (EN-D2 is '1'); this bit is ignored when EN-D2 is '0'. Remote sensor D1 failure flag. 4 D1-FAIL-ALR 0 R 0 = The sensor is in a normal condition. 1 = The sensor is an open-circuit or short-circuit. This bit is only checked when D1 is enabled (EN-D1 is '1'); this bit is ignored when EN-D1 is '0'. Remote sensor D2 failure flag. 3 D2-FAIL-ALR 0 R 0 = The sensor is in a normal condition. 1 = The sensor is an open-circuit or short-circuit. This bit is only checked when D2 is enabled (EN-D2 is '1'); this is ignored when EN-D2 is '0'. 2 THERM-ALR 0 R Thermal alarm flag. When the die temperature is equal to or greater than +150°C, the bit is set ('1') and the THERM-ALR flag activates. The on-chip temperature sensor (LT) monitors the die temperature. If LT is disabled, the THERM-ALR bit is always '0'. The hysteresis of this alarm is 8°C. 1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 71 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ADC Channel Register 0 (Read or Write, Address = 50h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 0 SE0 BIT 12 DF (CH0+, CH1–) SE1 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 DF (CH2+, CH3–) SE4 SE5 SE6 SE7 SE8 SE9 SE10 SE11 SE12 BIT 11 BIT 10 SE2 SE3 These bits specify the external analog auxiliary input channels (CH0 to CH12) to be converted. The specified channels are accessed sequentially in order from bit 14 to bit 0. The input is converted when the corresponding bit is set ('1'). Bit 15 Reserved Writing to this bit causes no change. Reading this bit returns '0'. Bits 14, 13, 11, 10, 8:0 SE0 to SE12 External single-ended analog input for CHn. The result is stored in ADC-n-data register in straight binary format. Bit 12 DF (CH0+, CH1–) External analog differential input pair, CH0 and CH1, with CH0 as positive and CH1 as negative. The difference of (CH0 – CH1) is converted and the result is stored in the ADC-0-data register in twos complement format. Bit 9 DF(CH2+, CH3-) External analog differential input pair, CH2 and CH3, with CH2 as positive and CH3 as negative. The difference of (CH2 – CH3) is converted and the result is stored in the ADC-2-data register in twos complement format. Table 23. CH0 and CH1 Bit Settings BIT 14 BIT 13 BIT 12 1 1 0 CH0 and CH1 are both accessed as single-ended inputs. Bit 12 is ignored. DESCRIPTION 1 0 0 CH0 is accessed as a single-ended input. CH1 is not accessed. Bit 12 is ignored. 0 1 0 CH1 is accessed as a singled-ended. CH0 is not accessed. Bit 12 is ignored. 0 0 1 Differential input pair CH0 + and CH1– is accessed as a differential input. 0 0 0 CH0, CH1, and differential pair CH0+, CH1– are not accessed. Table 24. CH2 and CH3 Bit Settings BIT 11 BIT 10 BIT 9 1 1 0 CH2 and CH3 are both accessed as single-ended inputs. Bit 9 is ignored. DESCRIPTION 1 0 0 CH2 is accessed as a single-ended input. CH3 is not accessed. Bit 9 is ignored. 0 1 0 CH3 is accessed as a singled-end input. CH2 is not accessed. Bit 9 is ignored. 0 0 1 Differential input pair CH2+ and CH3– is accessed as a differential input. 0 0 0 CH2, CH3, and differential pair CH2+, CH3– are not accessed. Table 25. CH4 to CH12 Bit Settings BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DESCRIPTION 1 — — — — — — — — CH4 is accessed as a single-ended input — 1 — — — — — — — CH5 is accessed as a single-ended input — — 1 — — — — — — CH6 is accessed as a single-ended input — — — 1 — — — — — CH7 is accessed as a single-ended input — — — — 1 — — — — CH8 is accessed as a single-ended input — — — — — 1 — — — CH9 is accessed as a single-ended input — — — — — — 1 — — CH10 is accessed as a single-ended input — — — — — — — 1 — CH11 is accessed as a single-ended input — — — — — — — — 1 CH12 is accessed as a single-ended input 72 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ADC Channel Register 1 (Read or Write, Address = 51h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 SE13 SE14 SE15 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 0 0 0 0 0 0 0 0 0 These bits specify the external analog auxiliary input channels (CH13, CH14, and CH15) to be converted. The specified channel is accessed sequentially in the order from bit 14 to bit 0 of ADC channel register 0, and then bit 14 to bit 12 of ADC channel register 1. The input is converted when the corresponding bit is set ('1'). Bits[14:12] SEn External single-ended analog input CHn. The result is stored in the ADC-n-data register in straight binary format. ADC Gain Register (Read or Write, Address = 52h, Default = FFFFh) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 ADG0 ADG1 ADG2 ADG3 ADG4 ADG5 ADG6 ADG7 ADG8 ADG9 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 ADG10 ADG11 ADG12 ADG13 ADG14 ADG15 Bit 15 ADG0 0 = The analog input range of single-ended input CH0 (SE0) is 0 V to VREF or differential input pair DF (CH0+, CH1–) is –VREF to +VREF 1 = The analog input range of single-ended input CH0 (SE0) is 0 V to (2 × VREF) or differential input pair DF (CH0+, CH1–) is (–2 × VREF) to (+2 × VREF) Bit 14 ADG1 0 = The analog input range of single-ended input CH1 (SE1) is 0 V to VREF 1 = The analog input range is 0 V to (2 × VREF) Bit 13 ADG2 0 = The analog input range of single-ended input CH2 (SE2) is 0 V to VREF or differential input pair DF (CH2+, CH3–) is –VREF to +VREF 1 = The analog input range of single-ended input CH2 (SE2) is 0 V to (2 × VREF) or differential input pair DF (CH2+, CH3–) is (–2 × VREF) to (+2 × VREF) Bit 12 ADG3 0 = The analog input range of single-end input CH3 (SE3) is 0 V to VREF 1 = The analog input range is 0 V to (2 × VREF) Bit[11:0] ADG4 to ADG15 0 = The analog input range of CHn (where n = 4 to 15) is 0 V to VREF 1 = The analog input range is 0 V to (2 × VREF) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 73 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com AUTO-DAC-CLR-SOURCE Register (Read or Write, Address = 53h, Default = 0004h) This register selects which alarm forces the DAC into a clear state, regardless of which DAC operation mode is active, auto, or manual. Table 26. AUTO-DAC-CLR-SOURCE Register BIT NAME DEFAULT R/W 15 — 0 R 14 CH0-ALR-CLR 0 R/W CH0 alarm clear bit. 0 = CH1-ALR goes to '1' and does not force any DAC to a clear status 1 = DAC-n is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the CH0-ALR bit in the status register are set ('1') 13 CH1-ALR-CLR 0 R/W CH1 alarm clear bit. 0 = CH1-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the CH1-ALR bit in the status register are set ('1') 12 CH2-ALR-CLR 0 R/W CH2 alarm clear bit. 0 = CH2-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the CH2-ALR bit in the status register are set ('1') R/W CH3 alarm clear bit. 0 = CH3-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the CH3-ALR bit in the status register are set ('1') R/W Local temperature sensor low alarm clear bit. 0 = LT-Low-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the LT-Low-ALR bit in the status register are set ('1') R/W Local temperature sensor high alarm clear bit. 0 = LT-High-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the LT-High-ALR bit in the status register are set ('1') R/W Remote temperature sensor D1 low alarm clear bit. 0 = D1-Low-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the D1-Low-ALR bit in the status register are set ('1') R/W Remote temperature sensor D1 high alarm clear bit. 0 = D1-High-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the D1-High-ALR bit in the status register are set ('1') R/W Remote temperature sensor D2 low alarm clear bit. 0 = D2-Low-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the D2-Low-ALR bit in the status register are set ('1') 74 0 DESCRIPTION Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 11 CH3-ALR-CLR 10 LT-Low-ALRCLR 9 LT-High-ALRCLR 8 D1-Low-ALRCLR 7 D1-High-ALRCLR 6 D2-Low-ALRCLR 5 D2-High-ALRCLR 0 R/W Remote temperature sensor D2 high alarm clear bit. 0 = D2-High-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the D2-High-ALR bit in the status register are set ('1') 4 D1-FAIL-CLR 0 R/W D1 fail alarm clear bit. 0 = D1-FAIL-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the D2-FAIL-ALR bit in the status register are set ('1') 3 D2-FAIL-CLR 0 R/W D2 fail alarm clear bit. 0 = D2-FAIL-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the D2-FAIL-ALR bit in the status register are set ('1') 2 THERM-ALRCLR 1 R/W Thermal alarm clear bit. 0 = THERM-ALR goes to '1' and does not force any DAC to a clear status 1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN register and the THERM-ALR bit in the status register are set ('1') 1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 0 0 0 0 0 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 AUTO-DAC-CLR-EN Register (Read or Write, Address = 54h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 ACLR 11 Bits[14:3] ACLR 10 ACLR 9 ACLR 8 ACLR 7 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 ACLR 6 ACLR 5 ACLR 4 ACLR 3 ACLR 2 ACLR 1 ACLR 0 0 0 0 ACLRn Auto clear DAC-n enable bit. 0 = DAC-n is not forced to a clear state when the alarm occurs (default) 1 = DAC-n is forced to a clear state when the alarm occurs NOTE ACLRn is always ignored when an alarm occurs for a temperature greater than +150°C (THERM-ALR is '1'). If an alarm activates for a temperature greater than +150°C, and if the THERM-ALR-CLR bit in the AUTO-DAC-CLR-SOURCE register is set ('1'), all DACs are forced into a clear status. However, if THERM-ALR-CLR is cleared ('0'), the over +150°C alarm does not force any DAC to a clear status. SW-DAC-CLR Register (Read or Write, Address = 55h, Default = 0000h) This register uses software to force the DAC into a clear state. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 ICLR 11 Bits[14:3] ICLR 10 ICLR 9 ICLR 8 ICLR 7 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 ICLR 6 ICLR 5 ICLR 4 ICLR 3 ICLR 2 ICLR 1 ICLR 0 0 0 0 ICLRn Software clear DACn bit. 0 = DACn is restored to normal operation 1 = DACn is forced into a clear state HW-DAC-CLR-EN 0 Register (Read or Write, Address = 56h, Default = 0000h) This register determines which DAC is in a clear state when the DAC-CLR-0 pin goes low. MSB BIT 15 0 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR 11 10 9 8 7 6 5 4 3 2 1 0 Bits[14:3] BIT 2 BIT 1 LSB BIT 0 0 0 0 H0CLRn: Hardware clear DAC-n enable 1 bit. If H0CLRn = '1', DAC-n is forced into a clear state when the DAC-CLR-0 pin goes low. If H0CLRn = '0', pulling the DAC-CLR-0 pin low does not effect the state of DAC-n. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 75 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com HW-DAC-CLR-EN 1 Register (Read or Write, Address = 57h, Default = 0000h) This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low. MSB BIT 15 0 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 0 H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR 11 10 9 8 7 6 5 4 3 2 1 0 Bits[14:3] H1CLRn Hardware clear DAC-n enable 1 bit. 0 = Pulling the DAC-CLR-1 pin low does not effect the state of DAC-n 1 = DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low DAC Configuration Register (Read or Write, Address = 58h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 Bits[11:0] 0 0 SLDA 11 SLDA 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 SLDA 9 SLDA 8 SLDA 7 SLDA 6 SLDA 5 SLDA 4 SLDA 3 SLDA 2 SLDA 1 SLDA 0 SLDA-n DAC synchronous load enable bit. 0 = Asynchronous load is enabled. A write command to the DAC-n-data register immediately updates the DAC-n latch and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default value of SLDA-n is '0'. The device updates the DAC latch only if the ILDAC bit is set ('1'), thereby eliminating unnecessary glitches. Any DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output changes to the new level immediately. Note that the SLDA-n bit is ignored in auto mode (DAC-n mode bits do not equal '00'). In auto mode, the DAC latch is always updated asynchronously. 1 = Synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n latch is loaded with the value of the corresponding DACn-data register, and the output of DAC-n is updated immediately. The internal load DAC signal ILDAC is generated by writing a '1' to the ILDAC bit in the AMC configuration register. In synchronous load, a write command to the DAC-n-data register updates that register only, and does not change the DAC-n output. NOTE The DACs can be forced to a clear state immediately by the external DAC-CLR-n signal, by alarm events, and by writing to the SW-DAC-CLR register. In these cases, the SLDA-n bit is ignored. DAC Gain Register (Read or Write, Address = 59h, Default = 0000h) The DACn GAIN bits specify the output range of DACn. MSB BIT 15 BIT 14 BIT 13 BIT 12 0 0 Bits[11:0] 0 0 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 DAC11 GAIN DAC10 GAIN DAC9 GAIN DAC8 GAIN DAC7 GAIN DAC6 GAIN DAC5 GAIN DAC4 GAIN DAC3 GAIN DAC2 GAIN DAC1 GAIN DAC0 GAIN DACnGAIN: DACn gain bits. 1 = Gain is 5 and the output is 0 V to 5 × VREF 0 = Gain is 2 and the output is 0 V to 2 × VREF 76 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Analog Input Channel Threshold Registers (Read or Write, Addresses = 5Ah to 61h) Four analog auxiliary inputs (CH0, CH1, CH2, and CH3) and three temperature sensors (LT, D1, and D2) implement an out-of-range alarm function. Threshold-High-n and Threshold-Low-n (where n = 0, 1, 2, 3) define the upper bound and lower bound of the nth analog input range, as shown in Table 27. This window determines whether the nth input is out-of-range. When the input is outside the window, the corresponding CH-ALR-n bit in the status register is set to '1'. For normal operation, the value of Threshold-High-n must be greater than the value of Threshold-Low-n; otherwise, CH-ALR-n is always set to '1' and an alarm is always indicated. Note that when the analog channel is accessed as single-ended input, its threshold is in a straight binary format. However, when the channel is accessed as a differential pair, its threshold is in twos complement format. Table 27. Threshold Coding INPUT CHANNEL INPUT TYPE THRESHOLD STORED IN FORMAT Channel 0 Single-ended Input-0-Threshold-High-Byte Input-0-Threshold-Low-Byte Straight binary Channel 1 Single-ended Input-1-Threshold-High-Byte Input-1-Threshold-Low-Byte Straight binary Channel 2 Single-ended Input-2-Threshold-High-Byte Input-2-Threshold-Low-Byte Straight binary Channel 3 Single-ended Input-3-Threshold-High-Byte Input-3-Threshold-Low-Byte Straight binary CH0+, CH1– Differential Input-0-Threshold-High-Byte Input-0-Threshold-Low-Byte Twos complement CH2+, CH3– Differential Input-2-Threshold-High-Byte Input-2-Threshold-Low-Byte Twos complement Input-n-High-Threshold Register (where n = 0, 1, 2, 3) (Read or Write, Default = 0FFFh) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 Bits[15:12] 0 0 THRH 11 THRH 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRH 9 THRH 8 THRH 7 THRH 6 THRH 5 THRH 4 THRH 3 THRH 2 THRH 1 THRH 0 Reserved These bits are '0' when read back. Writing to these bits has no effect. Bits[11:0] THRHn Data bits of the upper-bound threshold of the nth analog input. Input-n-Low-Threshold Register (where n = 0, 1, 2, 3) (Read or Write, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 Bits[15:12] 0 0 0 THRL 11 THRL 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRL 9 THRL 8 THRL 7 THRL 6 THRL 5 THRL 4 THRL 3 THRL 2 THRL 1 THRL 0 Reserved These bits are '0' when read back. Writing to these bits has no effect. Bits[11:0] THRLn Data bits of the lower-bound threshold of the nth analog input. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 77 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Temperature Threshold Registers LT-High-Threshold Register (Read or Write, Address = 62h, Default = 07FFh, +255.875°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRH 11 THRH 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRH 9 THRH 8 THRH 7 THRH 6 THRH 5 THRH 4 THRH 3 THRH 2 THRH 1 THRH 0 Bits[15:12] are ‘0' when read back. Writing these bits causes no change LT-Low-Threshold Register (Read or Write, Address = 63h, Default = 0800h, –256°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRL 11 THRL 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRL 9 THRL 8 THRL 7 THRL 6 THRL 5 THRL 4 THRL 3 THRL 2 THRL 1 THRL 0 Bits[15:12] are reserved. Writing to these bits causes no change. Reading these bits returns '0'. D1-High-Threshold Register (Read or Write, Address = 64h, Default = 07FFh, +255.875°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRH 11 THRH 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRH 9 THRH 8 THRH 7 THRH 6 THRH 5 THRH 4 THRH 3 THRH 2 THRH 1 THRH 0 Bits[15:12] are ‘0' when read back. Writing these bits causes no change. D1-Low-Threshold Register (Read or Write, Address = 65h, Default = 0800h, –256°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRL 11 THRL 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRL 9 THRL 8 THRL 7 THRL 6 THRL 5 THRL 4 THRL 3 THRL 2 THRL 1 THRL 0 Bits[15:12] are ‘0' when read back. Writing these bits causes no change. D2-High-Threshold Register (Read or Write, Address = 66h, Default = 07FFh, +255.875°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRH 11 THRH 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRH 9 THRH 8 THRH 7 THRH 6 THRH 5 THRH 4 THRH 3 THRH 2 THRH 1 THRH 0 Bits[15:12] are ‘0' when read back. Writing these bits causes no change. D2-Low-Threshold Register (Read or Write, Address = 67h, Default = 0800h, –256°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRL 11 THRL 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRL 9 THRL 8 THRL 7 THRL 6 THRL 5 THRL 4 THRL 3 THRL 2 THRL 1 THRL 0 Bits[15:12] are ‘0' when read back. Writing these bits causes no change. 78 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Hysteresis Registers The hysteresis registers define the hysteresis in the alarm detection of an individual alarm. Hysteresis Register 0 (Read or Write, Address = 68h, Default = 0810h, 8 LSB) This register contains the hysteresis values for CH0 and CH1. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 CH0CH0CH0CH0CH0CH0CH0CH1CH1CH1CH1CH1CH1CH1HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 Bits[14:8] LSB BIT 0 0 CH0-HYS-n Hysteresis of CH0, 1 LSB per step. Bits[7:1] CH1-HYS-n Hysteresis of CH1, 1 LSB per step. Hysteresis Register 1 (Read or Write, Address = 69h, Default = 0810h, 8 LSB) This register contains the hysteresis values for CH2 and CH3. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 CH2CH2CH2CH2CH2CH2CH2CH3CH3CH3CH3CH3CH3CH3HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 Bits[14:8] LSB BIT 0 0 CH2-HYS-n Hysteresis of CH2, 1 LSB per step. Bits[7:1] CH3-HYS-n Hysteresis of CH3, 1 LSB per step. Hysteresis Register 2 (Read or Write, Address = 6Ah, Default = 2108h, 8°C) This register contains the hysteresis values for D2, D1, and LT. The range is 0°C to +31°C. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 D2D2D2D2D2D1D1D1D1D1LTLTLTLTLTHYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 Bits[14:10] D2-HYS-n Hysteresis of D2, 1°C per step. Note that bits D2-HYS-[2:0] are always '0'. Bits[9:5] D1-HYS-n Hysteresis of D1, 1°C per step. Note that bits D1-HYS-[2:0] are always '0'. Bits[4:0] LT-HYS-n Hysteresis of LT, 1°C per step. Note that bits LT-HYS-[2:0] are always '0'. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 79 AMC7812B SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Power-Down Register (Read or Write, Address = 6Bh, Default = 0000h) After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled by this register are either powered-down or off. The Power-Down Register allows the host to manage the AMC7812B power dissipation. When not required, the ADC, the reference buffer amplifier, and any of the DACs can be put into an inactive low-power mode to reduce current drain from the supply. The bits in the Power-Down Register control this power-down function. Set the respective bit to '1' to activate the corresponding function. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 PADC Bit 14 PREF PDAC 0 PDAC 1 PDAC 2 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 PDAC 3 PDAC 4 PDAC 5 PDAC 6 PDAC 7 PDAC 8 PDAC 9 PDAC 10 PDAC 11 LSB BIT 0 0 PADC Power-down mode control bit. 0 = The ADC is inactive in low-power mode. 1 = The ADC is in normal operating mode. Bit 13 PREF Internal reference in power-down mode control bit. 0 = The reference buffer amplifier is inactive in low-power mode. 1 = The reference buffer amplifier is powered on. Bits[12:1] PDACn DACn power-down control bit. 0 = DACn is inactive in low-power mode and its output buffer amplifier is in a Hi-Z state. The output pin of DACn is internally switched from the buffer output to the analog ground through an internal resistor. 1 = DACn is in normal operating mode. Device ID Register (Read-Only, Address = 6Ch, Default = 1221h) Model and revision information. Software Reset Register (Read or Write, Address = 7Ch, Default = NA) The software reset register resets all registers to the default values, except for the DAC data register, DAC latch, and DAC clear register. The software reset is similar to a hardware reset, which resets all registers including the DAC data register, DAC latch, and DAC clear register. After a software reset, make sure that the DAC data register, DAC latch, and DAC clear register are set to the desired values before the DAC is powered on. SPI Mode In SPI Mode, writing 6600h to this register forces the device reset. I2C Mode Writing to this register (with any data) forces the device to perform a software reset. Reading this register returns an undefined value that must be ignored. Note that this register is 8-bit, instead of 16-bit. Both reading from and writing to this register are single-byte operations. Writing data to the software reset register in I2C mode is described in the following steps: 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a write operation. 3. The AMC7812B asserts an acknowledge signal on SDA. 4. The master sends register address 7Ch. 5. The AMC7812B asserts an acknowledge signal on SDA. 6. The master sends a data byte. 7. The AMC7812B asserts an acknowledge signal on SDA. 8. The master asserts a stop condition to end the transaction. 80 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B AMC7812B www.ti.com SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2013) to Revision A • Page Changed device status to Production Data .......................................................................................................................... 1 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: AMC7812B 81 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) AMC7812BSPAP ACTIVE HTQFP PAP 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AMC7812B AMC7812BSPAPR ACTIVE HTQFP PAP 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AMC7812B AMC7812BSRGCR ACTIVE VQFN RGC 64 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AMC7812B AMC7812BSRGCT ACTIVE VQFN RGC 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AMC7812B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of