BQ2005PN

bq2005 Fast-Charge IC for DualBattery Packs Features General Description be used to gate an externally reg ulated charging cur rent. ∗ Sequential fast charge and con ditioning of two NiCd or NiMH nickel cadmium or nickel-metal hydride bat tery packs The bq2005 Fast-Charge IC provides com pre hen sive fast charge control func tions to gether with high-speed switching power control circuitry on a mono lithic CMOS device for sequential charge man age ment in dual battery pack ap pli ca tions. Fast charge may be gin on ap pli ca tion of the charg ing sup ply, re place ment of the battery, or switch de pres sion. For safety, fast charge is in hib ited unless/un til the bat tery tem per a ture and volt age are within con fig ured lim its. ∗ Hysteretic PWM switch-mode cur rent regulation or gated control of an ex ter nal reg u la tor ∗ Easily integrated into sys tems or used as a stand-alone charger ∗ Pre-charge qual i fi ca tion of tem per ature and volt age ∗ Direct LED outputs dis play bat tery and charge sta tus ∗ Fast-charge ter mi na tion by ∆ temperature/∆ time, -∆V, max i mum volt age, max i mum tem per a ture, and max i mum time ∗ Optional top-off and pulse-trickle charging Pin Connections In te gra tion of closed-loop cur rent control circuitry al lows the bq2005 to be the basis of a cost-effective solution for stand-alone and sys tem-integrated charg ers for bat ter ies of one or more cells. S w i t c h - a c t i v a t e d dis-charge-before-charge al lows bq2005-based chargers to support bat tery conditioning and capacity de ter mination. High-efficiency power con ver sion is accomplished using the bq2005 as a hysteretic PWM con trol ler for switch-mode regulation of the charging cur rent. The bq2005 may alternatively Temperature, volt age, and time are mon i tored throughout fast charge. Fast charge is ter mi nated by any of the fol low ing: n Rate of temperature rise ( ∆T/∆t) n Negative delta voltage (-∆V) n Maximum voltage n Maximum temperature n Maximum time Af ter fast charge, op tional top-off and pulsed current maintenance phases are avail able. Pin Names DCMDA Dis charge com mand in put, DISA bat tery A DVEN -DV en able TM1 Timer mode se lect 1 TM2 Dis charge con trol out put, bat tery A CHA, CHB Charge status out put, bat tery A/B Timer mode se lect 2 FCCA, FCCB Fast charge com plete out put, bat tery A/B TCO Tem pera ture cut- off VSS Sys tem ground TSA, TSB Tem pera ture sense in put, bat tery A/B VCC 5.0V ±10% power BAT A, BAT B Bat tery volt age in put, bat tery A/B MODA, MODB Charge cur rent con trol out put, bat tery A/B SNSA, SNSB Sense re sis tor in put , bat tery A/B SLUS079A - AU GUST 2000 G 1 bq2005 DISA Pin Descriptions DCMDA Push-pull output used to control an external transistor to discharge battery A before charging. Discharge-before-charge control input, battery A DCMDA controls the discharge-before-charge function of the bq2005. A negative-going pulse on DCMDA initiates a discharge to EDV followed by a charge if conditions allow. By tying DCMDA to ground, automatic discharge-before-charge is enabled on every new charge cycle start. DVEN CHA, CHB FCCA, FCCB -∆ V enable input MODA, MODB VCC Temperature cutoff threshold input Vss Temperature sense inputs Voltage inputs The battery voltage sense input, referenced to SNSA,B, respectively. This is created by a high-impedance resistor divider network connected between the positive and the negative terminals of the battery. SNSA, SNSB VCC supply input 5.0 V, ±10% power input. Input, referenced to SNSA or SNSB, respectively, for an external thermistor monitoring battery temperature. BATA, BATB Charge current control outputs MODA,B is a push-pull output that is used to control the charging current to the battery. MODA,B switches high to enable charging current to flow and low to inhibit charging c u r r e n t flow t o b a t t e r i e s A a n d B, respectively. Timer mode inputs Input to set maximum allowable battery temperature. If the potential between TSA and SNSA or TSB and SNSB is less than the voltage at the TCO input, then fast charge or top-off charge is terminated for the corresponding battery pack. TSA, TSB Fast charge complete outputs Open-drain outputs indicating fast charge complete for batteries A and B, respectively. See Figure 1 and Table 2. TM1 and TM2 are three-state inputs that configure the fast charge safety timer, -∆V holdoff time, and that enhance/disable top-off. See Table 2. TCO Charge status outputs Push-pull outputs indicating charging status for batteries A and B, respectively. See Figure 1 and Table 2. This input enables/disables -∆ V charge termination. If DVEN is high, the -∆ V test is enabled. If DVEN is low, -∆ V test is disabled. The state of DVEN may be changed at any time. TM1– TM2 Discharge control output Charging current sense inputs, SNSA,B controls the switching of MODA,B based on the voltage across an external sense resistor in the current path of the battery. SNS is the reference potential for the TS and BAT pins. If SNS is connected to VSS, MOD switches high at the beginning of charge and low at the end of charge. 2 Ground bq2005 Functional Description Discharge-Before-Charge Figure 3 shows a block diagram and Figure 4 shows a state diagram of the bq2005. The DCMDA input is used to command dischargebefore-charge via the DISA output. Once activated, DISA becomes active (high) until VCELL falls below VEDV where: Battery Voltage and Temperature Measurements VEDV = 0.475 ∗ VCC ± 30mV at which time DISA goes low and a new fast charge cycle begins. Battery voltage and temperature are monitored for maximum allowable values. The voltage presented on the battery sense input, BATA,B, must be divided down to between 0.95 ∗ VCC and 0.475 ∗ VCC for proper operation. A resistor-divider ratio of: The DCMDA input is internally pulled up to VCC (its inactive state). Leaving the input unconnected, therefore, results in disabling discharge-before-charge. A negative going pulse on DCMDA initiates discharge-before-charge a t any t ime r egardless of t he current state of the bq2005. If DCMDA is tied to VSS, discharge-beforecharge will be the first step in all newly started charge cycles. RB1 N = −1 RB2 2.375 is recommended to maintain the battery voltage within the valid range, where N is the number of cells, RB1 is the resistor connected to the positive battery terminal, and RB2 is the resistor connected to the negative battery terminal. See Figure 1. Starting A Charge Cycle Anew charge cycle is started by (see Figure 2): Note: This resistor-divider network input impedance to end-to-end should be at least 200kΩ and less than 1MΩ. A ground-referenced negative temperature coefficient thermistor placed in proximity to the battery may be used as a low-cost temperature-to-voltage transducer. The temperature sense voltage input at TSA,B is developed using a resistor-thermistor network between VCC and VSS. See Figure 1. Both the BATA,B and TSA,B inputs are referenced to SNSA,B, so the signals used inside the IC are: 1. VCC rising above 4.5V 2. VCELL falling through the maximum cell voltage, VMCV where: VMCV = 0.95 ∗ VCC ± 30mV If DCMDA is tied low, a discharge-before-charge will be executed as the first step of the new charge cycle. Otherwise, pre-charge qualification testing will be the first step. VBAT(A,B) - VSNS(A,B) = VCELL(A,B) The battery must be within the configured temperature and voltage limits before fast charging begins. and VTS(A,B) - VSNS(A,B) = VTEMP(A,B) Negative Temperature Coefficient Thermister VCC PACK + RT1 PACK+ bq2005 TSA,B RB1 bq2005 BATA,B RB2 SNSA,B RT2 SNSA,B PACK- N T C PACK - Fg2005-1.eps Figure 1. Voltage and Temperature Monitoring 3 bq2005 The valid battery voltage range is VEDV < VBAT < VMCV. The valid temperature range is VHTF < VTEMP < VLTF, where: pending state; the charger remains in this state as long as the voltage or temperature conditions are outside of the allowed limits. If the voltage is too high, the chip goes to the battery absent state and waits until a new charge cycle is started. VLTF = 0.4 ∗ VCC ± 30mV VHTF = [(1/4 ∗ VLTF) + (3/4 ∗ VTCO)] ± 30mV Fast charge continues until termination by one or more of the five possible termination conditions: VTCO is the voltage presented at the TCO input pin, and is configured by the user with a resistor divider between VCC and ground. The allowed range is 0.2 to 0.4 ∗ VCC. Delta temperature/delta time (∆T/∆t) Negative delta voltage (-∆ V) If the temperature of the battery is out of range, or the voltage is too low, the chip enters the charge pending state and waits for both conditions to fall within their allowed limits. The MODA,B output is modulated to provide the configured trickle charge rate in the charge pending state. There is no time limit on the charge Discharge Charge Pending* Maximum voltage Maximum temperature Maximum time Fast Charging Top-Off Pulse-Trickle (Optional) (Optional (Pulse-Trickle) Battery A) DISA 260 s 4s Switch-mode MODA,B Configuration Note* 34s 260 s 4s or External MODA,B Regulation 34s Note* CHA,B Status Output FCCA,B Status Output Battery within temperature/voltage limits. Battery discharged to 0.475 * VCC. Battery outside temperature/voltage limits. Discharge-Before-Charge started *See Table 3 for pulse-trickle period. T200501.eps Figure 2. Charge Cycle Phases 4 bq2005 Table 1. Fast Charge Safety Time/Hold-Off/Top-Off Table Corresponding Fast-Charge Rate C/4 C/2 1C 2C 4C C/2 1C 2C 4C Note: TM1 Low Float High Low Float High Low Float High Typical Fast-Charge and Top-Off Time Limits 360 180 90 45 23 180 90 45 23 TM2 Low Low Low Float Float Float High High High Typical -∆ V/MCV Hold-Off Time (seconds) 137 820 410 200 100 820 410 200 100 Top-Off Rate Disabled Disabled Disabled Disabled Disabled C/16 C/8 C/4 C/2 Typical conditions = 25°C, VCC = 5.0V. - V Termination Temperature Sampling If the DVEN input is high, the bq2005 samples the voltage at the BAT pin once every 34s. If VCELL is lower than any previously measured value by 12mV ±4mV, fast charge is terminated. The -∆V test is valid in the range VMCV - (0.2 ∗ VCC) < VCELL < VMCV. Each sample is an average of 16 voltage measurements t a k e n 57µs a p a r t . The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%. Voltage Sampling Maximum Voltage, Temperature, and Time Each sample is an average of 16 voltage measurements t a k e n 57µs a p a r t . The r e s u l t i n g s a m p l e period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%. Anytime VCELL rises above VMCV, CHG goes high (the LED goes off) immediately. If the bq2005 is not in the voltage hold-off period, fast charging also ceases immediately. If VCELL then falls back below VMCV before t MCV = 1s (maximum), the chip transitions to the Charge Complete state (maximum voltage termination). If VCELL remains above VMCV at the expiration of t MCV, the bq2005 transitions to the Battery Absent state (battery removal). See Figure 4. Voltage Termination Hold-off A hold-off period occurs at the start of fast charging. During the hold-off period, -∆V termination is disabled. This avoids premature termination on the voltage spikes sometimes produced by older batteries when fast-charge current is first applied. ∆T/∆t, maximum voltage and maximum temperature terminations are not affected by the hold-off period. Maximum temperature termination occurs anytime the voltage on the TS pin falls below the temperature cut-off threshold VTCO. Charge will also be terminated if VTEMP rises above the minimum temperature fault threshold, VLTF, after fast charge begins. Maximum charge time is configured using the TM pin. Time settings are available for corresponding charge rates of C/4, C/2, 1C, and 2C. Maximum time-out termination is enforced on the fast-charge phase, then reset, and enforced again on the top-off phase, if selected. There is no time limit on the trickle-charge phase. T/ t Termination The bq2005 samples at the voltage at the TS pin every 34s, and compares it to the value measured two samples earlier. If VTEMP has fallen 16mV ±4mV or more, fast charge is terminated. The ∆T/∆t termination test is valid only when VTCO < VTEMP < VLTF. Top-off Charge An optional top-off charge phase may be selected to follow fast charge termination for the C/2 through 4C rates. This phase may be necessary on NiMH or other 5 bq2005 battery chemistries that have a tendency to terminate charge prior to reaching full capacity. With top-off enabled, charging continues a t a r educed r ate after fast-charge termination for a period of time selected by the TM1 and TM2 input pins. (See Table 2.) During top-off, the CC pin is modulated at a duty cycle of 4s active for every 30s inactive. This modulation results in an average rate 1/8th that of the fast charge rate. Maximum voltage, time, and temperature are the only termination methods enabled during top-off. selected), and then maintenance charging on both. If only battery A is present, the charge cycle begins on A and continues until fast charge termination even if a battery is inserted in channel B in the meantime. A new battery insertion in channel B while A is in the top-off phase terminates top-off on A and begins a new charge cycle on B. If A is configured for or commanded to discharge-before-charge, the discharge may take place while channel B is the active charging channel. When the discharge is complete, if B is still the active channel battery A enters the Charge Pending state until A becomes the active channel. Pulse-Trickle Charge Pulse-trickle charging follows the fast charge and optional top-off charge phases to compensate for selfdischarge of the battery while it is idle in the charger. The configured pulse-trickle rate is also applied in the charge pending state to raise the voltage of an overdischarged battery up to the minimum required before fast charge can begin. Charge Current Control The bq2005 controls charge current through the MODA,B output pin. The current control circuitry is designed to support implementation of a constant-current switching regulator or to gate an externally regulated current source. When used in switch mode configuration, the nominal regulated current is: In the pulse-trickle mode, MOD is active for 260µs of a period specified by the settings of TM1 and TM2. See Table 1. The resulting trickle-charge rate is C/64 when top-off is enabled and C/32 when top-off is disabled. Both pulse trickle and top-off may be disabled by tying TM1 and TM2 to VSS. I REG = 0.225V/RSNS Charge current is monitored at the SNSA,B input by the voltage drop across a sense resistor, RSNS, between the low side of the battery pack and ground. RSNS is sized to provide the desired fast charge current. Charge Status Indication If the voltage at the SNSA,B pin is less than VSNSLO, the MODA,B output is switched high to pass charge current to the battery. Charge status is indicated by the CHG output. The state of the CHG output in the various charge cycle phases is shown in Figure 4 and illustrated in Figure 2. When the SNSA,B voltage is greater than VSNSHI, the MODA,B output is switched low—shutting off charging current to the battery. Temperature status is indicated by the TEMP output. TEMP is in the high state whenever VTEMP is within the temperature window defined by the VLTF and VHTF temperature limits, and is low when the battery temperature is outside these limits. VSNSLO = 0.04 ∗ VCC ± 25mV VSNSHI = 0.05 ∗ VCC ± 25mV In all cases, if VCELL exceeds the voltage at the MCV pin, both CHG and TEMP outputs are held high regardless of other conditions. CHG and TEMP may both be used to directly drive an LED. When used to gate an externally regulated current source, the SNSA,B pin is connected to VSS, and no sense resistor is required. Pack Sequencing If both batteries A and B are present when a new charge cycle is started, the charge cycle starts on battery B and B remains the active channel until fast charge termination. Then battery A will be fast charged, followed by a top-off phase on B (if selected), a top-off phase on A (if 6 bq2005 TM1 TCO TM2 TIMING CONTROL OSC TCO TCO CHECK CHECK FCC FCC CH CH - A B A - TSA TSB LTF DISPLAY CONTROL CHECKLTF CHECK B V TS - V SNS SNSA A/D A/D DCMD A SNSB V BAT - V SNS CHARGE CONTROL STATE MACHINE DVEN EDV EDV CHECK CHECK MCV DISCHARGE CONTROL DIS A CHECK MCV CHECK MOD CONTROL MOD A MOD V CC B - - BATA BATB V SS BD2005 Figure 3. Block Diagram 7 bq2005 New Charge Cycle Started by either one of: VCC rising to valid level Battery replacement (VCELL falling through V MCV) DCMDA tied to ground? (channel A only) Yes No or channel B VEDV < VCELL < VMCV Charge Pending Rising edge on DCMD A VCELL < VEDV Battery Voltage? VCELL < VEDV VTEMP > VLTF or Trickle VTEMP < VHTF Battery CHG = 1/8s Temperature? flash FCC = high VHTF < VTEMP < VLTF VCELL > VMCV Discharge CH A = 1/8s flash FCC A = high VCELL > VMCV VCELL > VMCV Battery Absent VEDV < VCELL < VMCV and VHTF < VTEMP < VLTF Fast CHG = low FCC = high VCELL > VMCV - V or T/ t or VTEMP < VTCO or Maximum Time Out Top-off selected? Trickle CHG = high FCC = high Yes VCELL > VMCV VCELL < VMCV Top-off CHG = high FCC = low No t> tMCV Trickle CHG = high FCC = high VCELL > VMCV VTEMP < VTCO or Maximum Time Out Charge Complete Trickle CHG = high FCC = low SD2005 Figure 4. State Diagram 8 bq2005 Absolute Maximum Ratings Minimum Maximum Unit VCC Symbol VCC relative to VSS -0.3 +7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 +7.0 V TOPR Operating ambient temperature -20 +70 °C TSTG Storage temperature -55 +125 °C TSOLDER Soldering temperature - +260 °C TBIAS Temperature under bias -40 +85 °C Note: Parameter Commercial 10s max. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Thresholds Symbol Notes (TA = TOPR; VCC ±10%) Parameter Rating Tolerance Unit VSNSHI High threshold at SNSA,B resulting in MODA,B = Low 0.05 * VCC ±0.025 V VSNSLO Low threshold at SNSA,B resulting in MODA,B = High 0.04 * VCC ±0.010 V VLTF Low-temperature fault 0.4 * VCC ±0.030 V VTEMP ≥ VLTF inhibits/ terminates charge VHTF High-temperature fault (1/4 * VLTF) + (3/4 * VTCO) ±0.030 V VTEMP ≤ VHTF inhibits charge VEDV End-of-discharge voltage 0.475 * VCC ±0.030 V VCELL < VEDV inhibits fast charge VMCV Maximum cell voltage 0.95 * VCC ±0.030 V VCELL > VMCV inhibits/ terminates charge VTHERM TS input change for ∆T/∆t detection 16 ±4 mV -∆V BAT input change for -∆V detection 12 ±4 mV 9 Notes bq2005 Recommended DC Operating Conditions (TA = 0 to +70°C) Symbol Parameter Minimum Typical Maximum Unit 4.5 5.0 5.5 V 0 - VCC V VCC Supply voltage VCELL BAT voltage potential VBAT Battery input 0 - VCC V VTEMP TS voltage potential 0 - VCC V VTS Thermistor input 0 - VCC V VTCO Temperature cutoff VIH VIL 0.2 * VCC - 0.4 * VCC V Logic input high 2.0 - - V Notes VBAT - VSNS VTS - VSNS DCMDA, DVEN Logic input high VCC - 0.3 - - V TM1, TM2 Logic input low - - 0.8 V DCMDA, DVEN Logic input low - - 0.3 V TM1, TM2 VOH Logic output high VCC - 0.5 - - V DISA, MODA,B, IOH ≤ -5mA VOL Logic output low - - 0.5 V DISA, FCCA,B, CHA,B, MODA,B, IOL ≤ 5mA ICC Supply current - 1.0 3.0 mA Outputs unloaded I OH DISA, MODA,B source -5.0 - - mA @VOH = VCC - 0.5V I OL DISA, FCCA,B, MODA,B, CHA,B sink 5.0 - - mA @VOL = VSS + 0.5V IL - - Input leakage ±1 µA DVEN, V = VSS to VCC - - -400 µA DCMDA, V = VSS I IL Logic input low source - - 70.0 µA TM1, TM2, V = VSS to VSS + 0.3V I IH Logic input high source -70.0 - - µA TM1, TM2, V = VCC - 0.3V to VCC I IZ TM1, TM2 tri-state open detection -2.0 - 2.0 µA TM1, TM2 should be left disconnected (floating) for Z logic input state. I BAT Input current to BATA,B when battery is removed - - -20 µA VCC = 5.0V; TA = 25°C; input should be limited to this current when input exceeds VCC. Note: All voltages relative to VSS, except as noted. 10 bq2005 Impedance Symbol Parameter Minimum Typical Maximum Unit RBATA,B Battery A/B input impedance 50 - - MΩ RTSA,B TSA,B input impedance 50 - - MΩ RTCO TCO input impedance 50 - - MΩ RSNSA,B SNSA,B input impedance 50 - - MΩ Timing Symbol (TA = 0 to +70°C; VCC ±10%) Parameter Minimum Typical Maximum Unit t PW Pulse width for DCMDA, pulse command 1 - - µs Pulse start for discharge-beforecharge dFCV Time base variation -16 - 16 % VCC = 4.5V to 5.5V t REG MOD output regulation frequency - - 300 kHz t MCV Maximum voltage termination time limit - - 1 s Note: Typical is at TA = 25°C, VCC = 5.0V. 11 Notes Time limit to distinguish battery removed from charge complete bq2005 Data Sheet Revision History Change No. Page No. Description Nature of Change 3 9 VSNSLO rating Was VSNSHI - (0.01 * VCC); is 0.04 * VCC 4 5 Corrected sample period Was: 32s; Is: 34s 4 5, 9 Corrected -∆V threshold Was: 13mV Is: 12mV 4 All Revised and expanded format of this Clarification data sheet 5 9 6 1, 13 Notes: TOPR Deleted industrial temperature range Deleted DIP package option Removed DIP from pinout drawing and Ordering Information; deleted DIP package specifications Change 3 = Sept. 1996 D changes from Nov. 1993 C. Change 4 = Nov. 1997 E changes from Sept. 1996 D. Change 5 = June 1999 F changes from Nov. 1997 E. Change 6 = Aug. 2000 G changes from June 1999 F Ordering Information bq2005 Package Option: S = 20-pin SOIC Device: bq2005 Dual-Battery Fast-Charge IC 12 bq2005 S: 20-Pin SOIC 20-Pin S (SOIC) e D Dimension Minimum A 0.095 A1 0.004 B 0.013 C 0.008 D 0.500 E 0.290 e 0.045 H 0.395 L 0.020 All dimensions are in inches. B E H A C .004 L A1 13 Maximum 0.105 0.012 0.020 0.013 0.515 0.305 0.055 0.415 0.040 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ2005S ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 2005S -D Samples BQ2005STR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 2005S -D Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of