BQ2026DBZR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 1.5K-Bit Serial EPROM with SDQ Interface 1 Features 3 Description • The bq2026 is a 1.5K-bit serial EPROM containing a factory-programmed, unique 48-bit identification number, 8-bit family code, and a 64-bit status register. 1 • • • • • • 1536 Bits of One-Time Programmable (OTP) EPROM For Storage Of User-Programmable Configuration Data Factory-Programmed Unique 64-Bit Identification Number Single-Wire Interface to Reduce Circuit Board Routing Synchronous Communication Reduces Host Interrupt Overhead 6KV IEC 61000-4-2 ESD Compliance on Data Pin No Standby Power Required Available in a 3-Pin SOT-23 and TO-92 Packages The bq2026 SDQ™ interface requires only a single connection and a ground return. The SDQ pin is also the sole power source for the bq2026. The small surface-mount package options saves printed-circuit-board space, while the low cost makes it ideal for applications such as battery-pack configuration parameters, record maintenance, asset tracking, product-revision status, and access-code security. Device Information(1) 2 Applications • • • • PART NUMBER Security Encoding Inventory Tracking Product-Revision Maintenance Battery-Pack Identification bq2026 PACKAGE BODY SIZE (NOM) SOT-23 (3) 4.30 mm × 4.30 mm TO-92 (3) 2.92 mm × 1.30 mm (1) For all available packages, see the package option addendum at the end of the datasheet. Block Diagram DBZ Package (Top View) SDQ SDQ Communications Controller and CRC Generation Circuit Internal Bus ID ROM (64 bits) RAM Buffer (1 byte) EPROM Status (64 bits) 1 VSS 2 3 EPROM Memory (1536 bits) VSS SDQ VSS VSS LP Package (BottomView) 1 2 3 VSS SDQ VSS NOTE: Pin 3 for LP package can be ground or left unconnected. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 3 3 4 4 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Electrical Characteristics: DC ................................... Switching Characteristcs: AC.................................... 7 Detailed Description .............................................. 5 7.1 7.2 7.3 7.4 8 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 5 5 5 6 Device and Documentation Support.................. 15 8.1 Trademarks ............................................................. 15 8.2 Electrostatic Discharge Caution .............................. 15 8.3 Glossary .................................................................. 15 9 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History Changes from Original (April 2013) to Revision A Page • Changed document format to latest data sheet standards .................................................................................................... 1 • Added Handling Rating table, Feature Description, Device Functional Modes, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections ......................................................................................... 1 • Added note to front page diagram ......................................................................................................................................... 1 • Changed pin 3 (VSS) description for LP package.................................................................................................................. 3 2 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 5 Pin Configuration and Functions DBZ Package SOT-23-3 (Top View) SDQ 1 VSS 3 VSS 2 LP Package TO-92-3 (Top View) 1 2 3 VSS SDQ VSS Pin Functions PIN NAME I/O DESCRIPTION DBZ LP SDQ 1 2 I/O Data VSS 2, 3 1 — Ground VSS — 3 — Can be ground or left unconnected 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) DC voltage applied to VPU See Figure 1 MIN MAX –0.3 12.5 V 5 mA 6 kV 70 °C Low-level output current, IOL ESD IEC 61000-4-2 Air discharge SDQ to VSS, VSS to SDQ Operating free-air temperature range, TA (1) –20 UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 Handling Ratings MIN MAX UNIT Storage temperature range –55 125 °C Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Tstg Product Folder Links: bq2026 3 bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com 6.3 Electrical Characteristics: DC At TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS. PARAMETER ISDQ TEST CONDITION Supply current MIN TYP MAX UNIT VPU = 5.5 V 20 μA Logic 0, VPU = 5.5 V, IOL = 4 mA, SDQ pin 0.4 V Logic 0, VPU = 2.65 V, IOL = 2 mA 0.4 V 5.5 V VOL Low-level output voltage VOH High-level output voltage Logic 1 IOL Low-level output current (sink) VOL = 0.4 V, SDQ pin VIL Low-level input voltage Logic 0 VIH High-level input voltage Logic 1 VPP Programming voltage Ilkg Input leakage 1.4 µA CI Input capacitance 1.2 nF VPU 4 0.8 2.2 mA V V 11.5 12 V 6.4 Switching Characteristcs: AC TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS PARAMETER tc Bit cycle time (1) tWSTRB Write start cycle (1) tWDSU Write data setup tWDH Write data hold (1) (2) trec Recovery time (1) tRSTRB Read start cycle tODD Output data delay tODHO Output data hold tRST Reset time (1) tPPD Presence pulse delay tPP Presence pulse (1) tEPROG EPROM programming time tPSU tPREC tPRE Program rising-edge time tPFE Program falling-edge time TEST CONDITION (1) 4 MAX UNIT 60 TYP 120 μs 1 15 μs tWSTRB 15 μs 60 tc μs μs 1 (1) (1) (1) 1 13 μs tRSTRB 13 μs 17 60 μs μs 480 (1) 15 64 μs 60 240 μs 480 μs Program setup time 5 μs Program recovery time 5 tRSTREC (1) (2) MIN 480 μs 5 μs 5 μs μs 5-kΩ series resistor between SDQ pin and VPU. (See Figure 1) tWDH must be less than tc to account for recovery. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 7 Detailed Description 7.1 Overview The block diagram shows the relationships among the major control and memory sections of the bq2026. The bq2026 has three main data components: a 64-bit factory-programmed ROM, including 8-bit family code, 48-bit identification number and 8-bit CRC value, 1536-bit EPROM, and EPROM Status bytes. Power for read and write operations is derived from the SDQ pin. An internal capacitor stores energy while the signal line is high, and releases energy during the low times of the SDQ pin until the pin returns high to replenish the charge on the capacitor. 7.2 Functional Block Diagram SDQ SDQ Communications Controller and CRC Generation Circuit ID ROM (64 bits) Internal Bus EPROM Memory (1536 bits) VSS EPROM Status (64 bits) RAM Buffer (1 byte) VSS 7.3 Feature Description 7.3.1 EPROM Table 1 is a memory map of the 1536-bit EPROM section of the bq2026, configured as six pages of 32 bytes each. The 1-byte RAM buffer is an additional register used when programming the memory. Data are first written to the RAM buffer and then verified by reading a 16-bit CRC from the bq2026 that confirms proper receipt of the data. If the buffer contents are correct, a programming pulse is issued and a 1-byte segment of data is written into the selected address in memory. This process ensures data integrity when programming the memory. The details for reading and programming the 1536-bit EPROM portion of the bq2026 are in the Memory and Status Function Commands section of this data sheet. Table 1. 1536-Bit EPROM Data Memory Map ADDRESS (HEX) PAGE 00A0-00BF Page 5 0080-009F Page 4 0060-007F Page 3 0040-005F Page 2 0020-003F Page 1 0000-001F Page 0 7.3.2 EPROM Status Memory In addition to the programmable 1536-bits of memory are eight bytes of status information, the first seven bytes are available to the user, contained in the EPROM status memory. The status memory is accessible with separate commands. The status bytes are EPROM and are read or programmed to indicate various conditions to the software interrogating the bq2026. These general-purpose bytes can be used by the customer to store various information. Table 2. EPROM Status Bytes ADDRESS (HEX) 100h-107h PAGE General-purpose OTP status memory Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 5 bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com 7.3.3 Error Checking Implement error checking by comparing the 16-bit CRC values transmitted by the bq2026. If the two CRC values match, the transmission is error-free. Details are found in the CRC Generation section. 7.4 Device Functional Modes 7.4.1 Customizing the bq2026 The 64-bit ID identifies each bq2026 device. The 48-bit serial number is unique and programmed by Texas Instruments. The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis. Contact your Texas Instruments sales representative for more information. 7.4.2 Bus Termination Because the drive output of the bq2026 is an open-drain, N-channel MOSFET, the host must provide a source current or a 5-kΩ external pullup, as shown in the typical application circuit in Figure 1. VPU bq2026 SDQ SDQI 1 Communications Controller CPU SDQO VSS 3 VSS 2 HOST Figure 1. Bus Termination Example for SOT-23 Package 7.4.3 Serial Communication A host reads, programs, or checks the status of the bq2026 through the hierarchical command structure of the SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or status can be read or modified. Initialization ROM Command Sequence Memory and Status Command Sequence Figure 2. General Command Sequence 7.4.4 Initialization Initialization consists of two pulses, the reset and the presence pulses. The host generates the reset pulse, while the bq2026 responds with the presence pulse. The host resets the bq2026 by driving the DATA bus low for at least 480 μs. For more details, see the Reset and Presence Pulse section. 6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 7.4.5 ROM Commands 7.4.5.1 Read ROM The Read ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code and 48-bit identification number. The Read ROM sequence starts with the host generating the reset pulse of at least 480 μs. The bq2026 responds with a presence pulse. Next, the host continues by issuing the Read ROM command, 33h, and then reads the ROM and CRC byte using the read signaling (see the Write and Read sections) during the data frame. Reset and Presence Signals 1 1 Read ROM (33h) 0 0 1 1 Family Code and Identification Number (7 BYTES) 0 0 CRC (1 BYTE) Figure 3. Read ROM Sequence 7.4.5.2 Match ROM The Match ROM command, 55h, is used by the host to select a specific SDQ device when the family code and identification number is known. The host issues the Match ROM command followed by the family code, ROM number, and the CRC byte. The device that matches the 64-bit ROM sequence is selected and available to perform subsequent memory and status function commands. Reset and Presence Signals 1 0 Match ROM (55h) 1 0 1 0 1 Family Code and Identification Number (7 BYTES) 0 CRC (1 BYTE) Figure 4. Match ROM Sequence 7.4.5.3 Skip ROM This Skip ROM command, CCh, allows the host to access the memory and status functions without issuing the 64-bit ROM code sequence. The Skip ROM command is directly followed by a memory or status functions command. Reset and Presence Signals Skip ROM (CCh) 0 1 0 1 0 1 0 1 Figure 5. Skip ROM Sequence Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 7 bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com 7.4.6 Memory and Status Function Commands Four memory and status function commands allow read and modification of the 1536-bit EPROM data memory or the 7-byte EPROM status memory. There is a Read Memory and Field CRC command, plus the Write Memory, Read Status, and Write Status commands. The bq2026 responds to memory and status function commands only after a device is selected by a ROM command. 7.4.7 Read Memory and Field CRC To read the memory, the ROM command is followed by the Read Memory command, F0h, followed by the address low byte and then the address high byte. The host then issues read time slots and receives data from the bq2026, starting at the initial address and continuing until the end of the 1536-bit data field is reached, or until a reset pulse is issued. If reading occurs through the end of memory space, the host may issue sixteen additional read time slots and the bq2026 responds with a 16-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the host, any subsequent read time slots appears as logical 1s until a reset pulse is issued. Any reads ended by a reset pulse prior to reaching the end of memory do not have the 16-bit CRC available. Initialization and ROM Command Sequence Read Memory Command F0h Address Low Byte A0 (1) Address High Byte A7 A8 Read and Verify 16-bit CRC Read EPROM Memory Until End of EPROM Memory A15 Individual bytes of address and data are transmitted LSB first. Figure 6. Read Memory and Field CRC 7.4.8 Read Status The Read Status command is used to read data from the EPROM status data field. After issuing a ROM command, the host issues the Read Status command, AAh, followed by the address low byte and then the address high byte. NOTE An 16-bit CRC of the command byte and address bytes is computed by the bq2026 and read back by the host to confirm that the correct command word and starting address were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the host issues read time slots and receives data from the bq2026 starting at the supplied address and continuing until the end of the EPROM Status data field is reached. At that point, the host receives a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte through the final byte. This feature is provided because the EPROM status information may change over time making it impossible to program the data once and include an accompanying CRC that is always valid. Therefore, the Read Status command supplies a 16-bit CRC that is based on (and always is consistent with) the current data stored in the EPROM status data field. After the 16-bit CRC is read, the host receives logical 1s from the bq2026 until a reset pulse is issued. The Read Status command sequence can be ended at any point by issuing a reset pulse. Initialization and ROM CommandSequence Read Memory Command AAh Address Low Byte A0 8 Address High Byte A7 A8 Submit Documentation Feedback A15 Read Status Memory Until End of Page Read and Verify 16-bit CRC of command, address and data Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 Figure 7. READ STATUS Command Read Status Flow Write Status Flow Master TX: 16-bit address, A Master TX: 16-bit address, A Master RX: 8-bit data at A A = 0x0107? A=A+1 NO Master TX: 8-bit data, D Master RX: CRC of M/F cmd, A & D YES Master RX: CRC of preloaded A[15:0] & shifted D Master TX: Programming Pulse Master RX: CRC of all data transmitted Master RX: D ROM Function Flow A = 0x0107? Master TX: 8-bit data, D CRC = A[15:0] NO A=A+1 YES ROM Function Flow Figure 8. Status Memory Read and Write Flowchart Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 9 bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com 7.4.9 Write Memory The Write Memory command is used to program the 1536-bit EPROM memory field. The 1536-bit memory field is programmed in 1-byte segments. Data is first written into an 1-byte RAM buffer. The contents of the RAM buffer is then ANDed with the contents of the EPROM memory field when the programming command is issued. Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROM command, the host issues the Write Memory command, 0Fh, followed by the low byte and then the high byte of the starting address. The host then transmits 1 byte of data to the bq2026. a 16-bit CRC is calculated and transmitted based on the command, address and data. If this CRC agrees with the CRC calculated by the host, the host applies the programming voltage for at least 480 μs or tEPROG. If at any time during the Write Memory process, the CRC read by the host is incorrect, a reset pulse must be issued, and the entire sequence must be repeated. The Write Data Memory command sequence can be terminated at any point by issuing a reset pulse except during the program pulse period tPROG. NOTE The bq2026 responds with the data from the selected EPROM address sent least significant-bit first. This response should be checked to verify the programmed byte. If the programmed byte is incorrect, then the host must reset the part and begin the write sequence again. For both of these cases, the decision to continue programming is made entirely by the host, because the bq2026 is not able to determine if the 16-bit CRC calculated by the host agrees with the 16-bit CRC calculated by the bq2026. Prior to programming, bits in the 1536-bit EPROM data field appear as logical 1s. 10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 Read Memory Flow Write Memory Flow Master TX: 16-bit address, A Master TX: 16-bit address, A Master RX: 8-bit data at A A = 0x00BF? A=A +1 NO Master TX: 8-bit data, D Master RX: CRC of M/F cmd, A & D Master RX: CRC of preloaded A[15:0] & shifted D YES Master RX: CRC of all data transmitted Master TX: Programming Pulse CRC = A[15:0] Master RX: D ROM Function Flow Master TX: 8-bit data, D A = 0x00BF? A=A+1 NO YES ROM Function Flow Figure 9. General Use OTP Memory Read and Write Flowchart 7.4.10 Write Status The Write Status command is used to program the EPROM Status data field after the bq2026 has been selected by a ROM command The flow chart in Figure 9 illustrates that the host issues the Write Status command, 55h, followed by the address low byte and then the address high byte followed by the byte of data to be programmed. NOTE Individual bytes of address and data are transmitted LSB first. a 16-bit CRC of the command byte, address bytes, and data byte is computed by the bq2026 and read back by the host to confirm that the correct command word, starting address, and data byte were received. If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the host is correct, the programming voltage, VPP is applied to the SDQ pin for period tPROG. Prior to programming, the first 7 bytes of the EPROM STATUS data field appear as logical 1s. For each bit in the data byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the EPROM STATUS data field is programmed to a logical 0 after the programming pulse has been applied at the byte location. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 11 bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com After the programming pulse is applied and the data line returns to VPU, the host issues eight read time slots to verify that the appropriate bits have been programmed. The bq2026 responds with the data from the selected EPROM STATUS address sent least significant bit first. This response should be checked to verify the programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write sequence again. If the bq2026 EPROM data byte programming was successful, the bq2026 automatically increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant byte of the new two-byte address is also loaded into the 16-bit CRC generator as a starting value. The host issues the next byte of data using eight write time slots. As the bq2026 receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the host reads this 16-bit CRC from the bq2026 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory is programmed. NOTE The initial write of the Write Status command, generates a 16-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two-address bytes, and finally the data byte. Subsequent writes within this Write Status command due to the bq2026 automatically incrementing its address counter generates a 16-bit CRC that is the result of loading (not shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by the host, because the bq2026 is not able to determine if the 16-bit CRC calculated by the host agrees with the 16-bit CRC calculated by the bq2026. If an incorrect CRC is ignored and a program pulse is applied by the host, incorrect programming could occur within the bq2026. Also note that the bq2026 always increments its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Status command, incorrect programming could occur within the bq2026. The Write Status command sequence can be ended at any point by issuing a reset pulse. Table 3. Command Code Summary COMMAND (HEX) DESCRIPTION 33h Read serialization ROM and CRC 55h Match serialization ROM CCh Skip serialization ROM F0h Read memory and field CRC AAh Read EPROM status 0Fh Write memory 55h Write EPROM status CATEGORY ROM Commands Available in Command Level I Memory Function Commands Available in Command Level II 7.4.11 SDQ Signaling All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or to begin the start frame for a bit read. Figure 10 shows the initialization timing, whereas Figure 11 and Figure 12 show that the host initiates each bit by driving the data bus low for the start period, tWSTRB / tRSTRB. After the bit is initiated, either the host continues controlling the bus during a write, or the bq2026 responds during a read. 12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 7.4.12 Reset and Presence Pulse If the data bus is driven low for more than 120 μs, the bq2026 may be reset. Figure 10 shows that if the data bus is driven low for more than 480 μs, the bq2026 resets and indicates that it is ready by responding with a presence pulse. RESET (Sent by Host) VPU VIH VIL Presence Pulse (Sent by bq2026) t PPD t RST t PP t RSTREC Figure 10. Reset Timing Diagram 7.4.13 Write The Write bit timing diagram in Figure 11 shows that the host initiates the transmission by issuing the tWSTRB portion of the bit and then either driving the data bus low for a write 0, or releasing the data bus for a write 1. V PU Write ”1” V IH V IL Write ”0” t rec t WSTRB t WDSU t WDH Figure 11. Write Bit Timing Diagram 7.4.14 Read The Read bit timing diagram in Figure 12 shows that the host initiates the transmission of the bit by issuing the tRSTRB portion of the bit. The bq2026 then responds by either driving the data bus low to transmit a read 0, or releasing the data bus to transmit a read 1. VPU Read ”1” V IH V IL Read ”0” t RSTRB t REC t ODD t ODHO Figure 12. Read Bit Timing Diagram 7.4.15 Program Pulse Figure 13 shows the program pulse timing. VPP VPU tPSU tPFE tPRE tPREC tEPROG VSS Figure 13. Program Pulse Timing Diagram Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 13 bq2026 SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 www.ti.com 7.4.16 Idle If the bus is high, the bus is in the idle state. Bus transactions can be suspended by leaving the data bus in idle. Bus transactions can resume at any time from the idle state. 7.4.17 CRC Generation The bq2026 has a 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master computes a CRC value from the first 56 bits of the 64-bit ROM and compares it to the value stored within the bq2026 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is shown in Figure 14. Under certain conditions, the bq2026 also generates a 16-bit CRC value using the polynomial function is shown in Figure 15 and provides this value to the bus master which validates the transfer of command, address, and data bytes from the bus master to the bq2026. The bq2026 computes a 16-bit CRC for the command, address, and data bytes received for the Write Memory and the Write Status commands, and then outputs this value to the bus master which confirms proper transfer. Similarly, the bq2026 computes a 16-bit CRC for the command and address bytes received from the bus master for the Read Memory, and Read Status commands to confirm that these bytes have been received correctly. In each case, where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function in Figure 14 or Figure 15 and compares the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the bq2026 (for ROM reads) or the 16-bit CRC value computed within the bq2026. The comparison of CRC values and the decision to continue with an operation are determined entirely by the bus master. No circuitry on the bq2026 prevents a command sequence from proceeding if the CRC stored in or calculated by the bq2026 does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity. CLK DAT Q D Q D R Q D R R + Q D R + Q D Q D R R Q D R + Q D R Figure 14. 8-bit CRC Generator Circuit (X8 + X5 + X4 + 1) for Serial Number Read SPACER CLK DAT Q D Q D R Q D R Q D R Q D Q D R R Q D R Q D R Q D R Q D R Q D Q D R R Q D R Q D R R Q D Q D R R Figure 15. 16-bit CRC Generator Circuit (X16 + X15 + X2 + 1) for Memory Interface 14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 bq2026 www.ti.com SLUS938A – DECEMBER 2011 – REVISED OCTOBER 2014 8 Device and Documentation Support 8.1 Trademarks SDQ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 8.2 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: bq2026 15 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ2026DBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 70 WAIS BQ2026LPR ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type -20 to 70 BQ2026 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of