BQ2052SN-A515

Preliminary bq2052 Gas Gauge IC for Lithium Primary Cells Features General Description ➤ Accurate measurement of available capacity in Lithium primary batteries such as Lithium Sulphur Dioxide and Lithium Manganese Dioxide The bq2052 Lithium Primary Gas G a u g e I C is in t en d ed f or b a ttery-pack or in-system installation to maintain an accurate record of available battery capacity. The IC monitors a voltage drop across a sense resistor connected in series with the cells to determine discharge activity of the battery. The bq2052 applies compensations for battery temperature and discharge rate to the available charge counter to provide available capacity information across a wide range of operating conditions. ➤ Provides a low-cost battery monitor solution for pack integration - Complete circuit can fit less than 1 square inch of PCB space - Low operating current Less than 100nA of data retention current ➤ Single-wire communication interface (HDQ bus) for critical battery parameters ➤ Communicates remaining capacity with direct drive of LEDs in 3 selectable modes ➤ Measurements automatically compensated for discharge rate and temperature communications link to an external micro-controller. The link allows the micro-controller to read and write the internal registers of the bq2052. The internal registers include available battery capacity, voltage, temperature, current, and battery status. The controller may also overwrite some of the bq2052 gas gauge data registers. The bq2052 can operate from the batteries in the pack. The REF output and an external FET provide a simple, inexpensive voltage regulator to supply power to the circuit from the cells. Compensated available capacity may be directly indicated using an LED display. The LED display is programmable and can be configured as two, four, or five segments. These segments are used to depict available battery capacity. The bq2052 supports a single-wire serial ➤ 16-pin narrow SOIC Pin Connections Pin Names LCOM LCOM 1 16 VCC SEG1/PROG1 2 15 REF SEG2/PROG2 3 14 CP SEG3/PROG3 4 13 HDQ SEG4/PROG4 5 12 RBI SEG5/PROG5 6 11 SB PROG6 7 10 DISP VSS 8 9 SR 16-Pin Narrow SOIC PN2052H1.eps LED common output SEG1/PROG1 LED segment 1/ program 1 input SEG1/PROG2 LED segment 2/ program 2 input SEG1/PROG3 LED segment 3/ program 3 input SEG1/PROG4 LED segment 4/ program 4 input SEG1/PROG5 LED segment 5/ program 5 input CP Control port SLUS019–MAY 1999 1 VSS System ground SR Sense resistor input DISP Display control input SB Battery sense input RBI Register backup input HDQ Serial communications input/output PROG6 Program 6 input REF Voltage reference output VCC Supply voltage bq2052 Preliminary SR Pin Descriptions LCOM The voltage drop (VSR) across the sense resistor RS is monitored and integrated over time to interpret discharge activity. VSR > VSS indicates discharge. The effective voltage drop, VSRO, as seen by the bq2052 is VSR + VOS . LED common output This open-drain output switches V CC to source current for the LEDs. The switch is off during initialization to allow reading of the soft pull-up or pull-down program resistors. LCOM is also high impedance when the display is off. SEG1– SEG5 DISP LED display segment outputs (dual function with PROG1–PROG5) SB Programmed full count selections Power gauge scale selection inputs (dual function with SEG3–SEG4) RBI This three-level input pin defines the scale factor. PROG4 Programmed compensation factors HDQ CP Control port This open drain output may be controlled by serial port commands and its state is reflected in the CPIN bit in FLGS1. Programmed initial capacity state This input defines the initial battery capacity indication state. When tied to VCC, the bq2052 sets the available capacity to full on reset. When tied to VSS, the bq2052 sets the available capacity to zero on reset. VSS Serial communication input/output This is the open-drain bidirectional communications port. Programmed display mode This three-level input pin defines the capacity indication display mode. PROG6 Register backup input This pin is used to provide backup potential to the bq2052 registers during periods when VCC ≤ 3V. A storage capacitor or a battery can be connected to RBI. This three-level input pin defines the battery discharge compensation factors. PROG5 Secondary battery input This input monitors the battery cell voltage potential through a high-impedance resistive divider network for the end-of-discharge voltage (EDV) thresholds. These three-level input pins define the programmed full count. PROG3 Display control input DISP high disables the LED display. DISP tied to VCC (no display LEDs in the circuit) allows PROGX to connect directly to VCC or V S S in s t ea d of t h r ou g h a p u ll- u p o r pull-down resistor. DISP low activates the display. Each output may activate an LED to sink the current sourced from LCOM. PROG1– PROG2 Sense resistor input REF Voltage reference output for regulator REF provides a voltage reference output for an optional micro-regulator. Ground VCC 2 Supply voltage input Preliminary bq2052 Functional Description Measurements General Operation The bq2052 uses a voltage-to-frequency converter (VFC) for discharge measurement and an analog-to-digital converter (ADC) for battery voltage measurement. The bq2052 determines battery capacity by monitoring the amount of charge removed from a primary battery. The bq2052 measures discharge currents and battery voltage, monitors the battery for the low battery-voltage thresholds, and compensates available capacity for temperature and discharge rate. The bq2052 measures capacity by monitoring the voltage across a small-value series sense resistor between the negative battery terminal and ground. Discharge Counting The VFC measures the discharge flow of the battery by monitoring a small value sense resistor between the SR pin and VSS as shown in Figure 1. The bq2052 detects “discharge” activity when the potential at the SR input, VSRO, is positive. The bq2052 integrates the signal over time using an internal counter. The fundamental rate of the counter is 3.125µVh. The VFC measures signals up to 0.5V in magnitude. Figure 1 shows a typical battery pack application of the b q 2 0 5 2 u s i ng t he L E D d i s p l ay c ap a b ilit y a s a charge-state indicator. The bq2052 displays capacity with two, four, or five LEDs using the programmed full count (PFC) as the battery’s “full” reference. The bq2052 has a push-button input for momentarily enabling the LED display. Digital Magnitude Filter The bq2052 has a digital filter to eliminate discharge counting below a set threshold. The minimum discharge threshold, VSRD, for the bq2052 is 250µV. R1 bq2052 Gas Gauge IC Q1 ZVNL110A REF C1 LCOM SEG1 RB1 VCC SB SEG2 H or L To µC RB2 SEG3 DISP SEG4 VSS SEG5 SR 100K PROG6 CP RS 0.1µF RBI HDQ Notes: 1. Load Indicates optional. 2. VCC can connect directly to two lithium primary cells (6.0V nominal and should not exceed 6.5V). Otherwise, R1, C1, and Q1 are needed for regulation of > 2 cells. 3. Programming resistors and ESD-protection diodes are not shown. 4. R-C on SR is required. 5. A series diode is required on RBI if the bottom series cell is used as the backup source. If the cell is used, the backup capacitor is not required, and the anode is connected to the positive terminal of the cell. FG205201.eps Figure 1. Application Diagram—5-Segment LED Display 3 bq2052 Preliminary Table 1. bq2052 Current-Sensing Errors Symbol Parameter Typical INL Integrated non-linearity error ±2 INR Integrated nonrepeatability error ±1 Maximum Units Notes ±4 % Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. ±2 % Measurement repeatability given similar operating conditions. Voltage Monitoring and Thresholds Temperature In conjunction with monitoring the SR input for discharge currents, the bq2052 monitors the battery potential through the SB pin. The voltage at the SB pin, VSB, is developed through a high impedance resistor network connect across the battery. The bq2052 monitors the voltage at the SB pin and reports the voltage in the VSB register (address = 0bh). The bq2052 has an internal temperature sensor to measure temperature. The bq2052 determines the temperature and stores it in the TEMP register (address = 02h). The bq2052 uses temperature to adapt remaining capacity for the battery’s discharge efficiency. Gas Gauge Operation T h e b q 2 0 5 2 c o m p ar e s t he V S B r e ad in g t o t w o end-of-discharge voltage (EDV) thresholds. The EDV threshold levels are used to determine when the battery has reached an “empty” state. The EDV thresholds for the bq2052 are programmable with the default values fixed at: General The operational overview diagram in Figure 2 illustrates the operation of the bq2052. The bq2052 accumulates a measure of discharge currents and calculates available capacity. The bq2052 compensates available capacity for discharge rate and temperature and provides the information in the Compensated Available Capacity (CAC) registers (address = 0eh–0fh). The main counter, Discharge Count Register (DCR) (address = 2eh), represents the cumulative amount of charge removed from the battery. Battery discharging increments the DCR register. EDV1 (first) = 0.76V EDVF (final) = EDV1 - 0.10V = 0.66V If VSB is below either of the two EDV thresholds for 8 consecutive samples over a 4 second period, the bq2052 sets the associated flag in the FLGS1 register (address = 01h). Once set, the EDV flags remain set, independent of VSB. Inputs Discharge Current Rate and Temperature Efficiency Factor + Main Counters Discharge Count Register (DCR) – Full Nominal Available Charge (FNAC) + Compensated Available Capacity (CAC) Complete Data Set Chip-Controlled Available Charge LED Display Outputs Serial Port FG2052.eps Figure 2. Operational Overview 4 Preliminary bq2052 Table 2. bq2052 Programmed Full Count mVh PROGx 1 2 Programmed Full Count (PFC) - - H PROG3 H Z L Units - SCALE = 1/40 SCALE = 1/80 SCALE = 1/160 mVh/ count H 48128 1203 602 301 mVh H Z 46080 1152 576 288 mVh H L 43264 1082 541 271 mVh Z H 39936 998 499 250 mVh Z Z 38400 960 480 240 mVh Z L 36096 902 451 226 mVh L H 31744 794 397 199 mVh L Z 28928 723 362 181 mVh L L 26112 653 327 164 mVh The bq2052 applies the compensation according to the formula: Main Gas-Gauge Registers Programmed Full Count CAC = [FCE ∗ FNAC] - DCR The PFC register stores the user-specified battery full capacity. The 8-bit PFC registers stores the full capacity in mVh scaled as shown in Table 2. Where FCE is the calculated efficiency compensation factor, FNAC = Full Nominal Available Capacity and DCR = Discharge Count Register. Full Nominal Available Capacity The bq2052 calculates an FCE based on the battery discharge rate and temperature. The discharge rate portion of the FCE compensation is a “peak hold” function; therefore, the bq2052 latches the highest discharge rate it has measured and uses the highest rate to calculate FCE throughout the complete discharge cycle. The highest discharge rate measured by the bq2052 is stored in MRATE (address = 12h). The FNAC register stores the full capacity reference of the battery. It can be programmed to initialize to PFC or zero. The 8-bit FNAC register stores data scaled to the same units as PFC. The bq2052 does not update FNAC during the course of operation; therefore, if it is programmed to 0 on initialization, it must be written to full using the serial port. The bq2052 does not latch the temperature portion of an FCE calculation. Therefore, CAC may increase or decrease during the course of a complete discharge cycle if a temperature shift causes a change in the calculated FCE value. Discharge Count Register The DCR is the main gas gauging register and contains the cumulative amount of discharge counted by the bq2052. The 16-bit register stores data scaled to the same units as PFC. Compensated Available Capacity Programming the bq2052 The CAC registers contain the current available capacity of the battery. The data stored in CAC represents the amount of remaining capacity of the battery compensated for rate and temperature use conditions. Tables 3, 4, and, 5 outline the options for typical efficiency compensation factors for lithium primary batteries. The bq2052 applies the efficiency factors to FNAC to derive CAC. The bq2052 is programmed with the PROG1–6 pins. During power-up or initialization, the bq2052 reads the state of these six three-level inputs and latches in the programmable configuration settings. 7 5 bq2052 Preliminary Programmable Configuration Settings Table 5. Discharge Efficiency Factor Table PROG4 = H Design Capacity The battery’s rated design capacity or Programmed Full Count (PFC) is programmed with the PROG1–PROG3 pins as shown in Table 2, and represents the battery’s full reference. TEMP -20 -10 0 21 55 70 The correct PFC may be determined by multiplying the rated battery capacity in mAh by the sense resistor value: Battery capacity (mAh) * sense resistor (Ω) = PFC (mVh) Selecting a PFC slightly less than the rated capacity provides a conservative capacity reference. The bq2052 stores the selected PFC in the PFC register (address = 10h). 0 92 98 100 104 106 107 C/80 93 98 100 104 106 107 Discharge Rage C/25 C/10 92 88 97 93 99 96 102 99 105 100 105 101 The display mode is selected using the PROG5 pin. The three options include a two, four, or five segment display mode as described in Tables 7, 8, and 9. The discharge rate and temperature compensations are selected using the PROG4 pin. The level of PROG4 on power-up or initialization determines which compensation table the bq2052 uses for the discharge cycle. The following tables illustrate the calculated efficiency compensation factors at selected discharge rates and temperatures. Initial Capacity Setting Table 3. Discharge Efficiency Factor Table PROG4 = Z Programming Example TEMP -20 -10 0 21 55 70 0 97 98 98 99 99 99 C/5 85 89 90 92 93 93 C/3 75 81 84 88 90 91 Display Mode Discharge Rate and Temperature Compensation Discharge Rage C/80 C/25 C/10 99 96 92 98 97 94 98 97 94 99 98 96 99 98 96 99 98 96 C/5 83 89 91 95 97 98 The PFC value is copied to the FNAC register if PROG6 is programmed high, otherwise FNAC defaults to 0. FNAC may be written to the desired full capacity to initialize the pack manually. Given: Sense resistor = 0.05mΩ Number of cells = 5 in series Capacity = 7000mAh, Chemistry = LiSO2 Discharge current range = 250mA to 2A Voltage drop over sense resistor = 12.5mV to 100mV Display mode = 5 segment bar graph display C/3 81 85 87 89 90 90 Therefore: 7000mAh * 0.05 = 350mVh Select: Table 4. Discharge Efficiency Factor Table PROG4 = L TEMP -20 -10 0 21 55 70 0 87 93 96 99 100 101 C/80 85 91 94 97 99 100 Discharge Rage C/25 C/10 80 70 88 80 91 85 95 89 97 92 98 93 C/5 53 68 74 81 85 86 PFC = 26112 counts or 327mVh PROG1 = low PROG2 = low PROG3 = float PROG4 = float, high, or low depending on desired compensation factors PROG5 = float selects five segment display PROG6 = high sets FNAC to PFC C/3 50 51 60 68 74 76 With these selections, the full battery capacity is 327mVh (6540mAh). 6 Preliminary bq2052 Table 6. bq2052 Command and Status Registers Symbol Register Name Loc. Read/ (hex) Write Control Field 7 6 5 4 3 2 1 0 CMDWD Command word 00h W CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 FLGS1 Primary status flags 01h R INIT RSVD RSVD CPIN RSVD EDVF TEMP Temperature (°C) 02h R NAC Nominal available capacity 03h R/W R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0 RSVD EDV1 TEMP7 TEMP6 TEMP5 TEMP4 TEMP3 TEMP2 TEMP1 TEMP0 NAC7 NAC6 NAC5 NAC4 NAC3 NAC2 NAC1 NAC0 BATID Battery identification 04h VSRL Current scale (Low) 05h R VSRL7 VSRH Current scale (High) 06h R VSRH7 VSRH6 VSRH5 VSRH4 VSRH3 VSRH2 VSRH1 VSRH0 PPD Program pin pulldown 07h R RSVD RSVD PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 PPU Program pin pull-up 08h R RSVD RSVD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 VSB Battery voltage register 0bh R VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 VTS End-of-discharge threshold select register 0ch R/W VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0 RCAC Relative compensated capacity 0dh R RSVD CACL Compensated avail0eh able capacity low byte R CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0 CACH Compensated available 0fh capacity high byte R CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0 PFC Program pin full count 10h R FNAC Full nominal available capacity 11h R/W MAX RATE Maximum discharge rate 12h R MAX7 RATE Discharge rate 13h R RATE7 RATE6 RATE5 RATE4 RATE3 RATE2 RATE1 RATE0 DCRL Discharge count register (low byte) 2eh R/W DCRL7 DCRL6 DCRL5 DCRL4 DCRL3 DCRL2 DCRL1 DCRL0 DCRH Discharge count register (high byte) 2fh R/W DCRH7 DCRH6 DCRH5 DCRH4 DCRH3 DCRH2 DCRH1 DCRH0 Notes: PFC7 VSRL6 VSRL5 VSRL4 VSRL3 VSRL2 VSRL1 VSRL0 RCAC6 RCAC5 RCAC4 RCAC3 RCAC2 RCAC1 RCAC0 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 FNAC7 FNAC6 FNAC5 FNAC4 FNAC3 FNAC2 FNAC1 FNAC0 MAX6 RSVD = reserved. All other registers not documented are reserved. 7 MAX5 MAX4 MAX3 MAX2 MAX1 MAX0 bq2052 Preliminary Send Host to bq-HDQ Send Host to bq-HDQ or Receive from bq-HDQ Data CDMR R/W MSB Bit7 Address LSB Bit0 Break tRR tRSPS Start-bit Address-Bit/ Data-Bit Stop-Bit TD201807.eps Figure 4. bq2052 Communication Example Written by Host to bq2052 CMDR = 03h LSB Received by Host to bq2052 NAC = 65h MSB Break 1 1 0 0 0 0 0 0 LSB MSB 1 01 0 011 0 HDQ tRSPS TD2052TC.eps Figure 5. Typical Communication with the bq2052 8 Preliminary bq2052 Communicating With the bq2052 bq2052 Command Code and Registers The bq2052 includes a simple single-pin (HDQ plus return) serial data interface. A host processor uses the interface to access various bq2052 registers. Battery characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain HDQ pin on the bq2052 should be pulled up by the host system, or may be left floating if the serial interface is not used. The bq2052 status registers are listed in Table 6 and described below. Command Code The bq2052 latches the command code when eight valid command bits have been received by the bq2052. The command code contains two fields: The interface uses a command-based protocol, where the host processor sends a command byte to the bq2052. The command directs the bq2052 to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte. ■ W/R bit ■ Command address The W/R bit of the command code is used to select whether the received command is for a read or a write function. The communication protocol is asynchronous return-to-one. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2052 may be sampled using the pu l se -wi d th c a p t ur e t i m e r s av ai l abl e on s om e microcontrollers. The W/R values are: Command Code Bits 7 6 5 4 3 2 1 0 W/R - - - - - - - Where W/R is: If a communication error occurs, e.g., tCYCB > 250µs, the bq2052 should be sent a BREAK to reinitiate the serial interface. A BREAK is detected when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2052 is now ready to receive a command from the host processor. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2052 taking the HDQ pin to a logic-low state for a period, tSTRH;B. The next section is the actual data transmission, where the data should be valid by a period, tDSU;B, after the negative edge used to start communication. The data should be held for a period, tDH;DV, to allow the host or bq2052 to sample the data bit. 0 The bq2052 outputs the requested register contents specified by the address portion of command code. 1 The following eight bits should be written to the register specified by the address portion of command code. The lower seven-bit field of the command code contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored. 7 - The final section is used to stop the transmission by returning the HDQ pin to a logic-high state by at least a period, tSSU;B, after the negative edge used to start communication. The final logic-high state should be until a period tCYCH;B, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial communication timing specification and illustration sections. 6 5 Command Code Bits 4 3 2 AD6 AD5 AD4 AD3 AD2 1 AD1 0 AD0 (LSB) Command Word (CMDWD) The CMDWD register (address = 00h) is used by the external host to control the CP pin and to reset the bq2052. CMDWD Action 0x55 CP high impedence, CPIN bit in FLGS1 set 0x66 CP driven low, CPIN bit in FLGS1 cleared 0x78 bq2052 reset Communication with the bq2052 is always performed with the least-significant bit being transmitted first. Figure 5 shows an example of a communication sequence to read the bq2052 NAC register. 9 bq2052 Preliminary Primary Status Flags Register (FLGS1) 1 The FLGS1 register (address = 01h) contains the primary bq2052 flags. VSB < VTS The initialized flag (INIT) is asserted to a 1 or 0 whenever the bq2052 is initialized either by the application of Vcc or by a serial port command. INIT = 1 signifies that the device has been reset with FNAC set to PFC. INIT = 0 signifies that the battery has been reset with FNAC = 0. The bq2052 sets the final end-of-discharge warning flag (EDVF) when VSB is less than the EDVF threshold. The EDVF threshold is set 100mV below the EDV1 threshold. The EDVF flag is used to warn the system or user that battery power is at a failure condition. The bq2052 turns all segment drivers off upon EDVF detection. The INIT location is: The EDVF location is: FLGS1 Bits FLGS1 Bits 7 INIT 6 - 5 4 - - 3 - 2 1 - - 0 7 6 5 4 3 2 1 0 - - - - - - - - EDVF Where EDVF is: where INIT is: 0 The bq2052 initialized with FNAC = 0. 0 VSB ≥ (VTS - 100mV) 1 The bq2052 initialized with FNAC = PFC. 1 VSB < (VTS -100mV) Temperature Register (TEMP) The CPIN but reflects the state of the CP output. If set, the CP output is high impedance. If cleared, the CP output is asserted low. The CP output is an open drain output and requires an external pull-up register. The 8-bit TEMP register (address=02h) contains the battery temperature in degrees C. The bq2052 contains an internal temperature sensor. The temperature is used to set discharge efficiency factors. The temperature register contents are store in 2’s complement form and represent the temperature ± 5°C. The CPIN location is 7 - 6 - 5 - FLGS1 Bits 4 3 CPIN - 2 - 1 - 0 - Nominal Available Capacity Register (NAC) The NAC register contains the uncompensated remaining capacity of the battery. The bq2052 determines NAC as Where CPIN is: NAC = FNAC - DCR 0 CP is low 1 CP is high impedance Battery Identification Register (BATID) The bq2052 sets the first end-of-discharge warning flag (EDV1) when the battery voltage VSB is less than the EDV1 threshold VTS. The flag warns the user that the battery is almost empty. The bq2052 modulates the first segment pin, SEG1, at a 4Hz rate if the 4 or 5 segment display mode is enabled and EDV1 is asserted. The 8-bit BATID register (address=04h) is a general purpose memory register that can be used to uniquely identify a battery pack. The bq2052 maintains the BATID contents as long as VRBI is greater than 2V. The contents of this register have no effect on the operation of the bq2052. The EDV1 threshold has a default value of 0.76V but can be adjusted by writing the VTS register . Current Scale Registers (VSRL/VSRH) The VSRH high-byte register and the VSRL low-byte register are used to calculate the average signal across the SR and VSS pins. This register pair is updated every 5.625 seconds. VSRH and VSRL form a 16-bit value representing the average current over this time. The battery pack current can be calculated by: The EDV1 location is FLGS1 Bits 7 6 5 4 3 2 1 0 - - - - - - EDV1 - |I(mA)| = Where EDV1 is: 0 VSB ≥ VTS 10 (VSRH ∗ 256 + VSRL) (RS) Preliminary bq2052 where temperature. The CAC value is also used in calculating the LED display pattern relative to PFC. RS = sense resistor value in Ω. VSRH = high-byte value of current scale Program Full Count (PFC) VSRL = low-byte value of current scale The PFC register (address = 10h) contains the user selected programmed full count (PFC) setting. Program Pin Pull-Down Register (PPD) Full Nominal Available Capacity (FNAC) The PPD register (address = 07h) contains the pull-down programming pin information for the bq2052. The program pins, PROG1–6, have a corresponding PPD register location, PPD1–6. A given location is set if the bq2052 detects a pull-down resistor on its corresponding segment driver. For example, if PROG1 and PROG4 have pull-down resistors, the contents of PPD are xx001001. The FNAC (address = 11h) contains the full capacity reference of the battery. Maximum Discharge Rate (MAXRATE) The MAXRATE register (address = 12h) stores the highest discharge rate detected by the bq2052. The bq2052 uses the MAXRATE value to calculate the efficiency compensation factors. Program Pin Pull-Up Register (PPU) The PPU register (address = 08h) contains the pull-up programming pin information for the bq2052. The segment drivers, PROG1–6, have a corresponding PPU register location, PPU 1–6. A given location is set if a pull-up resistor has been detected on its corresponding segment driver. For example, if PROG3 and PROG5 have pull-up resistors, the contents of PPU are xx010100. Discharge Rate (RATE) The RATE register (address = 13h) provides the current discharge rate of the battery. Discharge Count Registers (DCRH/DCRL) The DCRH high-byte register and the DCRL low-byte register are the main gas gauging registers for the bq2052. The DCR registers are incremented during discharge. Battery Voltage (VSB) The battery voltage register (address = 0bh) stored the voltage detected on the SB pin. The bq2052 updates the VSB register approximately once per second with the present value of the battery voltage. Writing to the DCR registers affects the available charge counts and, therefore, affects the bq2052 gas gauge operation. VSB  VSB = 1.2V ∗    256  Display The bq2052 can directly display remaining capacity information using low-power LEDs. The bq2052 uses the CAC value in relation to FNAC as the basis for the display activity. The bq2052 displays the battery’s remaining capacity in either of three modes selected with program pin PROG5. The display is activated using the DISP input. When DISP is connected to VCC, the SEG outputs are OFF. When pulled low, the segment outputs turn ON for a period of 4 ± 0.5s, depending on the selected mode. Voltage Threshold Register (VTS) The end-of-discharge threshold voltages (EDV1 and EDVF) can be set using the VTS register. The VTS register sets the EDV1 trip point. EDVF is set 100mV below EDV1. The default value in the VTS register is A2h, representing EDV1 = 0.76V and EDVF = 0.66V. EDV1 = 1.2V *  VTS  .  256  The segment outputs are modulated as two banks, with segments 1, 3, and 5 alternating with segments 2 and 4. The segment outputs are modulated at approximately 100Hz with each segment bank active for 30% of the period. In incremental and bar graph modes, SEG1 blinks at a 4Hz rate whenever VSB is below VEDV1 (EDV1 flag bit set in FLGS1), indicating a low-battery condition. When VSB is below VEDVF (EDVF flag bit set in FLGS1) the display outputs are disabled in all modes. Relative CAC Register (RCAC) The RCAC register (address = 0dh) provides the relative battery state-of-charge by dividing CAC by FNAC. RCAC varies from 0 to 7dh representing relative state-of-charge from 0 to 125%. Compensated Available Capacity (CAC) The CAC registers (address = 0eh–0fh) contain the available capacity compensated for discharge rate and 11 bq2052 Preliminary In incremental mode (PROG5 = L), the battery charge state is displayed on pins SEG1–SEG4. The charge state condition indicated by each segment is shown in Table 7. Only the segment pin representing the present remaining capacity is ON (low); all other segments are OFF (high impedance). When DISP is pulled low, the display is active for 10s. Microregulator A micro-power source for the bq2052 can be inexpensively built using a FET and an external resistor as shown in Figure 1. RBI Input Table 7. Incremental Display Mode PROG5 = L SEG Pin ON SEG4 SEG3 SEG2 SEG1 SEG1—BLINK The RBI input pin should be used with a storage capacitor or external supply to provide backup potential to the internal bq2052 registers when VCC drops below 3.0V. VCC is output on RBI when VCC is above 3.0V. If using an external supply (such as the bottom series cell) as the backup source, an external diode is required for isolation. Remaining Capacity 90 -100% 50 - < 90% 20 - < 50% < 20% VSB < VEDV1 Initialization The bq2052 can be initialized by removing VCC and grounding the RBI pin for 5s or by a command over the serial port. The serial port reset command requires writing 78h to register CMDWD (address = 00h). In binary mode (PROG5 = H), the battery charge state is displayed using only pins SEG1 and SEG2, with the remaining capacity indication defined as in Table 8. When DISP is pulled low, the display is active for 4s. On initialization with PROG6 = H, the bq2052 sets the registers as Table 8. Binary Display Mode PROG5 = H SEG 1 ON ON OFF OFF SEG 2 ON OFF ON OFF FNAC = PFC CACH = PFC CACL = 0x00 RCAC = 0x64 FLGS1 = 0x90 Remaining Capacity 70 -100% 40 - < 70% 10 - < 40% < 10% or VSB < VEDVF In bar graph mode (PROG5 = Z), the battery charge state is displayed using pins SEG1 through SEG 5 according to Table 9. When DISP is pulled low, the display is active for 4s. Table 9. Bar Graph Display Mode PROG5 = Z SEG1 ON ON ON ON ON BLINK SEG2 ON ON ON ON OFF OFF SEG3 ON ON ON OFF OFF OFF SEG4 ON ON OFF OFF OFF OFF 12 SEG5 ON OFF OFF OFF OFF OFF Remaining Capacity 80 - 100% 60 - < 80% 40 - < 60% 20 - < 40% < 20% VSB < VEDV1 Preliminary bq2052 Layout Considerations On initialization with PROG6=L, the bq2052 sets the registers as The bq2052 measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. FNAC = 0x00 CACH = 0x00 CACL = 0x00 RCAC = 0x00 FLGS1 = 0x10 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Notes VCC Relative to VSS -0.3 +7.0 V All other pins Relative to VSS -0.3 +7.0 V REF Relative to VSS -0.3 +8.5 V Current limited by R1 (see Figure 1) VSR Relative to VSS -0.3 Vcc+0.7 V Recommended 100KΩ series resistor should be used to protect SR in case of a shorted battery. TOPR Operating temperature -20 +70 °C Commercial Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V) Symbol Parameter Minimum Typical Maximum Unit Notes VEDV1 First empty warning 0.73 0.76 0.79 V SB, default VEDVF Final empty warning - VEDV1 - 0.10 - V SB, default VSRO SR sense range -300 - +500 mV SR, VSR + VOS VSRD Valid discharge - - -250 µV VSR + VOS (see note) Note: VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance. See “Layout Considerations.” 13 bq2052 Preliminary DC Electrical Characteristics (TA = TOPR) Symbol Parameter VCC Supply voltage VOS Offset referred to VSR VREF RREF ICC Minimum Typical Maximum Unit Notes 3.0 4.25 6.5 V VCC excursion from < 2.0V to ≥ 3.0V initializes the unit. - ±50 ±150 µV DISP = VCC Reference at 25°C 5.7 6.0 6.3 V IREF = 5µA Reference at -40°C to +85°C 4.5 - 7.5 V IREF = 5µA Reference input impedance 2.0 5.0 - MΩ VREF = 3V - 90 135 µA VCC = 3.0V, HDQ = 0 - 120 180 µA VCC = 4.25V, HDQ = 0 - 170 250 µA VCC = 6.5V, HDQ = 0 VCC V Normal operation VSB Battery input 0 - RSBmax SB input impedance 10 - - MΩ IDISP DISP input leakage - - 5 µA VDISP = VSS ILCOM LCOM input leakage -0.2 - 0.2 µA DISP = VCC IRBI RBI data retention current - - 100 nA VRBI > VCC < 3V RHDQ Internal pulldown 500 - - KΩ RSR SR input impedance 10 - - MΩ VIHPFC PROG logic input high VCC - 0.2 - - V PROG1-6 VILPFC PROG logic input low - - VSS + 0.2 V PROG1-6 VIZPFC PROG logic input Z float - float V PROG1-6 0 < VSB < VCC VSR < VCC VOLSL SEG output low, low VCC - 0.1 - V VCC = 3V, IOLS ≤ 1.75mA SEG1–5, CP VOLSH SEG output low, high VCC - 0.4 - V VCC = 6.5V, IOLS ≤ 11.0mA SEG1–5, CP VOHML LCOM output high, low VCC VCC - 0.3 - - V VCC = 3V, IOHLCOM = -5.25mA VOHMH LCOM output high, high VCC VCC - 0.6 - - V VCC > 3.5V, IOHLCOM = -33.0mA IOLS SEG sink current 11.0 - - mA At VOLSH = 0.4V, VCC = 6.5V IOL Open-drain sink current 5.0 - - mA At VOL = VSS + 0.3V, HDQ VOL Open-drain output low - - 0.3 V IOL ≤ 5mA, HDQ VIHDQ HDQ input high 2.5 - - V HDQ VILDQ HDQ input low - - 0.8 V HDQ RPROG Soft pull-up or pull-down resistor value (for programming) - - 200 KΩ PROG1–PROG6 RFLOAT Float state external impedance - 5 - MΩ PROG1–6 Note: All voltages relative to VSS. 14 Preliminary bq2052 Serial Communication Timing Specification (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tCYCH Cycle time, host to bq2052 (write) 190 - - µs tCYCB Cycle time, bq2052 to host (read) 190 205 250 µs tSTRH Start hold, host to bq2052 (write) 5 - - ns tSTRB Start hold, bq2052 to host (read) 32 - - µs tDSU Data setup - - 50 µs tDSUB Data setup - - 50 µs tDH Data hold 90 - - µs tDV Data valid - - 80 µs tSSU Stop setup - - 145 µs tSSUB Stop setup - - 145 µs tRSPS Response time, bq2052 to host 190 - 320 µs tB Break 190 - - µs tBR Break recovery 40 - - µs Note: Notes See note The open-drain HDQ pin should be pulled to at least VCC by the host system for proper HDQ operation. HDQ may be left floating if the serial interface is not used. 15 bq2052 Preliminary Break Timing tBR tB TD201803.eps Host to bq2052 Write "1" Write "0" tSTRH tDSU tDH tSSU tCYCH bq2052 to Host Read "1" Read "0" tSTRB tDSUB tDV tSSUB tCYCB 16 Preliminary bq2052 16-Pin SOIC Narrow (SN) 16-Pin SN (SOIC Narrow) D Dimension Minimum A 0.060 A1 0.004 B 0.013 C 0.007 D 0.385 E 0.150 e 0.045 H 0.225 L 0.015 All dimensions are in inches. B e E H A C A1 .004 L Ordering Information bq2052 Temperature Range: blank = Commercial (-20 to +70°C) Package Option: SN = 16-pin narrow SOIC Device: bq2052 Gas Gauge IC 17 Maximum 0.070 0.010 0.020 0.010 0.400 0.160 0.055 0.245 0.035 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ2052SN-A515 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -20 to 70 2052 A515 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of