bq24105-Q1
www.ti.com
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
SYNCHRONOUS SWITCHMODE, LI-ION AND LI-POLYMER CHARGE-MANAGEMENT
IC WITH INTEGRATED POWER FETs ( bqSWITCHER™)
Check for Samples: bq24105-Q1
FEATURES
DESCRIPTION
•
•
The bqSWITCHER™ series are highly integrated Liion and Li-polymer switch-mode charge management
devices targeted at a wide range of portable
applications. The bqSWITCHER™ series offers
integrated synchronous PWM controller and power
FETs, high-accuracy current and voltage regulation,
charge preconditioning, charge status, and charge
termination, in a small, thermally enhanced QFN
package.
•
•
•
•
•
•
•
•
•
•
•
•
The bqSWITCHER charges the battery in three
phases: conditioning, constant current, and constant
voltage. Charge is terminated based on userselectable minimum current level. A programmable
charge timer provides a safety backup for charge
termination. The bqSWITCHER automatically restarts
the charge cycle if the battery voltage falls below an
internal threshold. The bqSWITCHER automatically
enters sleep mode when VCC supply is removed.
RHL PACKAGE
(TOP VIEW)
STAT1
IN
IN
PG
VCC
TTC
ISET1
ISET2
2
1
OUT
•
20 19
3
18
4
17
5
16
6
15
7
14
8
13
9 10
11 12
STAT2
PGND
PGND
CE
SNS
BAT
FB
TS
VTSB
•
Qualified for Automotive Applications
Ideal For Highly Efficient Charger Designs For
Single-, Two-, or Three-Cell Li-Ion and LiPolymer Battery Packs
Also for LiFePO4 Battery (see Using bq24105
to Charge LiFePO4 Battery)
Integrated Synchronous Fixed-Frequency
PWM Controller Operating at 1.1 MHz
With 0% to 100% Duty Cycle
Integrated Power FETs For Up To 2-A Charge
Rate
High-Accuracy Voltage and Current Regulation
Stand-Alone (Built-In Charge Management and
Control) Version
Status Outputs For LED or Host Processor
Interface Indicates Charge-In-Progress, Charge
Completion, Fault, and AC-Adapter Present
Conditions
20-V Maximum Voltage Rating on IN and OUT
Pins
High-Side Battery Current Sensing
Battery Temperature Monitoring
Automatic Sleep Mode for Low Power
Consumption
Reverse Leakage Protection Prevents Battery
Drainage
Thermal Shutdown and Protection
Built-In Battery Detection
Available in 20-Pin, 3.5 mm × 4.5 mm, QFN
Package
OUT
23
VSS
1
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
bqSWITCHER, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
bq24105-Q1
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
QFN – RHL
ORDERABLE PART NUMBER
Reel of 3000
BQ24105IRHLRQ1
TOP-SIDE MARKING
BQ24105
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range (with respect to VSS)
Input voltage range (with respect to VSS and PGND)
IN, VCC
20 V
STAT1, STAT2, PG, CE, SNS, BAT
–0.3 V to 20 V
OUT
–0.7 V to 20 V
TS, TTC
7V
VTSB
3.6 V
ISET1, ISET2
3.3 V
Voltage difference between SNS and BAT inputs (VSNS – VBAT)
Output sink
STAT1, STAT2, PG
Output current (average)
OUT
±1 V
10 mA
2.2 A
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Junction temperature range
–40°C to 125°C
Tstg
Storage temperature
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
300°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
(1)
PACKAGE
θJA
θJC
TA < 40°C
POWER RATING
DERATING FACTOR
ABOVE TA = 40°C
RHL (1)
46.87°C/W
2.5°C/W
1.81 W
0.021 W/°C
This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
Supply voltage, VCC and IN (Tie together)
4.35 (1)
16 (2)
V
Operating junction temperature range, TJ
–40
125
°C
(1)
(2)
UNIT
The IC continues to operate below Vmin, to 3.5 V, but the specifications are not tested and not specified.
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the IN or OUT pins. A tight layout
minimizes switching noise.
ELECTRICAL CHARACTERISTICS
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Currents
2
Copyright © 2009–2012, Texas Instruments Incorporated
bq24105-Q1
www.ti.com
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
VCC > VCC(min), PWM switching
I(VCC)
I(SLP)
VCC supply current
Battery discharge sleep current, (SNS,
BAT, OUT, FB pins)
TYP
MAX
10
VCC > VCC(min), PWM NOT switching
5
VCC > VCC(min), CE = HIGH
315
0°C ≤ TJ ≤ 65°C, VI(BAT) = 4.2 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
3.5
0°C ≤ TJ ≤ 65°C, VI(BAT) = 8.4 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
5.5
0°C ≤ TJ ≤ 65°C, VI(BAT) = 12.6 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
7.7
UNIT
mA
μA
μA
Voltage Regulation
VIBAT
Feedback regulation REF for bq24105
(W/FB)
Voltage regulation accuracy
IIBAT = 25 nA typical into pin
2.1
TA = 25°C
V
–0.5%
0.5%
–1%
1%
150
2000
–10%
10%
Current Regulation - Fast Charge
IOCHARGE
Output current range of converter
VLOWV ≤ VI(BAT) < VOREG,
V(VCC) - VI(BAT) > V(DO-MAX)
mA
100 mV ≤ VIREG≤ 200 mV,
V
IREG
+
1V
RSET1
1000,
VIREG
Voltage regulated across R(SNS) Accuracy
V(ISET1)
Output current set voltage
V(LOWV) ≤ VI(BAT) ≤ VO(REG),
V(VCC) ≤ VI(BAT) × V(DO-MAX)
1
K(ISET1)
Output current set factor
VLOWV ≤ VI(BAT) < VO(REG),
V(VCC) ≤ VI(BAT) + V(DO-MAX)
1000
Programmed Where
5 kΩ ≤ RSET1 ≤ 10 kΩ, Select RSET1 to
program VIREG,
VIREG(measured) = IOCHARGE + RSNS
(–10% to 10% excludes errors due to RSET1
and R(SNS) tolerances)
V
V/A
Precharge and Short-Circuit Current Regulation
VLOWV
Precharge to fast-charge transition voltage
threshold, BAT,
bq24100/03/03A/04/05/08/09 ICs only
t
Deglitch time for precharge to fast charge
transition,
IOPRECHG
V(ISET2)
K(ISET2)
Precharge current set factor
68
71.4
75
%VO(REG)
Rising voltage;
tRISE, tFALL = 100 ns, 2-mV overdrive
20
30
40
ms
Precharge range
VI(BAT) < VLOWV, t < tPRECHG
15
200
mA
Precharge set voltage, ISET2
VI(BAT) < VLOWV, t < tPRECHG
100
mV
1000
V/A
100 mV ≤ VIREG-PRE ≤ 100 mV,
V
VIREG-PRE
Voltage regulated across RSNS-Accuracy
IREG*PRE
+ 0.1V
RSET2
1000,
(PGM) Where
1.2 kΩ ≤ RSET2 ≤ 10 kΩ, Select RSET1
to program VIREG-PRE,
VIREG-PRE (Measured) = IOPRE-CHG × RSNS
(–20% to 20% excludes errors due to RSET1
and RSNS tolerances)
–20%
20%
15
200
Charge Termination (Current Taper) Detection
ITERM
Charge current termination detection range
VI(BAT) > VRCH
VTERM
Charge termination detection set voltage,
ISET2
VI(BAT) > VRCH
K(ISET2)
Termination current set factor
tdg-TERM
100
mV
1000
Charger termination accuracy
VI(BAT) > VRCH
Deglitch time for charge termination
Both rising and falling,
2-mV overdrive tRISE, tFALL = 100 ns
–20%
20
mA
V/A
20%
30
40
ms
Temperature Comparator and VTSB Bias Regulator
Copyright © 2009–2012, Texas Instruments Incorporated
3
bq24105-Q1
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
MIN
TYP
MAX
%LTF
Cold temperature threshold, TS, % of bias
PARAMETER
VLTF = VO(VTSB) × % LTF/100
TEST CONDITIONS
72.8%
73.5%
74.2%
%HTF
Hot temperature threshold, TS, % of bias
VHTF = VO(VTSB) × % HTF/100
33.7%
34.4%
35.1%
%TCO
Cutoff temperature threshold, TS, % of
bias
VTCO = VO(VTSB) × % TCO/100
28.7%
29.3%
29.9%
0.5%
1%
1.5%
20
30
40
LTF hysteresis
tdg-TS
Deglitch time for temperature fault, TS
Both rising and falling,
2-mV overdrive tRISE, tFALL = 100 ns
VO(VTSB)
TS bias output voltage
VCC > VIN(min),
I(VTSB) = 10 mA 0.1 μF ≤ CO(VTSB) ≤ 1 μF
VO(VTSB)
TS bias voltage regulation accuracy
VCC > IN(min),
I(VTSB) = 10 mA 0.1 μF ≤ CO(VTSB) ≤ 1 μF
3.15
–10%
UNIT
ms
V
10%
Battery Recharge Threshold
VRCH
tdg-RCH
Recharge threshold voltage
Below VOREG
75
100
125
mV/cell
Deglitch time
VI(BAT) < decreasing below threshold,
tFALL = 100 ns 10-mV overdrive
20
30
40
ms
Stat1, Stat2, and PG Outputs
VOL(STATx)
Low-level output saturation voltage, STATx
IO = 5 mA
0.5
VOL(PG)
Low-level output saturation voltage, PG
IO = 10 mA
0.1
VIL
Low-level input voltage
IIL = 5 μA
VIH
High-level input voltage
IIH = 20 μA
V
CE Input
0
0.4
1.3
VCC
V
TTC Input
tPRECHG
Precharge timer
tCHARGE
Programmable charge timer range
t(CHG) = C(TTC) × K(TTC)
Charge timer accuracy
0.01 μF ≤ C(TTC) ≤ 0.18 μF
KTTC
Timer multiplier
CTTC
Charge time capacitor range
VTTC_EN
TTC enable threshold voltage
4
1440
1800
25
-10%
2160
s
572
minutes
10%
2.6
0.01
V(TTC) rising
min/nF
0.22
200
μF
mV
Copyright © 2009–2012, Texas Instruments Incorporated
bq24105-Q1
www.ti.com
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Sleep Comparator
VSLP-ENT
Sleep-mode entry threshold
VSLP-EXIT
Sleep-mode exit hysteresis,
tdg-SLP
Deglitch time for sleep mode
2.3 V ≤ VI(OUT) ≤ VOREG, for 1 or 2 cells
VCC ≤ VIBAT
+5 mV
VCC ≤ VIBAT
+75 mV
VI(OUT) = 12.6 V, RIN = 1 kΩ
bq24105/15 (1)
VCC ≤ VIBAT
-4 mV
VCC ≤ VIBAT
+73 mV
40
160
2.3 V ≤ VI(OUT)≤ VOREG
VCC decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive,
PMOS turns off
VCC decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive,
STATx pins turn off
V
mV
μs
5
20
30
40
3.50
ms
UVLO
VUVLO-ON
IC active threshold voltage
VCC rising
3.15
3.30
IC active hysteresis
VCC falling
120
150
V
mV
PWM
Internal P-channel MOSFET on-resistance
Internal N-channel MOSFET on-resistance
fOSC
7 V ≤ VCC ≤ VCC(max)
400
4.5 V ≤ VCC ≤ 7 V
500
7 V ≤ VCC ≤ VCC(max)
130
4.5 V ≤ VCC ≤ 7 V
150
Oscillator frequency
1.1
Frequency accuracy
mΩ
–9%
MHz
9%
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
100%
tTOD
Switching delay time (turn on)
20
ns
tsyncmin
Minimum synchronous FET on time
60
ns
0%
Synchronous FET minimum current-off
threshold (2)
50
400
mA
Battery Detection
IDETECT
Battery detection current during time-out
fault
VI(BAT) < VOREG – VRCH
IDISCHRG1
Discharge current
tDISCHRG1
Discharge time
IWAKE
tWAKE
2
mA
VSHORT < VI(BAT) < VOREG – VRCH
400
μA
VSHORT < VI(BAT) < VOREG – VRCH
1
s
Wake current
VSHORT < VI(BAT) < VOREG – VRCH
2
mA
Wake time
VSHORT < VI(BAT) < VOREG – VRCH
0.5
s
IDISCHRG2
Termination discharge current
Begins after termination detected,
VI(BAT) ≤ VOREG
400
μA
tDISCHRG2
Termination time
262
ms
Output Capacitor
COUT
Required output ceramic capacitor range
from SNS to PGND, between inductor and
RSNS
CSNS
Required SNS capacitor (ceramic) at SNS
pin
4.7
10
47
μF
μF
0.1
Protection
Threshold over VOREG to turn off P-channel
MOSFET, STAT1, and STAT2 during charge
or termination states
110
117
2.6
3.6
4.5
A
Short-circuit voltage threshold, BAT
VI(BAT) falling
1.95
2
2.05
V/cell
ISHORT
Short-circuit current
VI(BAT) ≤ VSHORT
TSHTDWN
Thermal trip
VOVP
OVP threshold voltage
ILIMIT
Cycle-by-cycle current limit
VSHORT
Thermal hysteresis
(1)
(2)
35
121
65
%VO(REG)
mA
165
°C
10
°C
For bq24105 and bq24115 only. RIN is connected between IN and PGND pins and needed to ensure sleep entry.
N-channel always turns on for ~60 ns and then turns off if current is too low.
Copyright © 2009–2012, Texas Instruments Incorporated
5
bq24105-Q1
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BAT
14
I
Battery voltage sense input. Bypass it with a 0.1 μF capacitor to PGND if there are long inductive leads
to battery.
CE
16
I
Charger enable input. This active low input, if set high, suspends charge and places the device in the
low-power sleep mode. Do not pull up this input to VTSB.
FB
13
I
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider powered
from the battery terminals to this node to adjust the output battery voltage regulation.
IN
Charger input voltage.
3, 4
I
ISET1
8
I/O
Charger current set point 1 (fast charge). Use a resistor to ground to set this value.
ISET2
9
I/O
Charge current set point 2 (precharge and termination), set by a resistor connected to ground.
1, 20
O
Charge current output inductor connection. Connect a zener TVS diode between OUT pin and PGND
pin to clamp the voltage spike to protect the power MOSFETs during abnormal conditions.
5
O
Power-good status output (open drain). The transistor turns on when a valid VCC is detected. It is turned
off in the sleep mode. PG can be used to drive a LED or communicate with a host processor.
OUT
PG
PGND
17,18
Power ground input
SNS
15
I
Charge current-sense input. Battery current is sensed via the voltage drop developed on this pin by an
external sense resistor in series with the battery pack. A 0.1-μF capacitor to PGND is required.
STAT1
2
O
Charge status 1 (open-drain output). When the transistor turns on indicates charge in process. When it
is off and with the condition of STAT2 indicates various charger conditions (see Table 1).
STAT2
19
O
Charge status 2 (open-drain output). When the transistor turns on indicates charge is done. When it is
off and with the condition of STAT1 indicates various charger conditions (see Table 1).
TS
12
I
Temperature sense input. This input monitors its voltage against an internal threshold to determine if
charging is allowed. Use an NTC thermistor and a voltage divider powered from VTSB to develop this
voltage (see Figure 6).
TTC
7
I
Timer and termination control. Connect a capacitor from this node to GND to set the bqSWITCHER
timer. When this input is low, the timer and termination detection are disabled.
VCC
6
I
Analog device input. A 0.1-μF capacitor to VSS is required.
VSS
10
VTSB
11
Exposed
Thermal Pad
6
Pad
Analog ground input
O
TS internal bias regulator voltage. Connect capacitor (with a value between a 0.1-μF and 1-μF) between
this output and VSS.
There is an internal electrical connection between the exposed thermal pad and VSS. The exposed
thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. The
power pad can be used as a star ground connection between VSS and PGND. A common ground plane
may be used. VSS pin must be connected to ground at all times.
Copyright © 2009–2012, Texas Instruments Incorporated
bq24105-Q1
www.ti.com
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
TYPICAL APPLICATION CIRCUIT
LOUT
BQ24105
VIN
CIN
1.5 KW
10 mF
1.5 KW
Adapter
Present
1.5 KW
Done
Charge
3
IN
4
IN
OUT 1
6
VCC
2
STAT1 PGND 18
RSNS
10 mH
OUT 20
D1
COUT
0.1W
10 mF
Battery
Pack
Pack+
Pack-
MMBZ18VALT1
PGND 17
103AT
19 STAT2
5
PG
7
TTC
SNS 15
BAT 14
ISET1 8
7.5 KW RISET1
VTSB
7.5 KW
CTTC
16 CE
ISET2 9
0.1 mF
10 VSS
0.1 mF
13 FB
9.31 KW
RT1
442 KW
RT2
RISET2
TS 12
VTSB 11
0.1 mF
0.1 mF
301 KW
100 KW
Figure 1. Stand-Alone 2-Cell Application
Copyright © 2009–2012, Texas Instruments Incorporated
7
bq24105-Q1
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
www.ti.com
TYPICAL OPERATING PERFORMANCE
EFFICIENCY
vs
CHARGE CURRENT
100
90
Efficiency - %
VI = 5 V
80
VI = 16 V
70
V(BAT) = 4.2 V
1-Cell
60
50
0
0.5
1
2
1.5
I(BAT) - Charge Current - A
Figure 2.
EFFICIENCY
vs
CHARGE CURRENT
100
VI = 9 V
90
Efficiency - %
VI = 16 V
80
70
V(BAT) = 8.4 V
2-Cell
60
50
0
0.5
1
1.5
2
I(BAT) - Charge Current - A
Figure 3.
8
Copyright © 2009–2012, Texas Instruments Incorporated
Copyright © 2009–2012, Texas Instruments Incorporated
VCC
VSS
TTC
STAT2
STAT1
CE
PG
0.5V
1V
CE
CHARGE
50 mV
BAT
TERM
OVP
Charge
(STATE
MACHINE)
TIMER
FF CHAIN
PRE-CHG
TIMEOUT
TIMER CLK
*Patent Pending #36889
TG
CONTROL
LOGIC
DSABL_TERM
PRE-CHARGE
WAKE
DISCHARGE
0.75V
bq2410x
VCC
V(3.6A)
Icntrl
Sense FET
VCC-6V
Poff VCC PG
2.1V
0.25V
SLEEP
VCC-6V
bqSWITCHER
VCC
VTSB
Voltage
Reference
Vuvlo UVLO/POR
POR
CHARGE
SLEEP
OVP
MOD
FAST CHG
TIMEOUT
RESET
SLEEP
SYNCH
VSHORT
LowV 30ms
Dgltch
BAT_PRS_dischg
Vrch 30ms
Dgltch
Vovp
Q S
Q R
I
2.1V
BAT
VCC
+
-
SNS+
1V
TS
SPIN
SUSPEND
FASTCHG
Disable
BAT
20uA
VCC
Ibat Reg
+
-
+
-
+
-
TCO
HTF
LTF
30ms
dgltch
PRE-CHG
Disable
0.1V
FASTCHG
Disable
TEMP
SUSPEND
0.1V
SNS
+
1k
-
TERM
SLEEP
SUSPEND
1V
Vbat Reg
+
2.1V
20uA
VCC
VCC
RAMP
(Vpp=VCC/10)
VCC
RAMP
OSC
VCC/10
*
COMPENSATION
Discharge
Charge
PkILim
+
BG
Wake
Vreg
BAT
CLAMP
Synch
Gate
Drive
TG
VSHORT
BAT_PRS_
disch
LowV
Term_Det
Vrch
UVLO/
POR
SUSPEND
6V
VCC-6V
VCC
V(150 mA)
Isynch
PkILim or OVP
TIMEOUT FAULT
SUSPEND
TERM
UVLO/POR
MOD
OVP
SYNCH
TIMEOUT
PkILim
BG
Sense FET
1C
2C
FB
SPIN
BAT
1k
Term_Det
VTSB
+
-
10
Co
10 F
H
Lo
Rsns
TS
ISET2
ISET1
VTSB
RSET2
RSET1
FB
CELLS (bq24103/04/13)
FB (bq24105/15)
N/C (bq24100)
VTSB
BAT
SNS
PGND
PGND
OUT
OUT
to FB
FB
SPIN
ONLY
Temp
Pack-
+
Pack+
www.ti.com
Term &
Timer
Disable
VCC
VTSB
VCC
VTSB
VCC
IN
IN
+
-
VIN
Protection PMOS FET is OFF when not charging
or in SLEEP to prevent discharge of battery
when IN < BAT
bq24105-Q1
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
FUNCTIONAL BLOCK DIAGRAM
9
bq24105-Q1
SLUS953A – AUGUST 2009 – REVISED APRIL 2012
www.ti.com
OPERATIONAL FLOW CHART
POR
Check for Battery
Presence
Battery
Detect?
No
Indicate BATTERY
ABSENT
Yes
Suspend Charge
TS Pin
in LTF to HTF
Range?
No
Indicate CHARGE
SUSPEND
Yes
VBAT
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