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BQ24153AYFFT

BQ24153AYFFT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    20-UFBGA,DSBGA

  • 描述:

    IC LI-ION CHARGER MGMT 20DSBGA

  • 数据手册
  • 价格&库存
BQ24153AYFFT 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 bq2415x Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support bq24153A, bq24156A, bq24159 1 Features • • 1 • • • • • • • • • • • • • • Charge Faster than Linear Chargers High-Accuracy Voltage and Current Regulation – Input Current Regulation Accuracy: ±5% (100 mA and 500 mA) – Charge Voltage Regulation Accuracy: ±0.5% (25°C), ±1% (0°C to 125°C) – Charge Current Regulation Accuracy: ±5% Input Voltage Based Dynamic Power Management (VIN DPM) Bad Adaptor Detection and Rejection Safety Limit Register for Maximum Charge Voltage and Current Limiting High-Efficiency Mini-USB/AC Battery Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs 20-V Absolute Maximum Input Voltage Rating 9-V Maximum Operating Input Voltagebq24156A/9 6-V Maximum Operating Input Voltagebq24153A/8 Built-In Input Current Sensing and Limiting Integrated Power FETs for Up To 1.55-A Charge Rate Programmable Charge Parameters through I2C™ Compatible Interface (up to 3.4 Mbps): – Input Current Limit – VIN DPM Threshold – Fast-Charge/Termination Current – Charge Regulation Voltage (3.5 V to 4.44 V) – Low Charge Current Mode Enable/Disable – Safety Timer with Reset Control – Termination Enable/Disable Support up to 1.55 A Charge Current Using 55mΩ Sensing Resistor Synchronous Fixed-Frequency PWM Controller Operating at 3 MHz With 0% to 99.5% Duty Cycle Automatic High Impedance Mode for Low Power Consumption Robust Protection – Reverse Leakage Protection Prevents Battery Drainage – Thermal Regulation and Protection – Input/Output Overvoltage Protection • • • • • • Status Output for Charging and Faults USB Friendly Boot-Up Sequence Automatic Charging Power Up System without Battery bq24158/9 Boost Mode Operation for USB OTG: (bq24153A/8 only) – Input Voltage Range (from Battery): 2.5 V to 4.5 V – Output for VBUS: 5.05 V/ 200 mA 2.1 mm x 2 mm 20-Pin WCSP Package 2 Applications • • • Mobile and Smart Phones MP3 Players Handheld Devices 3 Description The bq24153A/6A/8/9 is a compact, flexible, highefficiency, USB-friendly switch-mode charge management device for single-cell Li-ion and Lipolymer batteries used in a wide range of portable applications. The charge parameters can be programmed through an I2C interface. The IC integrates a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a small WCSP package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) bq24153A, bq24156A, 20-Pin WCSP bq24158, bq24159 2.1 mm x 2 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Circuit VBUS VBUS 1 µF CIN VAUX PMID 4.7 µF HOST LO 1 µH 10 kΩ CD SCL SDA STAT OTG CD 10 kΩ VSNS 22 µF 33 nF BOOT PGND CO2 33 µF CSIN 0.1 µF CSOUT VREF VBAT CO1 CBOOT CSIN 10 kΩ 10 kΩ SCL SDA STAT OTG 10 kΩ SW U1 bq24153A/8 CIN PACK+ + PACK– CVREF CSOUT 0.1 µF 1 µF Copyright © 2016, Texas Intruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Device Comparisons ............................................. Pin Configuration and Functions ......................... Specifications......................................................... 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 1 1 1 2 4 4 5 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings ............................................................ 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 11 Typical Characteristics ............................................ 12 Detailed Description ............................................ 14 9.1 9.2 9.3 9.4 9.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... 14 15 17 21 26 9.6 Register Maps ........................................................ 30 10 Application and Implementation........................ 34 10.1 Application Information.......................................... 34 10.2 Typical Application ................................................ 34 10.3 System Example ................................................... 39 11 Power Supply Recommendations ..................... 40 11.1 System Load After Sensing Resistor .................... 40 11.2 System Load Before Sensing Resistor ................. 41 12 Layout................................................................... 42 12.1 Layout Guidelines ................................................. 42 12.2 Layout Example .................................................... 43 13 Device and Documentation Support ................. 44 13.1 13.2 13.3 13.4 13.5 13.6 Third-Party Products Disclaimer ........................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 44 44 44 44 44 44 14 Mechanical, Packaging, and Orderable Information ........................................................... 45 14.1 Package Summary................................................ 45 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2013) to Revision D Page • Added the Device Information table, ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply Recommendation section, Layout section, Device and Documentation Support section, and the Mechanical, Packaging, and Orderable Information section.......................................................... 1 • Changed Features bullet From: "...1.5-A Charge Rate" To: "...1.55-A Charge Rate" ............................................................ 1 • Added Features bullet: "Support up to 1.55A......Sensing Resistor " ..................................................................................... 1 • Added information to the Device Comparisons table. ............................................................................................................ 4 • Changed t32S in the Timing Requirements table, PROTECTION section, MAX value From: 32s To 40s .......................... 11 • Added information to bullet note at Table 9 for clarification. ............................................................................................... 33 Changes from Revision B (August 2012) to Revision C Page • Changed Boot capacitor value from 10 nF to 33 nF in Typical Application Circuit ................................................................ 1 • Changed BOOT capacitor value from 10 nF to 33 nF in Pin Functions Description.............................................................. 5 • Changed CBOOT capacitor value from 10 nF to 33 nF in Figure 25 and Figure 36 .............................................................. 34 Changes from Revision A (February 2012) to Revision B Page • Changed the revision to Rev B, August 2012 ........................................................................................................................ 1 • Deleted the last sentence in the PIN Functions table: Name CD, in the description column ................................................ 5 • Changed IO(CHARGE) Test Conditions statement from "V(LOWV)" to "V(SHORT)" ........................................................................... 7 • Deleted from the CD Pin (Charge Disable) section the last sentence: In 15-minute....32-second timer. ............................ 24 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Changes from Original (October 2010) to Revision A Page • Added bq24159 throughout this data sheet. .......................................................................................................................... 1 • Changed the Device Comparisons table ................................................................................................................................ 4 Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 3 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 5 Description (Continued) The IC charges the battery in three phases: conditioning, constant current and constant voltage. The input current is automatically limited to the value set by the host. Charge is terminated based on battery voltage and user-selectable minimum current level. A safety timer with reset control provides a safety backup for I2C interface. During normal operation, The IC automatically restarts the charge cycle if the battery voltage falls below an internal threshold and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge status can be reported to the host using the I2C interface. During the charging process, the IC monitors its junction temperature (TJ) and reduces the charge current once TJ increases to about 125°C. To support USB OTG device, bq24153A/8 can provide VBUS (5.05 V) by boosting the battery voltage. The IC is available in 20-pin WCSP package. 6 Device Comparisons PART NUMBER bq24153A bq24156A bq24158 6.5 9.8 6.5 9.8 OTG SLRST OTG SLRST ICHARGE(MAX) at POR in 15-minute mode with R(SNS) = 68 mΩ (55 mΩ) and OTG=High on bq24153A/8 (mA) 325 (402) 325 (N/A) 325 (402) 325 (N/A) ICHARGE(MAX) in HOST mode with R(SNS) = 68 mΩ (55 mΩ) and Safety Limit Register increased from default (A) (1) 1.25 (1.55A) 1.55 (N/A) 1.25 (1.55A) 1.55(N/A) 1.55 N/A 1.55 N/A 3.54 3.54 3.54 3.54 Yes No Yes No 500mA 100mA (OTG=LOW); 500mA (OTG=High) 500mA VOVP (V) D4 Pin Definition Output regulation voltage at POR (V) Boost Function 100mA (OTG=LOW); 500mA (OTG=High) Input Current Limit in 15Min Mode bq24159 Battery Detection at Power Up Yes Yes No No I2C Address 6BH 6AH 6AH 6AH PN1 (bit4 of 03H) 1 0 1 0 PN0 (bit3 of 03H) 0 0 0 0 Enabled Enabled Enabled Enabled Safety Timer and WD Timer (1) 4 See Application Section for more explanation and calculations on using different sense resistors. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 7 Pin Configuration and Functions YFF Package 20-Pin Bump DSBGA bq24153A/8 (Top View) bq24156A/9 (Top View) A1 A2 A3 A4 A1 A2 A3 A4 VBUS VBUS BOOT SCL VBUS VBUS BOOT SCL B3 B4 B1 B3 B4 PMID B1 PMID B2 PMID SDA PMID PMID B2 PMID SDA C1 C2 C3 C4 C1 C2 C3 C4 SW SW SW STAT SW SW SW STAT D1 D2 D3 D4 D1 D2 D3 D4 PGND PGND PGND OTG PGND PGND PGND SLRST E1 E2 E3 E4 E1 E2 E3 E4 CD VREF CSOUT CSIN CD VREF CSOUT CSIN Pin Functions PIN I/O DESCRIPTION A3 I/O Bootstrap capacitor connection for the high-side FET gate driver. Connect a 33-nF ceramic capacitor (voltage rating ≥ 10 V) from BOOT pin to SW pin. CD E2 I Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to GND. CSIN E1 I Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor to PGND is required. CSOUT E4 I Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are long inductive leads to battery. I Boost mode enable control or input current limiting selection pin. When OTG is in active status, bq24153A/8 is forced to operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR while in 15-min mode, the OTG pin is default to be used as the input current limiting selection pin. The I2C register is ignored at startup. When OTG=High, IIN_LIMIT=500mA and when OTG=Low, IIN_LIMIT=100mA. NAME NO. BOOT OTG (bq24153A/8 only) D4 PGND D1, D2, D3 PMID B1, B2, B3 I/O SCL A4 I I2C interface clock. Connect a 10-kΩ pullup resistor to 1.8V rail (VAUX= VCC_HOST) SDA B4 I/O I2C interface data. Connect a 10-kΩ pullup resistor to 1.8V rail (VAUX= VCC_HOST) SLRST (bq24156A/9 only) D4 I Safety limit register reset control. When SLRST=0, bq24156A/9 resets all the safety limits (06H) to default values, regardless of the write actions to safety limits registers (06H). When SLRST=1, bq24156A/9 can program the safety limit register until any write action to other registers locks the programmed safety limits. STAT C4 O Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with a host processor. C1, C2, C3 O Internal switch to output inductor connection. VBUS A1, A2 I/O Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the load during boost mode (bq24153A/8 only) . VREF E3 O Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is not recommended. SW Power ground Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF capacitor from PMID to PGND. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 5 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) bq24153A/6A/8/9 MIN MAX UNIT Supply voltage (with respect to PGND (3)) VBUS; VPMID ≥ VBUS –0.3 V –2 20 V Input voltage (with respect to PGND (3)) SCL, SDA, OTG, SLRST, CSIN, CSOUT, CD –0.3 7 V PMID, STAT –0.3 20 V 7 V –0.7 20 V –7 7 V –0.3 7 V –7 0.7 V –0.7 20 V 10 mA Output voltage (with respect to PGND (3)) VREF SW, BOOT Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT) ) Voltage difference between BOOT and SW inputs (V(BOOT) – V(SW) ) Voltage difference between VBUS and PMID inputs (V(VBUS) – V(PMID) ) Voltage difference between PMID and SW inputs (V(PMID) – V(SW) ) Output sink STAT Output Current (average) SW 1.55 (2) A TA Operating free-air temperature range –30 85 °C TJ Junction temperature –40 125 °C Tstg Storage temperature –45 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Duty cycle for output current should be less than 50% for 10- year life time when output current is above 1.25A. All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal, if not specified. Consult Packaging Section of the data sheet for thermal limitations and considerations of packages. 8.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions MIN NOM MAX UNIT VBUS Supply voltage, bq24153A/8 4 6 (1) V VBUS Supply voltage, bq24156A/9 4 9 (1) V TJ Operating junction temperature range –40 125 °C (1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight layout minimizes switching noise. 8.4 Thermal Information bq24153A/6A/8/9 THERMAL METRIC (1) YFF (DSBGA) UNIT 20 Pins RθJA Junction-to-ambient thermal resistance 85 °C/W RθJC(top) Junction-to-case (top) thermal resistance 25 °C/W RθJB Junction-to-board thermal resistance 55 °C/W ψJT Junction-to-top characterization parameter 4 °C/W ψJB Junction-to-board characterization parameter 50 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Thermal Information (continued) bq24153A/6A/8/9 THERMAL METRIC (1) YFF (DSBGA) UNIT 20 Pins RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W 8.5 Electrical Characteristics Circuit of Figure 25, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS VBUS > VBUS(min), PWM switching I(VBUS) VBUS supply current control 10 VBUS > VBUS(min), PWM NOT switching 0°C < TJ < 85°C, CD=1 or HZ_MODE=1 Ilgk mA 5 23 μA Leakage current from battery to VBUS pin 0°C < TJ < 85°C, V(CSOUT) = 4.2 V, High Impedance mode, VBUS = 0 V 15 5 μA Battery discharge current in High Impedance mode, (CSIN, CSOUT, SW pins) 0°C < TJ < 85°C, V(CSOUT) = 4.2 V, High Impedance mode, V = 0 V, SCL, SDA, OTG = 0 V or 1.8 V 23 μA V VOLTAGE REGULATION V(OREG) Output regulation voltage programable range Operating in voltage regulation, programmable TA = 25°C Voltage regulation accuracy 3.5 4.44 –0.5% 0.5% –1% 1% CURRENT REGULATION (FAST CHARGE) IO(CHARGE) Output charge current programmable range bq24153A/8, V(SHORT) ≤ V(CSOUT) < V(OREG), VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG=0, Programmable 550 bq24156A/9, V(SHORT) ≤ V(CSOUT) < V(OREG), VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG=0, Programmable 550 VSHORT ≤ VCSOUT < VOREG, VBUS >VSLP, Low charge current (default after POR in 15 min RSNS= 68 mΩ, LOW_CHG=1, OTG=High for mode) for bq24153A/6A/8/9 bq24153A/8 Regulation accuracy of the voltage across R(SNS) (for charge current regulation) V(IREG) = IO(CHARGE) × R(SNS) 325 37.4 mV ≤ V(IREG)< 44.2mV 44.2 mV ≤ V(IREG) 1250 mA 1550 mA 350 mA –3.5% 3.5% –3% 3% 3.4 3.7 WEAK BATTERY DETECTION V(LOWV) Weak battery voltage threshold programmable range2 (1) Adjustable using I2C control Weak battery voltage accuracy Hysteresis for V(LOWV) –5% Battery voltage falling V 5% 100 mV CD, OTG and SLRST PIN LOGIC LEVEL VIL Input low threshold level VIH Input high threshold level I(bias) Input bias current 0.4 V 1.0 µA 1.3 V Voltage on control pin is 5 V CHARGE TERMINATION DETECTION I(TERM) Termination charge current programmable range Regulation accuracy for termination current across R(SNS) V(IREG_TERM) = IO(TERM) × R(SNS) V(CSOUT) > V(OREG) – V(RCH), VBUS > V(SLP), R(SNS) = 68 mΩ, Programmable 3.4 mV ≤ V(IREG_TERM) ≤ 6.8 mV 50 400 –15% 15% 6.8 mV < V(IREG_TERM) ≤ 17 mV –10% 10% 17 mV < V(IREG_TERM) ≤ 27.2 mV –5.5% 5.5% mA BAD ADAPTOR DETECTION VIN(min) ISHORT (1) Input voltage lower limit BAD ADAPTOR DETECTION 3.6 Hysteresis for VIN(min) Input voltage rising 100 Current source to GND During bad adaptor detection 20 3.8 30 4.0 V 200 mV 40 mA While in 15-min mode, if a battery that is charged to a voltage higher than this voltage is inserted, the charger enters Hi-Z mode and awaits I2C commands. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 7 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Electrical Characteristics (continued) Circuit of Figure 25, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT BASED DYNAMIC POWER MANAGEMENT VIN_DPM Input Voltage DPM threshold programmable range VIN DPM threshold accuracy 8 Submit Documentation Feedback 4.2 4.76 –3% 1% V Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Electrical Characteristics (continued) Circuit of Figure 25, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX TJ = 0°C – 125°C 88 93 98 TJ = –40°C –125°C 86 93 98 TJ = 0°C – 125°C 450 475 500 TJ = –40°C –125°C 440 475 500 UNIT INPUT CURRENT LIMITING IIN = 100 mA IIN_LIMIT Input current limiting threshold IIN = 500 mA mA mA VREF BIAS REGULATOR VREF Internal bias regulator voltage VBUS >VIN(min) or V(CSOUT) > VBUS(min), I(VREF) = 1 mA, C(VREF) = 1 μF 2 VREF output short current limit 6.5 30 V mA BATTERY RECHARGE THRESHOLD V(RCH) Recharge threshold voltage Below V(OREG) 100 120 150 mV STAT OUTPUTS VOL(STAT) Low-level output saturation voltage, STAT pin IO = 10 mA, sink current High-level leakage current for STAT Voltage on STAT pin is 5 V 0.55 V 1 μA I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS VOL Output low threshold level IO = 10 mA, sink current 0.4 V VIL Input low threshold level V(pull-up) = 1.8 V, SDA and SCL 0.4 V VIH Input high threshold level V(pull-up) = 1.8 V, SDA and SCL I(BIAS) Input bias current V(pull-up) = 1.8 V, SDA and SCL 1 μA f(SCL) SCL clock frequency 1.2 V 3.4 MHz BATTERY DETECTION I(DETECT) Battery detection current before charge done (sink current) (2) Begins after termination detected, V(CSOUT) ≤ V(OREG) –0.5 mA SLEEP COMPARATOR V(SLP) Sleep-mode entry threshold, VBUS – VCSOUT 2.3 V ≤ V(CSOUT) ≤ V(OREG), VBUS falling V(SLP_EXIT) Sleep-mode exit hysteresis 0 40 100 mV 2.3 V ≤ V(CSOUT) ≤ V(OREG) 140 200 260 mV 3.55 UNDERVOLTAGE LOCKOUT (UVLO) UVLO IC active threshold voltage VBUS rising - Exits UVLO 3.05 3.3 UVLO(HYS) IC active hysteresis VBUS falling below UVLO - Enters UVLO 120 150 Voltage from BOOT pin to SW pin During charge or boost operation Internal top reverse blocking MOSFET onresistance IIN(LIMIT) = 500 mA, Measured from VBUS to PMID 180 250 Internal top N-channel Switching MOSFET onresistance Measured from PMID to SW, VBOOT – VSW= 4V 120 250 Internal bottom N-channel MOSFET onresistance Measured from SW to PGND 110 210 V mV PWM f(OSC) 6.5 Oscillator frequency 3.0 Frequency accuracy D(MAX) Maximum duty cycle D(MIN) Minimum duty cycle –10% mΩ MHz 10% 99.5% 0 Synchronous mode to non-synchronous mode transition current threshold (2) (2) V Low-side MOSFET cycle-by-cycle current sensing 100 mA Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 9 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Electrical Characteristics (continued) Circuit of Figure 25, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 6.3 6.5 6.7 UNIT CHARGE MODE PROTECTION VOVP_IN_USB VOVP-IN_DYN VOVP ILIMIT VSHORT ISHORT Input VBUS OVP threshold voltage (bq24153A/8) VBUS threshold to turn off converter during charge V(OVP_IN_USB) hysteresis (bq24153A/8) VBUS falling from above V(OVP_IN_USB) Input VBUS OVP threshold voltage (bq24156A) Threshold over VBUS to turn off converter during charge V(OVP_IN_DYN) hysteresis (bq24156A/9) VBUS falling from above V(OVP_IN_DYN) Output OVP threshold voltage V(CSOUT) threshold over V(OREG) to turn off charger during charge V(OVP) hysteresis Lower limit for V(CSOUT) falling from above V(OVP) Cycle-by-cycle current limit for charge Charge mode operation 1.8 2.4 3.0 Trickle to fast charge threshold V(CSOUT) rising 2.0 2.1 2.2 VSHORT hysteresis V(CSOUT) falling below VSHORT Trickle charge charging current V(CSOUT) ≤ VSHORT) 170 9.57 9.8 V mV 10 140 110 117 121 %V OREG 11 100 20 30 A V mV 40 mA BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0, bq24153A/8 only) VBUS_B Boost output voltage (to VBUS pin) 2.5V < V(CSOUT) < 4.5 V 5.05 Boost output voltage accuracy Including line and load regulation IBO Maximum output current for boost VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V IBLIMIT Cycle by cycle current limit for boost VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V VBUSOVP Overvoltage protection threshold for boost (VBUS pin) Threshold over VBUS to turn off converter during boost VBUSOVP hysteresis VBUS falling from above VBUSOVP Maximum battery voltage for boost (CSOUT pin) V(CSOUT) rising edge during boost VBATMAX hysteresis V(CSOUT) falling from above VBATMAX 200 During boosting 2.5 Before boost starts 2.9 VBATMAX VBATMIN Minimum battery voltage for boost (CSOUT pin) Boost output resistance at high-impedance mode (From VBUS to PGND) –3% V 3% 200 mA 1.0 5.8 6.0 A 6.2 162 4.75 CD = 1 or HZ_MODE = 1 4.9 217 V mV 5.05 V mV V 3.05 V kΩ PROTECTION TSHTDWN) Thermal trip 165 Thermal hysteresis TCF 10 10 Thermal regulation threshold Charge current begins to reduce Submit Documentation Feedback °C 120 Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 8.6 Timing Requirements MIN NOM MAX UNIT WEAK BATTERY DETECTION Deglitch time for weak battery threshold Rising voltage, 2-mV over drive, tRISE = 100 ns 30 ms Both rising and falling, 2-mV overdrive, tRISE, tFALL = 100 ns 30 ms Deglitch time for VBUS rising above VIN(min) Rising voltage, 2-mV overdrive, tRISE = 100 ns 30 ms Detection Interval Input power source detection 2 s CHARGE TERMINATION DETECTION Deglitch time for charge termination BAD ADAPTER DETECTION tINT BATTERY RECHARGE THRESHOLD V(SCOUT) decreasing below threshold, tFALL = 100 ns, 10-mV overdrive Deglitch time 130 ms 262 ms 30 ms 140 ms BATTERY DETECTION tDETECT Battery detection time SLEEP COMPARATOR Deglitch time for VBUS rising above V(SLP) + V(SLP_EXIT) Rising voltage, 2-mV overdrive, tRISE = 100 ns UNDERVOLTAGE LOCKOUT (UVLO) Power up delay PROTECTION t32S 32 second watchdog (WD) timer 32 Second or HOST mode 15 t15M 15 minute safety timer 15 Minute mode 12 Copyright © 2010–2016, Texas Instruments Incorporated 32 40 s 15 m Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 11 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 8.7 Typical Characteristics Using circuit shown in Figure 25, TA = 25°C, unless otherwise specified. VSW 2 V/div VSW 2 V/div IL 0.5 A/div IL 0.5 A/div 100 nS/div 2 ms/div VBUS = 5V, VBAT = 3.5V Charge Mode Overload Operation VBUS = 5 V, ICHG = 1550 mA VBAT = 2.6 V, Voreg = 4.2 V, Figure 2. PWM Charging Waveforms Figure 1. Cycle by Cycle Current Limiting in Charge Mode VSW 5 V/div VBUS 2 V/div VSW 2 V/div IBUS 20 mA/div IBAT 200 mA/div 500 mS/div 10 ms/div VBUS = 5 V at 8 mA, ICHG = 550 mA VBAT = 3.2V, Iin_limit = 100 mA, Vin = 5 V, ICHG = 1550mA Figure 3. Poor Source Detection VBAT = 3. 2V, No Input Current Limit, Figure 4. Charge Current Ramp Up VBUS 1 V/div OTG 2 V/div 15 Minute Mode 32 S Mode IBUS 0.2 A/div IBAT 0.1 A/div Write Command 0.5 mS/div 1 S/div VBUS = 5 V, VBAT = 3.1V, Iin_limit = 100/500 mA, (OTG Control, 15 Minute Mode), Iin_limit = 100 mA (I2C Control, 32 Second Mode) Figure 5. Input Current Control (bq24153A/8) 12 Submit Documentation Feedback VBUS = 5 V at 500 mA, VBAT = 3.5V, ICHG = 1550 mA, VIN_DPM = 4.52 V space Figure 6. VIN Based DPM Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Typical Characteristics (continued) 94 93 VBUS 2 V/div Vbat = 4.2 V 92 Vbat = 3.6 V 91 Efficiency - % 90 89 VPMID 200 mV/div, 5.02 V Offset 88 VSW 5 V/div 87 86 85 Vbat = 3 V 84 IBUS 0.2 A/div 83 82 81 5 mS/div 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Charge Current - A 1.1 1.2 1.3 1.4 1.5 VBUS = 5.05 V, VBAT = 3.5V, RLOAD (at VBUS) = 1kΩ to 0.5Ω Figure 8. VBUS Overload Waveforms (BOOST Mode) Figure 7. Charger Efficiency 95 VBUS 0.5 V/div, 4.5 V Offset 90 Efficiency (%) OTG 2 V/div VSW 5 V/div 85 80 VBAT = 2.7 V 75 VBAT = 3.6 V IL 0.5 A/div VBAT = 4.2 V 70 0 50 100 150 200 Load Current at VBUS (mA) 10 mS/div space VBUS = 4.5 V (Charge Mode) / 5.1 V (Boost Mode), VBAT = 3.5V, IIN_LIM = 500 mA, (32S mode) Figure 10. BOOST Efficiency Figure 9. BOOST to Charge Mode Transition (OTG Control) 5.09 5.08 IBUS = 200 mA 5.08 5.07 5.07 5.06 IBUS = 50 mA VBUS VBUS - V 5.06 5.05 5.04 5.05 5.04 IBUS = 100 mA 5.03 5.03 5.02 5.02 VBAT = 2.7 V 5.01 VBAT = 3.6 V VBAT = 4.2 V 5 5.01 2.6 2.8 3 3.2 3.4 3.6 3.8 4 VBAT - V Figure 11. Line Regulation for BOOST Copyright © 2010–2016, Texas Instruments Incorporated 4.2 0 50 100 150 200 Load Current at VBUS (mA) Figure 12. Line Regulation for Boost Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 13 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 9 Detailed Description 9.1 Overview For a current restricted power source, such as a USB host or hub, a high efficiency converter is critical to fully use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power loss and better thermal management than a linear charger. The bq24153A/8/9 are highly integrated synchronous switch-mode chargers, featuring integrated FETs and small external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or Lipolymer battery pack. Furthermore, bq24153A/8 also has bi-directional operation to achieve boost function for USB OTG support. The bq24153A/8 have three operation modes: charge mode, boost mode, and high impedance mode, while the bq24156A/9 only has charge mode and high impedance mode. In charge mode, the IC supports a precision Liion or Li-polymer charging system for single-cell applications. In boost mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode, the IC stops charging or boosting and operates in a mode with very low current from VBUS or battery, to effectively reduce the power consumption when the portable device is in standby mode. Through I2C communication with a host, referred to as "HOST or 32-second" control/mode, the IC achieves smooth transition among the different operation modes. Even when no I2C communication is available, the IC starts a 15 minute saftey timer and enters "15-minute" (default) mode. During 15-minute operation, the charger will still charge the battery but using each register's default values. 14 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 9.2 Functional Block Diagram PMID bq24153A/6A/8/9 PMID V PMID PMID NMOS VBUS NMOS SW VBUS VBUS SW Q2 Q1 VREF 1 OSC Charge Pump - PWM Controller CBC Current Limiting Q3 I LIMIT - - I IN _ LIMIT - T CF + TJ - V BUS + V UVLO - V BUS + V IN(MIN) - VBUS + V OVP_IN - TJ + VOUT + V OVP - V CSIN + - CSIN IOCHARGE VREF I SHORT PWM _ CHG VBUS UVLO LINEAR Poor Input Source Thermal Shutdown * _CHG VREF REFERNCES & BIAS VBUS OVP - T SHTDWN CSOUT V OREG - + V IN _ DPM V OUT + + SW NMOS CHARGE CONTROL TIMER and DISPLAY LOGIC VREF BOOT VREF 1 V PMID VOUT Battery OVP STAT V BAT VBUS VOREG - VRCH PGND PGND VOUT VOUT VCSIN I TERM + - * Sleep CD + - + - * Recharge * PGND VBAT + VSHORT - OTG (bq 24153 /8) SLRST(bq24156) Termination ( I2 C Control ) Decoder DAC SCL SDA Charge * PWMMode * Signal Deglitched Copyright © 2016, Texas Intruments Incorporated Figure 13. Function Block Diagram of bq2415x in Charge Mode Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 15 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Functional Block Diagram (continued) PMID bq24153A/8 PMID V PMID PMID NMOS VBUS NMOS SW SW SW V BUS VBUS Q2 Q1 VREF 1 Charge Pump OSC PWM Controller CBC Current Limiting Q3 PFM Mode I BO - + + VBUS_B + I BLIMIT V BUS + - TJ + TSHTDWN - VOUT + VBATMAX - 75 mA - VREF REFERNCES & BIAS PWM _ BOOST V BUSOVP NMOS VBUS OVP VREF BOOT VREF 1 VPMID CSIN Thermal Shutdown * Battery OVP V OUT CHARGE CONTROL, TIMER and DISPLAY LOGIC CSOUT STAT CD PGND PGND V BAT + VBATMIN - * * Low Battery OTG ( I2 C Control) Decoder DAC Signal Deglitched PGND SCL SDA Copyright © 2016, Texas Intruments Incorporated Figure 14. Function Block Diagram of bq2415x in Boost Mode 16 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 9.3 Feature Description 9.3.1 Input Voltage Protection 9.3.1.1 Input Overvoltage Protection The IC provides a built-in input overvoltage protection to protect the device and other components against damage if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge process resumes. 9.3.1.2 Bad Adaptor Detection/Rejection Although not shown in Figure 26, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30ms, the adaptor is good and the charge process begins. Otherwise, if the VBUS drops below VIN(MIN), a bad adaptor is detected. Then, the IC disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag (B2 - B0 = 011 for Register 00H). After a delay of TINT, the IC repeats the adaptor detection process, as shown in Figure 15 and Figure 16. Adpator V BUS VBUS ISHORT (30 mA) Adaptor Detection Control VIN_GOOD Deglitch 30ms PGND GND START VIN VIN(MIN) VIN_POOR Delay TINT Figure 15. Bad Adaptor Detection Circuit Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 17 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Feature Description (continued) Charge Command (Host Control or VBUS Ramps Up) Delay 10mS Enable Adaptor Detection Start 30ms Timer Enable Input Current Sink (30mA, to GND) No VBUS>VIN(MIN)? No Yes 30ms Timer Expired? Yes Bad Adaptor Detected Good Adaptor Detected Pulsing STAT Pin Set Bad Adaptor Flag Disable Adaptor Detection Charge Start Enable VIN Based DPM Delay TINT (2 Seconds) Figure 16. Bad Adaptor Detection Scheme Flow Chart 9.3.1.3 Sleep Mode The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold, VCSOUT+VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and PWM are turned off. 9.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold) During the charging process, if the input power source is not able to support the programmed or default charging current, the VBUS voltage will decrease. Once the VBUS drops to VIN_DPM (default 4.52V), the charge current begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is lower than the set value and the special charger bit is set (B4 in Register 05H). This feature makes the IC compatible with adapters having different current capabilities. 9.3.2 Battery Protection 9.3.2.1 Output Overvoltage Protection The IC provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge process resumes. 18 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Feature Description (continued) 9.3.2.2 Battery Short Protection During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the charger operates in short circuit mode with a lower charge rate of ISHORT. 9.3.2.3 Battery Detection at Power Up in 15-minute Mode (bq24153A/6A only) bq24153A/6A also have a unique battery detection scheme during the start up of the charger. At VBUS power up, if the timer is in 15-minute mode, bq24153A/6A will start a 262ms timer when exiting from short circuit mode to PWM charge mode. If the battery voltage is charged above the recharge threshold (VOREG-VRCH) when the 262ms timer expired, bq2153A/6A will not consider the battery present; then stop charging, and go to high impedance mode immediately. However, if the battery voltage is still below the recharge threshold when the 262ms timer expires, the charging process will continue as normal battery charging process. bq24158/9 simply begin regulating the output voltage to their default values (3.54V) at power up while in 15minute mode. 9.3.2.4 Battery Detection in Host Mode For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably detect insertion or removal of battery packs. During the normal charging process with host control, once the voltage at the CSOUT pin is above the battery recharge threshold, VOREG - VRCH, and the termination charge current is detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT, (262 ms typical) then checks the battery voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery is present. On the other hand, if the battery voltage is below the battery recharge threshold, the battery is absent. Under this condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes after a delay of TINT. This function ensures that the charge parameters are reset whenever the battery is replaced. 9.3.3 15-Minute Safety Timer and 32-second Watchdog Timer in Charge Mode Once a good adapter and good battery are attached, the IC starts the 15-minute saftey timer (t15min) that can be disabled by any write-action performed by host through I2C interface. Once the 15-minute timer is disabled, a 32second watchdog timer (t32sec) is automatically started. The 32-second timer can be reset by the host using I2C interface. Writing “1” to reset the TMR_RST bit in the control register will reset the 32-second timer and TMR_RST is automatically set to “0” after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge parameters are reset to default values. Then the 15-minute timer starts and the charge resumes in 15-minute mode. During normal charging process, the IC is usually in 32-second mode with host control and 15-minute mode without host control using I2C interface. The above process repeats until the battery is fully charged. If the 15minute timer expires, the IC turns off the charge, enunciates FAULT on the STATx bits of status register, and sends the 128μs interrupt pulse. This function prevents battery over charge if the host fails to reset the safety timer. The 15-minute charge, with default parameters, allows time for a discharged battery to charge sufficiently to be able to power the host and start communication. The safety timer flow chart is shown in Figure 17. Fault condition is cleared by POR and fault status bits can only be updated after the status bits are read by the host. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 19 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Feature Description (continued) Charge Start Start T15 min Timer Reset Charge Parameters Yes No T 32 sec Expired ? Start T32 sec Stop T15 min No Yes Charge 2 T 15 min Active ? Yes Any I C Write Action ? No T 15 min Expired ? No Host Should Reset T 32 sec Timer Yes Timer Fault Figure 17. Timer Flow Chart for bq24153A/6A/8/9 9.3.4 USB Friendly Power Up Prior to POR, if the host continues to write the TMR_RST bit to 1, to stay in 32-second mode, then at POR, the charger enters normal charge mode (using the desired control bits). If not in 32-second mode at POR, the charge will operate with default bit values, in 15 minute mode, until the host updates the control registers. If the battery voltage is above the VLOWV threshold while in 15 minute mode, the charger will be in the high impedance state. The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating USB spec and over-charging any of the Li-Ion chemistries, while the host has lost communication. The input current limiting is described below. 9.3.5 Input Current Limiting at Power Up The input current sensing circuit and control loop are integrated into the IC. When operating in 15-minute mode, for bq24153A/8, the OTG pin logic level sets the input current limit to 100mA for a logic low and 500mA for a logic high, whereas the bq24156A/9 defaults to 500mA. In 32 second mode, the input current limit is set by the programmed control bits in register 01H. 20 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 9.4 Device Functional Modes 9.4.1 Charge Mode Operation Power Up V BUS > V UVLO V POR Load I 2 C Registers with Default Value CSOUT < V LOWV High Impedance Mode or Host No Controlled Operation Mode Yes Reset and Start 15-M inute T imer Disable Charge /CE = LOW /CE = HIGH Charge Configure Mode Any Charge State Disable Charge Wait Mode Delay TINT Indicate Power not Good Yes No Enable I SHORT V CSOPUT V OREG -V RCH ? Indicate DONE No Yes Charge Complete V CSOUT < V OREG VRCH ? High Impedance Mode Yes Figure 18. Operational Flow Chart of bq2415x in Charge Mode 9.4.1.1 Charge Profile Once a good battery with voltage below the recharge threshold has been inserted and a good adapter is attached, the bq2415x enters charge mode. In charge mode, the IC has five control loops to regulate input voltage, input current, charge current, charge voltage and device junction temperature. During the charging process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. (a) indicates a typical charge profile without input current regulation loop. It is the traditional CC/CV charge curve, while (b) shows a typical charge profile when input current limiting loop is dominant during the constant current mode. In this case, the charge current is higher than the input current so the charge process is faster than the linear chargers. For bq24153A/6A/8/9, the input voltage threshold for DPM loop, input current limits, the charge current, termination current, and charge voltage are all programmable using I2C interface. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 21 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Device Functional Modes (continued) Precharge Phase Current Regulation Phase Voltage Regulation Phase Regulation Voltage Regulation Current Charge Voltage V SHORT Charge Current Termination I SHORT Precharge (Linear Charge) Precharge Phase Fast Charge (PWM Charge) (a) Current Regulation Phase Voltage Regulation Phase Regulation voltage Charge Voltage VSHORT Charge Current Termination I SHORT Precharge (Linear Charge) Fast Charge (PWM Charge) (b) Figure 19. Typical Charging Profile of bq24153A/6A/8/9 for (a) without Input Current Limit, and (b) with Input Current Limit 22 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Device Functional Modes (continued) 9.4.2 PWM Controller in Charge Mode The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation network used for both continuous and discontinuous current conduction operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to 99.5% duty cycles. The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side. The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET (Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2. Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used when the current of the low-side FET is greater than 100mA to minimize power losses. 9.4.3 Battery Charging Process At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT. The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. Once the battery voltage reaches the regulation voltage, VOREG, the charge current is tapered down as shown in . The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. In HOST mode, the regulation voltage is adjustable (3.5V to 4.44V) and is programmed through I2C interface. In 15minute mode, the regulation voltage is fixed at 3.54V. The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the normal charging process with HOST control, once the voltage at the CSOUT pin is above the battery recharge threshold, VOREG - VRCH for the 32-ms (typical) deglitch period, and the termination charge current ITERM is detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT (262ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not occur because the battery was removed. After 40ms (typical) for synchronization purposes of the EOC state and the counter, the status bit and pin are updated to indicate charging has completed. The termination current level is programmable. To disable the charge current termination, the host can set the charge termination bit (I_Term) of charge control register to 0, refer to I2C section for detail. A • • • new charge cycle is initiated when one of the following conditions is detected: The battery voltage falls below the V(OREG) – V(RCH) threshold. VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold. CE bit toggle or RESET bit is set (Host controlled) 9.4.4 Thermal Regulation and Protection To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF. The charge current is reduced to zero when the junction temperature increases approximately 10°C above TCF. In any state, if TJ exceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and all timers are frozen. Charging resumes when TJ falls below TSHTDWN by approximately 10°C. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 23 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Device Functional Modes (continued) 9.4.5 Charge Status Output, STAT Pin The STAT pin is used to indicate operation conditions for bq24153A/6A/8/9. STAT is pulled low during charging when EN_STAT bit in control register (00H) is set to “1”. Under other conditions, STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED or communicate to the host processor. Table 1. STAT Pin Summary CHARGE STATE STAT Charge in progress and EN_STAT=1 Low Other normal conditions Open-drain Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source, VBUS UVLO, no battery, thermal shutdown 128-μs pulse, then open-drain Boost mode faults (bq24153A/8 only): Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal shutdown 128-μs pulse, then open-drain 9.4.6 Control Bits in Charge Mode 9.4.6.1 CE Bit (Charge Mode) The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge. 9.4.6.2 RESET Bit The RESET bit in the control register is used to reset all the charge parameters. Writing ‘1” to the RESET bit will reset all the charge parameters to default values except the safety limit register, and RESET bit is automatically cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge starts and it is not recommended to set the RESET bit while charging or boosting are in progress. 9.4.6.3 OPA_Mode Bit OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in boost mode. Table 2. Operation Mode Summary OPA_MODE HZ_MODE OPERATION MODE 0 0 Charge (no fault) Charge configure (fault, Vbus > UVLO) High impedance (Vbus < UVLO) 1(bq24153A/8 only) 0 Boost (no faults) Any fault go to charge configure mode X 1 High impedance 9.4.7 Control Pins in Charge Mode 9.4.7.1 CD Pin (Charge Disable) The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode. 24 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 9.4.7.2 SLRST Pin (Safety Limit Register 06H Reset, bq24156A/9 only) The safety limit registers provide a means to limit both the maximum charge current and maximum battery regulation voltage at POR regardless of subsequent attempts to increase them via I2C. When the SLRST pin is low, bq24156A/9 will reset all the safety limits to default values, regardless of the write actions to safety limits registers (06H). When the SLRST pin is high, the bq24156A/9 can program the safety limit register until any write action to other registers locks the programmed safety limits. 9.4.8 BOOST Mode Operation (bq24153A/8 only) In 32 second mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the operation mode bit (OPA_MODE) is set to 1, bq24153A/8 operates in boost mode and delivers the power to VBUS from the battery. In normal boost mode, bq24153A/8 converts the battery voltage to VBUS-B (about 5.05V) and delivers a current as much as IBO (about 200mA) to support other USB OTG devices connected to the USB connector. 9.4.8.1 PWM Controller in Boost Mode Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency voltagemode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range. In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses. 9.4.8.2 Boost Start Up To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up. 9.4.8.3 PFM Mode at Light Load In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency. During boosting, the PWM converter is turned off once the inductor current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM and PFM mode. 9.4.8.4 Safety Timer in Boost Mode At the beginning of boost operation, the IC starts a 32-second timer that is reset by the host using the I2C interface. Writing “1” to reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is automatically set to “0” after the 32-second timer is reset. Once the 32-second timer expires, the IC turns off the boost converter, enunciates the fault pulse from the STAT pin and sets fault status bits in the status register. The fault condition is cleared by POR or host control. 9.4.8.5 Protection in Boost Mode 9.4.8.5.1 Output Overvoltage Protection The IC provides a built-in over-voltage protection to protect the device and other components against damage if the VBUS voltage goes too high. When an over-voltage condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. Once VBUS drops to the normal level, the boost starts after host sets OPA_MODE to “1” or OTG pin stays in active status. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 25 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 9.4.8.5.2 Output Overload Protection The IC provides a built-in over-load protection to prevent the device and battery from damage when VBUS is over loaded. Once the over load condition is detected, Q1 operates in linear mode to limit the output current. If the over load condition lasts for more than 30ms, the over-load fault is detected. When an over-load condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out fault pulse in STAT pin. The boost will not start until the host clears the fault register. 9.4.8.5.3 Battery Overvoltage Protection During boosting, when the battery voltage is above the battery over voltage threshold, VBATMAX, or below the minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out fault pulse in STAT pin. Once the battery voltage goes above VBATMIN, the boost will start after the host sets OPA_MODE to “1” or OTG pin stays in active status. 9.4.8.6 STAT Pin in Boost Mode During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-μs pulse is sent out to notify the host. 9.4.9 High Impedance (HI-Z) Mode In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the CD pin high causes the charger to enter Hi-Z mode. When in 15-minute mode and the CD pin is low, the charger automatically enters Hi-Z mode if 1. VBUS > UVLO and a battery with VBAT > VLOWV is inserted, or 2. VBUS falls below UVLO. Taking the CD pin high while in 15-minute mode resets the 15 minute timer. When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is set to “1” and OTG pin is not in active status. Once the bq24153A/6A/8/9 enters Hi-Z mode and the CD pin is low, a low power 32-second timer is enabled when the battery voltage is below V(LOWV) to monitor if the host control is available or not. If the low power 32-second timer expires, the IC operates in 15-minute mode and the low power 32 second timer is disabled. In order to exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO and the HOST must write a "0" to the HZ-MODE control bit. 9.5 Programming 9.5.1 Serial Interface Description I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that SDA changes while SCL is LOW. The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HSmode. The bq24153A/6A/8/9 device supports 7-bit addressing only. The device 7-bit address is defined as ‘1101011’ (6BH) for bq24153A, and ‘1101010’ (6AH) for bq24156A/8/9. 26 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Programming (continued) 9.5.1.1 F/S Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 20. All I2C-compatible devices should recognize a start condition. DATA CLK S P START Condition STOP Condition Figure 20. START and STOP Condition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 21). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 21) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 21. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not listed in this section will result in FFh being read out. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 27 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Programming (continued) Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 9 8 2 Clock Pulse for Acknowledgement START Condition Figure 22. Acknowledge on the I2C Bus™ Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA Acknowledgement Signal From Slave MSB Sr Address R/W SCL S or Sr ACK ACK Sr or P Clock Line Held Low While Interrupts are Serviced Figure 23. Bus Protocol 9.5.1.2 H/S Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not listed in this section results in FFh being read out. 28 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Programming (continued) I2C Update Sequence 9.5.1.3 The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the acknowledge signal that follows the LSB byte. For the first update, the IC requires a start condition, a valid I2C address, a register address byte, a data byte. For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is received, the IC releases the I2C bus, and awaits a new start conditions. S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A P Data Transferred (n Bytes + Acknowledge) ‘0’ (Write) From master to IC A A From IC to master S Sr P = Acknowledge (SDA LOW) = Not acknowledge (SDA HIGH) = START condition = Repeated START condition = STOP condition (a) F/S-Mode F/S-Mode S F/S-Mode HS-Mode HS-MASTER CODE A Sr SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A/A Data Transferred (n Bytes + Acknowledge) ‘0’ (write) P HS-Mode Continues Sr Slave A. (b) HS- Mode Figure 24. Data Transfer Format in F/S Mode and H/S Mode 9.5.1.4 Slave Address Byte MSB X LSB 1 1 0 1 0 1 1 The slave address byte is the first byte received following the START condition from the master device. 9.5.1.5 Register Address Byte MSB 0 LSB 0 0 0 0 D2 D1 D0 Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only read access. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 29 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 9.6 Register Maps 9.6.1 Status/Control Register [Memory Location: 00, Reset State: x1xx 0xxx] Table 3. Status/Control Register (Read/Write) Memory Location: 00, Reset State: x1xx 0xxx BIT NAME READ/WRITE FUNCTION B7 (MSB) TMR_RST/OTG Read/Write Write: TMR_RST function, write "1" to reset the safety timer (auto clear) Read: OTG pin status, (for bq24153A/8 only) 0-OTG pin at Low level, 1-OTG pin at High level SLRST pin status (for bq2156A/9 only), 0-SLRST pin at LOW level, 1-SLRST pin at HIGH level. B6 EN_STAT Read/Write 0-Disable STAT pin function, 1-Enable STAT pin function (default 1) B5 STAT2 Read Only B4 STAT1 Read Only B3 BOOST Read Only B2 FAULT_3 Read Only B1 FAULT_2 Read Only B0 (LSB) FAULT_1 Read Only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault 1-Boost mode, 0-Not in boost mode, for bq24153A/8 only; NA–for bq24156A/9. Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or VBUS V(UVLO), 2) the digital reset threshold (typ. 2.4V) if VBUS < V(UVLO) or 3) SLRST (pin D4, for bq24156A/9 only) goes to logic ‘0’. After reset, the maximum values for battery regulation voltage and charge current can be programmed until any writing to other register locks the safety limits. Programmed values exclude higher values from memory locations 02 (battery regulation voltage), and from memory location 04 (Fast charge current). If host accesses (write command) to some other register before Safety limit register, the safety default values are used. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 33 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The bq24153A/6A/8/9 is a compact, flexible, high-efficiency, USB-friendly, switch-mode charge management solution for single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The devices integrate a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a small DSBGA package. The charge parameters can be programmed through an I2C interface. 10.2 Typical Application VBUS = 5 V, ICHARGE = 1250 mA, VBAT = 3.5 V to 4.44 V (Adjustable). LO 1.0 mH VBUS VBUS CIN VBAT SW CO1 CBOOT U1 bq24153A/8 1 mF RSNS CO2 22 mF 33 mF 33 nF C IN 4.7 mF BOOT PMID VAUX PACK+ CCSIN PGND + 0.1 mF CSIN 10 kW 10 kW 10 kW 10 kW I 2C BUS PACK– CSOUT SCL SCL SDA STAT SDA STAT OTG 10 kW CCSOUT VREF OTG CD CD 0.1 mF CVREF 1 mF 10 kW HOST Copyright © 2016, Texas Intruments Incorporated 2 Figure 25. I C Controlled 1-Cell USB Charger Application Circuit with USB OTG Support. 10.2.1 Design Requirements Use the following typical application design procedure to select external components values for the bq24153A/6A/8/9 device. Table 10. Design Parameters SPECIFICATIONS TEST CONDITIONS Input DC voltage, VIN Input voltage from AC adapter input Input current Maximum input current from AC adapter input Charge current Battery charge current Output regulation voltage Voltage applied to VBAT Operating junction temperature range, TJ 34 MIN TYP UNIT 5 6 V 0.1 0.1 to 0.5 1.5 A 0.325 0.7 1.55 A 0 0.3 to 4.2 4.44 V 125 °C 0 Submit Documentation Feedback MAX 4 Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 10.2.2 Detailed Design Procedure 10.2.2.1 Systems Design Specifications • VBUS = 5 V • VBAT = 4.2 V (1-Cell) • I(charge) = 1.25 A • Inductor ripple current = 30% of fast charge current 1. Determine the inductor value (LOUT) for the specified charge current ripple: VBAT ´ (VBUS - VBAT) VBUS ´ f ´ D IL L OUT = , the worst case is when battery voltage is as close as to half of the input voltage. LOUT = 2.5 ´ (5 - 2.5) 5 ´ (3 ´ 106 ) ´ 1.25 ´ 0.3 (1) LOUT = 1.11 μH Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor: DIL = VBAT ´ (VBUS - VBAT) VBUS ´ f ´ LOUT (2) 2.5 ´ (5 - 2.5) DIL = 5 ´ (3 ´ 106 ) ´ (1 ´ 10-6 ) (3) ΔIL = 0.42 A Calculate the maximum output current: DIL ILPK = IOUT + 2 (4) 0.42 ILPK = 1.25 + 2 (5) ILPK = 1.46 A Select 2.5mm by 2mm 1-μH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers are shown as following. Table 11. Inductor Part Numbers (1) PART NUMBER INDUCTANCE SIZE MANUFACTURER LQM2HPN1R0MJ0 1 μH 2.5 x 2.0 mm Murata MIPS2520D1R0 1 μH 2.5 x 2.0 mm FDK MDT2520-CN1R0M 1 μH 2.5 x 2.0 mm TOKO CP1008 1 μH 2.5 x 2.0 mm Inter-Technical (1) See Third-Party Products discalimer Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 35 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 2. Determine the output capacitor value (COUT) using 40 kHz as the resonant frequency: 1 fo = 2p ´ LOUT ´ COUT (6) 1 COUT = 4p2 ´ f02 ´ LOUT 1 COUT = (7) 4p2 ´ (40 ´ 103 )2 ´ (1 ´ 10-6 ) (8) COUT = 15.8 μF Select two 0603 X5R 6.3V 10-μF ceramic capacitors in parallel i.e., Murata GRM188R60J106M. 3. Determine the sense resistor using the following equation: V(RSNS) R(SNS) = I(CHARGE) (9) The maximum sense voltage across the sense resistor is 85 mV. In order to get a better current regulation accuracy, V(RSNS) should equal 85mV, and calculate the value for the sense resistor. 85mV R(SNS) = 1.25A (10) R(SNS) = 68 mΩ This is a standard value. If it is not a standard value, then choose the next close value and calculate the real charge current. Calculate the power dissipation on the sense resistor: P(RSNS) = I(CHARGE) 2 × R(SNS) P(RSNS) = 1.252 × 0.068 P(RSNS) = 0.106 W Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068. 4. Measured efficiency and total power loss with different inductors are shown in Figure 26 and Figure 27. SW node and inductor current waveform are shown in Figure 2. 90 800 89 700 600 87 Loss (mW) Efficiency (%) 88 86 85 84 82 500 600 700 800 400 300 FDK TOKO Inter-Technical muRata 83 500 FDK TOKO Inter-Technical muRata 200 100 900 1000 1100 1200 1300 500 600 700 Charge Current (mA) TA = 25°C VBUS = 5 V VBAT = 3 V Figure 26. Measured Battery Charge Efficiency 36 Submit Documentation Feedback 800 900 1000 1100 1200 1300 Charge Current (mA) TA = 25°C VBUS = 5 V VBAT = 3 V Figure 27. Measured Battery Charge Loss Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 10.2.2.2 Charge Current Sensing Resistor Selection Guidelines Both the termination current range and charge current range depend on the sensing resistor (RSNS). The termination current step (IOTERM_STEP) can be calculated using Equation 11: IO(TERM_STEP) = VI(TERM0) R(SNS) (11) Table 12 shows the termination current settings for three sensing resistors. Table 12. Termination Current Settings for 55-mΩ, 68-mΩ, 100-mΩ Sense Resistors BIT VI(TERM) (mV) I(TERM) (mA) R(SNS) = 55mΩ I(TERM) (mA) R(SNS) = 68mΩ I(TERM) (mA) R(SNS) = 100mΩ VI(TERM2) 13.6 247 200 136 VI(TERM1) 6.8 124 100 68 VI(TERM0) 3.4 62 50 34 Offset 3.4 62 50 34 For example, with a 68-mΩ sense resistor, V(ITERM2)=1, V(ITERM1)=0, and V(ITERM0)=1, ITERM = [ (13.6mV x 1) + (6.8mV x 0) + (3.4mV x 1) + 3.4mV ] / 68mΩ = 200mA + 0 + 50mA + 50mA = 300mA. The charge current step (IO(CHARGE_STEP)) is calculated using Equation 12: VI(CHRG0) IO(CHARGE_STEP) = R(SNS) (12) Table 13 shows the charge current settings for three sensing resistors. Table 13. Charge Current Settings for 55-mΩ, 68-mΩ and 100-mΩ Sense Resistors BIT IO(CHARGE) (mA) R(SNS) = 55mΩ VI(REG) (mV) IO(CHARGE) (mA) R(SNS) = 68mΩ IO(CHARGE) (mA) R(SNS) = 100mΩ bq24156A bq24159 bq24153A bq24158 bq24156A bq24159 bq24153A bq24158 bq24156A bq24159 bq24153A bq24158 bq24156A bq24159 bq24153A bq24158 VI(CHRG3) 54.4 27.2 989 495 800 400 544 272 VI(CHRG2) 27.2 13.6 495 247 400 200 272 136 VI(CHRG1) 13.6 6.8 247 124 200 100 136 68 VI(CHRG0) 6.8 n/a 124 n/a 100 n/a 68 n/a Offset 37.4 37.4 680 680 550 550 374 374 Using bq24156A as an example, with a 68-mΩ sense resistor, V(CHRG3)=1, V(CHRG2)=0, V(ICHRG1)=0, and V(ICHRG0)=1, ITERM = [ (54.4mV x 1) + (27.2mV x 0) + (13.6mV x 0) + (6.8mV x 1) + 37.4mV ] / 68mΩ = 800mA + 0 + 0 + 100mA = 900mA. 10.2.2.3 Output Inductor and Capacitance Selection Guidelines The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs when the LC resonant frequency, fo, is approximately 40 kHz (20 kHz to 80 kHz). Equation 13 can be used to calculate the value of the output inductor, LOUT, and output capacitor, COUT. fo = 1 2p ´ LOUT ´ COUT (13) To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 μF and 47 μF is recommended for COUT, see the application section for components selection. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 37 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 10.2.3 Application Curves Using circuit shown in Figure 25, TA = 25°C, unless otherwise specified. VBUS 2 V/div VBAT 2 V/div VSW 5 V/div VSW 5 V/div IBAT 0.5 A/div IBAT 0.5 A/div Battery Inserted Battery Removed 1 S/div 10 ms/div VBUS = 0-5V, VBAT = 3.5V, Iin_limit = 500mA, ICHG = 550mA, Voreg = 4.2V 32S mode VBUS = 5 V, VBAT = 3.4V, Iin_limit = 500 mA (32s Mode) Figure 29. Battery Insertion/Removal Figure 28. Adapter Insertion VBUS 5 V/div VBUS 4 V/div VBAT 2 V/div VBAT 2 V/div VSW 5 V/div IBUS 50 mA/div IBUS 100 mA/div 100 mS/div VBUS = 5V, 100 ms/div VBUS = 5V, No Battery Connected Figure 30. Battery Detection at Power Up (bq24153A/6A) VBUS 10 mV/div, 5.05 V Offset No Battery Connected Figure 31. Battery Detection at Power Up (bq24158/9) VBUS 100 mV/div, 5.05 V Offset VBAT 10 mV/div, 3.5 V Offset VBAT 100 mV/div, 3.5 V Offset VSW 2V/div VSW 2 V/div IL 100 mA/div IL 0.2 A/div 5 mS/div 100 nS/div VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA Figure 32. BOOST Waveform (PWM Mode) 38 Submit Documentation Feedback VBUS = 5.05 V, VBAT = 3.5V, IBUS = 42 mA Figure 33. BOOST Waveform (PFM Mode) Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 VBUS 100 mV/div 5.05 V Offset VBUS 100 mV/div, 5.05 V Offset VBAT 0.2 V/div 3.5 V Offset VBAT 0.2 V/div, 3.5 V Offset VSW 5 V/div VSW 5 V/div IBAT 0.1 A/div IBAT 0.1 A/div 100 mS/div 100 μs/div VBUS = 5.05 V, VBAT = 3.5V, VBUS = 5.05 V, IBUS = 0-217 mA VBAT = 3.5V, IBUS = 217 mA Figure 35. Load Step Down Response (BOOST Mode) Figure 34. Load Step Up Response (BOOST Mode) 10.3 System Example VBUS = 5 V, ICHARGE = 1550 mA, Vbat = 3.5 V to 4.44 V (adjustable). LO 1.0 mH VBUS VBUS CIN SW C IN 4.7 mF 33 mF BOOT PACK+ + CCSIN PGND VAUX CO2 22 mF 33 nF PMID VBAT CO1 CBOOT U1 bq24156A/9 1 mF RSNS 0.1 mF CSIN 10 kW 10 kW 10 kW 10 kW SLRST 10 kW 2 I C BUS SCL SCL SDA STAT SDA STAT SLRST CD CD 10 kW PACK– CSOUT CCSOUT VREF CVREF 0.1 mF 1 mF HOST Copyright © 2016, Texas Intruments Incorporated Figure 36. I2C Controlled 1-Cell Charger Application Circuit with External Safety Limit Register Control Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 39 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 11 Power Supply Recommendations 11.1 System Load After Sensing Resistor One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as shown in Figure 37. The input voltage has been converted to a usable system voltage with good efficiency from the input. When the input power is on, it supplies the system load and charges the battery pack at the same time. When the input power is off, the battery pack powers the system directly. SW VBUS L1 VIN + - Isys Isns Rsns bq2415x C1 PMID Ichg + PGND C4 C3 System Load BAT C2 Figure 37. System Load After Sensing Resistor The advantages of system load after sensing resistor: 1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power dissipation. Consequently, the time that the system runs on the battery pack can be maximized. 2. It reduces the number of external path selection components and offers a low-cost solution. 3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current can be limited to a desired value by setting the charge current value. When the system current increases, the charge current drops by the same amount. As a result, no potential over-current or over-heating issues are caused by excessive system load demand. 4. The total input current can be limited to a desired value by setting the input current limit value. USB specifications can be met easily. 5. The supply voltage variation range for the system can be minimized. 6. The input current soft-start can be achieved by the generic soft-start feature of the IC. Design considerations and potential issues: 1. If the system always demands a high current (but lower than the regulation current), the battery charging never terminates. Thus, the battery is always charged, and its lifetime may be reduced. 2. Because the total current regulation threshold is fixed and the system always demands some current, the battery may not be charged with a full-charge rate and thus may lead to a longer charge time. 3. If the system load current is large after the charger has been terminated, the IR drop across the battery impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle. The charger would then terminate due to low charge current. Therefore, the charger would cycle between charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold, resulting in a much slower cycling. 4. In a charger system, the charge current is typically limited to about 30mA, if the sensed battery voltage is below 2V short circuit protection threshold. This results in low power availability at the system bus. If an external supply is connected and the battery is deeply discharged, below the short circuit protection threshold, the charge current is clamped to the short circuit current limit. This then is the current available to the system during the power-up phase. Most systems cannot function with such limited supply current, and the battery supplements the additional power required by the system. Note that the battery pack is already at the depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown. 5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the 40 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 System Load After Sensing Resistor (continued) short circuit current limit, the end-equipment will be operational, but the charging process can be affected depending on the current left to charge the battery pack. Under extreme conditions, the system current is close to the short circuit current levels and the battery may not reach the fast-charge region in a timely manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process. Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the application possible. 6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is clamped by the battery and it cannot operate even if the input power is on. 11.2 System Load Before Sensing Resistor The second circuit is similar to first one; the difference is that the system load is connected before the sense resistor, as shown in Figure 38. Isys SW VBUS Isns L1 VIN + - Rsns Ichg bq2415x C1 PMID + PGND C4 C3 System Load BAT C2 Figure 38. System Load Before Sensing Resistor The advantages of system load before sensing resistor to system load after sensing resistor: 1. The charger controller is based only on the current going through the current-sense resistor. So, the constant current fast charge and termination functions operate without being affected by the system load. This is the major advantage of having the system load connected before the sense resistor. 2. A depleted battery pack can be connected to the charger without the risk of the safety timer expiration caused by high system load. 3. The charger can disable termination and keep the converter running to keep battery fully charged; or let the switcher terminate when the battery is full and then allow the system to run off of the battery through the sense resistor. Design considerations and potential issues: 1. The total current is limited by the IC input current limit, or peak current protection, but not the charge current setting. The charge current does not drop when the system current load increases until the input current limit is reached. This solution is not recommended if the system requires a high current. 2. Efficiency declines when discharging through the sense resistor to the system. 3. No thermal regulation. Therefore, the system design should ensure the maximum junction temperature of the IC is below 125°C during normal operation. Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 41 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 12 Layout 12.1 Layout Guidelines It is important to pay special attention to the PCB layout. The following provides some guidelines: • To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper layout to minimize high frequency current path loop is critical. (See Figure 39.) The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers (do not route the sense leads through a high-current path). (See Figure 40.) • Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths. • The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for smallsignal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue, and having the components segregated minimizes coupling between signals. • The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. • Place 4.7μF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. Place 1μF input capacitor as close to VBUS pin and PGND pin as possible to make high frequency current loop area as small as possible (see Figure 41). 12.1.1 Current Path L1 VBUS SW R1 V BAT High Frequency BAT V IN PMID Current Path PGND C3 C2 C1 Figure 39. High Frequency Current Path 42 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 12.2 Layout Example Charge Current Direction R SNS To Inductor To Capacitor and battery Current Sensing Direction To CSIN and CSOUT pin Figure 40. Sensing Resistor PCB Layout VBUS PMID SW Vin+ 1µF Vin– 4.7µF PGND Figure 41. Input Capacitor Position and PCB Layout Example Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 43 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com 13 Device and Documentation Support 13.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 14. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY bq24153A Click here Click here Click here Click here Click here bq24156A Click here Click here Click here Click here Click here bq24158 Click here Click here Click here Click here Click here bq24159 Click here Click here Click here Click here Click here 13.3 Community Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.4 Trademarks E2E, NanoFree are trademarks of Texas Instruments. I2C is a trademark of NXP B.V. Corporation. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 44 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14.1 Package Summary CHIP SCALE PACKAGE (Top Side Symbol For bq24153A) CHIP SCALE PACKAGE (Top Side Symbol For bq24156A) TIYMLLLLS bq24153A TIYMLLLLS bq24156A 0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code CHIP SCALE PACKAGE (Top Side Symbol For bq24158) CHIP SCALE PACKAGE (Top Side Symbol For bq24159) TIYMLLLLS bq24158 TIYMLLLLS bq24159 Copyright © 2010–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: bq24153A bq24156A bq24158 bq24159 45 bq24153A, bq24156A, bq24159 bq24153A, bq24156A bq24158, bq24159 SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 www.ti.com Package Summary (continued) WCSP PACKAGE (Top View) A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 E1 E2 E3 E4 D E 14.1.1 Chip Scale Packaging Dimensions The bq24153A/6A/8/9 devices are available in a 20-bump chip scale package (YFF, NanoFree™). The package dimensions are: 46 D E Max = 2.17mm Max = 2.03 mm Min = 2.11 mm Min = 1.97 mm Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: bq24153A bq24156A bq24158 bq24159 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ24153AYFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24153A Samples BQ24153AYFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24153A Samples BQ24156AYFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24156A Samples BQ24157YFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BQ24157A Samples BQ24157YFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BQ24157A Samples BQ24158YFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24158 Samples BQ24158YFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24158 Samples BQ24159YFFR ACTIVE DSBGA YFF 20 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24159 Samples BQ24159YFFT ACTIVE DSBGA YFF 20 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24159 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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