bq25040
www.ti.com ...................................................................................................................................................... SLUS910B – MARCH 2009 – REVISED MARCH 2009
1.1A, Single-Input, Single Cell Li-Ion Battery Charger
With 50mA LDO and 2.3A Production Test Support
•
•
FEATURES
1
•
•
•
•
•
•
•
•
30V Input Rating, with Overvoltage Protection
(OVP)
Input Voltage Dynamic Power Management
Feature
50mA Integrated Low Dropout Linear
Regulator (LDO)
1% Charge Voltage Regulation Accuracy
10% Charge Current Accuracy
Single-Input Interface Selects USB 100mA,
500mA or User-Programmable Maximum Input
Current Limit
4.2V at 2.3A Production Test Mode
Thermal Regulation and Thermal Shutdown
Protection for Output Current Control
Soft-Start Feature to Reduce Inrush Current
Status Indication – Power Good and
Charging/Done
Available in Small 2mm × 3mm DFN-10
Package
•
APPLICATIONS
•
•
•
•
•
Mobile Phones
Smart Phones
Portable Media Players
Portable Navigation Devices
Low-Power Handheld Devices
DESCRIPTION
The bq25040 is an integrated Li-ion linear battery charger targeted at space-limited portable applications. It
operates from either a USB port or AC adapter and charges a single cell Li-Ion battery with up to 1.1A of charge
current.
The bq25040 has a single power output that charges the battery. A system load can be placed in parallel with
the battery. The charge current is programmed using the ISET and EN/SET inputs. The input current limit is
programmable to USB100, USB500 or a user programmed current limit up to 1.1A. Additionally, a 4.9V ±3%
50mA LDO is integrated into the IC for supplying low power external circuitry. The single-input interface
(EN/SET) is used to select the charge current and to place the bq25040 into Production Test Mode. In
Production Test Mode, the bq25040 operates as a linear regulator without a battery connected, where the output
is regulated at 4.2V and supplies up to 2.3A to calibrate GSM transceivers.
APPLICATION SCHEMATIC
R2
1 kW
GND
1
IN
8
CHG
DC+
R3
1 kW
9
PG
Adaptor
C1
1mF
ABB
BAT 10
C2
1mF
bq 25040
R1
680 W
2
5
VSS
IFULL
OR
ISET
EN/SET 6
3,7
R2
2 kW
LDO 4
C3
1mF
USB Port
VBUS
GND
D+
D-
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
bq25040
SLUS910B – MARCH 2009 – REVISED MARCH 2009 ...................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases,
an internal control loop monitors the IC junction temperature and reduces the charge current if an internal
temperature threshold is exceeded.
The charger power stage and charge current sense functions are fully integrated. The charger function has
accuracy current and voltage regulation loops, charge status display, and charge termination.
ORDERING INFORMATION
PART NUMBER
(1)
(1)
VBAT(REG)
VOVP
VLDO
MARKING
bq25040DQCR
4.2V
6.9V
4.9V
OAB
bq25040DQCT
4.2V
6.9V
4.9V
OAB
The DQC package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Input voltage
Output voltage
VALUE
UNIT
IN (with respect to VSS)
–0.3 to 30
V
EN/SET, ISET, IFULL (with respect to VSS)
–0.3 to 7
V
BAT, CHG, PG (with respect to VSS)
–0.3 to 7
V
LDO (with respect to VSS)
-0.3 to 7
(2)
V
Input current (Continuous)
IN
1.5
A
Input current (Pulsed)
IN, 20% duty cycle with 10 ms period
2.5
A
Output current (Continuous)
BAT
1.5
A
Output current (Pulsed)
BAT, 20% duty cycle with 10 ms period
2.5
A
Output current (Continuous)
LDO
100
mA
Output sink current
CHG, PG
15
mA
Junction temperature, TJ
–40 to 150
°C
Storage temperature, Tstg
–65 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
If VLDO is greater than VIN, current must be limited to less than 100mA or damage may occur.
DISSIPATION RATINGS (1)
(1)
2
PACKAGE
RθJA
RθJC
10 Pin 2mm × 3mm SON
58.7 °C/W
3.9 °C/W
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. The pad is
connected to the ground plane by a 2x3 via matrix.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
IN voltage range
VIN
IN operating voltage range
MIN
MAX
4.35
26
4.35 (1)
6.7
UNITS
V
IIN
Input current, IN pin (charging)
1.1
A
IIN(PTM)
Input current PTM, IN pin, 20% duty cycle with 10ms period
2.3
A
IO
Output current in charge mode, BAT pin (charging)
1.1
A
IO(PTM)
Output current in PTM, BAT pin, 20% duty cycle with 10 ms period
TJ
Junction Temperature
RISET
Fast-charge current programming resistor
RIFULL
Charge Done threshold
(1)
2.3
A
0
125
°C
475
5360
Ω
1
10
kΩ
Operation with VIN < 5V may result in reduced performance due to dropout operation for LDO and/or charger.
ELECTRICAL CHARACTERISTICS
Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VUVLO
Undervoltage lock-out
VIN: 0V → 4V
3.15
3.30
3.45
V
VHYS(UVLO)
Hysteresis on UVLO
VIN: 4V → 0V
190
240
290
mV
VIN(PG)
Input Power Good detection threshold
VIN(PG) above VBAT
(Input power good if VIN > VBAT + VIN(PG))
VBAT = 3.6V, VIN: 3.5V → 4V
30
75
150
mV
VHYS(INPG)
Hysteresis on VIN(PG)
VBAT = 3.6V, VIN: 4V → 3.5V
18
32
54
mV
tDGL(NO-IN)
Delay time, input power loss to charger
turn-off
Time measured from VIN: 5V → 2.5V,
1µs fall-time
VOVP
Input overvoltage protection threshold
VIN: 5V → 7V
VHYS(OVP)
Hysteresis on OVP
VIN: 7V → 5V
tBLK(OVP)
Input overvoltage blanking time
32
6.7
6.9
ms
7.1
mV
115
µs
500
µs
tREC(OVP)
Input overvoltage recovery time
Time measured from VIN: 11V → 5V
1µs fall-time to CHG = LO, VBAT = 3.5V
VIN(DPM)
Input DPM threshold
VIN Falling, ICHRG reduced to 90%,
USB100 or USB500 Mode
4.38
4.43
4.48
USB100 mode input current limit
USB100 programmed by EN/SET,
RISET > 1.1kΩ , VBAT = 3.5V
90
95
100
USB500 mode input current Limit
USB500 programmed by EN/SET,
RISET > 1.1kΩ , VBAT = 3.5V
380
395
415
RISET= 500Ω → 200Ω, IC latches off after
tDGL(SHORT)
320
IIN
V
100
V
mA
ISET SHORT CIRCUIT TEST
RISET
Continuous Monitor
tDGL(SHORT)
Deglitch time transition from ISET to IC
latched off
ILIM
Current limit with ISET shorted
460
1.5
VISET = 0V, IC latches off after tDGL(SHORT)
1.7
2.0
Ω
ms
2.2
A
1
µA
QUIESCENT CURRENT
IBAT(PDWN)
Battery current into BAT
IIN(STDBY)
Standby current into IN pin
ICC
Active supply current, IN pin
VIN = 0 V
VIN ≤ VOVP
150
VIN = 10V
350
VIN = 6V, no load on BAT pin,
VBAT > VBAT(REG), IC enabled
3
µA
mA
BATTERY CHARGER FAST-CHARGE
VBAT(REG)
Battery charge voltage
4.16
ICHRG
Programmed Output “fast charge” current
range
VBAT(REG) > VBAT > VLOWV, VIN = 5V,
RISET = 475Ω to 5.36kΩ,
User Programmable set by EN/SET
VDO(IN-BAT)
VIN – VBAT
VIN = 4.1V and IBAT = 1A
Output “fast charge” formula
VBAT(REG) > VBAT > VLOWV, VIN = 5 V, User
Programmable set by EN/SET
ICHRG
4.20
100
280
4.24
V
1100
mA
512
mV
KISET/RISET
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ELECTRICAL CHARACTERISTICS (continued)
Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
KISET
TEST CONDITIONS
MIN
TYP
MAX
UNIT
480
530
580
AΩ
VBAT < VLOWV, VIN = 5V,
ICHRG = 250mA to 1100mA
17
20
22
VBAT < VLOWV, VIN = 5V,
ICHRG = 100 mA to 249 mA
16
20
27
2.4
2.5
2.6
Fast charge current factor
PRE-CHARGE AND CHARGE DONE
IPRECHG
Pre-charge current
%ICHG
VLOWV
Pre-charge to fast-charge transition
threshold
tDGL1(LOWV)
Deglitch time on pre-charge to fast-charge
transition
50
µs
tDGL2(LOWV)
Deglitch time on fast-charge to pre-charge
transition
25
ms
IIFULL
Reference current to IFULL programming
resistor
IIFULL%
Charge done current formula
IIFULL% = 0% to 50% of ICHRG
KIFULL
Charge done current factor
VIN = 5V, ICHGDONE = 25mA to 600mA
180
VLDO
LDO Output voltage
VLDO + VDO(LDO) ≤ VIN ≤ VOVP,
ILDO = 0mA to 50mA
ILDO(MAX)
LDO output current limit
VLDO = 0V
VDO(LDO)
LDO Dropout voltage
VIN = 4.5V, ILDO = 50mA
V
80
µA
200
220
Ω/%
4.75
4.90
5.05
V
65
125
185
mA
150
300
mV
4.20
4.284
70
75
RIFULL/KIFULL
%
LDO
PRODUCTION TEST MODE
VBAT(PTM)
Production Test Mode BAT Output Voltage VIN = 5.5V, IBAT = 2A for 4ms pulse
ILIM(PTM)
Production Test Mode Maximum BAT
output current
4.116
2.3
V
A
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
TJ Rising
125
°C
TJ(OFF)
Thermal shutdown temperature
TJ Rising
155
°C
TJ(OFF-HYS)
Thermal shutdown hysteresis
TJ Falling
20
°C
EN/SET INTERFACE
tEN/SET(Latch)
EN/SET latch timer
Timer to lock pulse count
1.5
tEN/SET(OFF)
EN/SET latch timer
Timer to turn off charge current
1.5
ms
tHI(MIN)
High duration on EN/SET
100
700
µs
tLO(MIN)
Low time duration on EN/SET
100
700
µs
V
ms
LOGIC LEVELS ON EN/SET
VIL
Logic LOW input voltage
0
0.4
VIH
Logic HIGH input voltage
1.4
6.0
RPULLDOWN
EN/SET pulldown resistor
See Note
(1)
260
V
kΩ
LOGIC LEVELS ON CHG and PG
VOL
Output LOW voltage
ISINK = 5mA
IIH
Leakage current
VCHG = VPG = 5V
(1)
4
0.425
V
1
µA
No specified low without an external pulldown.
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PIN CONFIGURATION
10-Pin 2mm × 3mm DFN
(TOP VIEW)
IN
1
10
BAT
ISET
2
9
PG
VSS
3
8
CHG
bq25040
LDO
4
7
VSS
IFULL
5
6
EN/SET
PIN FUNCTIONS
PIN
NAME
IN
NO.
1
I/O
DESCRIPTION
I
Input power supply. IN is connected to the external dc supply (ac adapter or USB port). Bypass IN to VSS
with at least a 1µF ceramic capacitor.
ISET
2
I
Current programming input. Connect a resistor from ISET to VSS to program the fast-charge current
when the user programmable mode is selected by EN/SET. If the current limit set by ISET is lower than
the USB500 limit, the current is limited by the ISET setting even in USB500 mode. The resistor range is
between 475Ω and 5.36kΩ to set the current between 100 mA and 1.1 A.
VSS
3, 7
–
Ground terminal. Connect to the thermal pad and the ground plane of the circuit.
LDO
4
O
LDO output. LDO is regulated to 4.9V and drives up to 50mA. Bypass LDO to VSS with at least a 1µF
ceramic capacitor. LDO is enabled when VIN is above the UVLO and less than VOVP. The LDO current is
not limited by the input current limit.
IFULL
5
I
Charge done current programming input. Connect a resistor from IFULL to VSS to program the charge
done threshold. The CHG output goes high-impedance when IBAT falls to the charge done threshold. The
charge done threshold is programmable from 5% to 50% of the fast charge current programmed at ISET.
EN/SET
6
I
One-wire Interface Input. Drive EN/SET with pulses to enable/disable the device and select different
modes. See Table 1 for the data map. EN/SET is pulled to VSS with an internal ~260kΩ resistor.
CHG
8
O
Charge done indicator open-drain output. CHG is pulled low while the device is charging the battery. CHG
goes high impedance when the battery is fully charged and does not indicate subsequent recharge
cycles. CHG is high impedance during fault conditions.
PG
9
O
Power good open-drain output. PG is an open-drain output that pulls to VSS when the input power is
above the battery voltage by 80mV and below the OVP threshold. PG is high impedance when outside
this range.
BAT
10
O
Battery connection output. Connect the battery and the system input to BAT. Bypass BAT to VSS with at
least a 1µF ceramic capacitor. If no battery is installed, the capacitance on the BAT line must be at least
40µF. In Production Test Mode, BAT regulates to 4.2V and supplies up to 2.3A.
-
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the
device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit
board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be
connected to ground at all times.
Thermal PAD
Pad
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BLOCK DIAGRAM
Q1
Q2
BAT
VIN
80mV
+
Charge
Pump
+
VIN(DPM)
TJ(REG)
TJ
+
+
-
ISET
Min
Current
Selector
VBAT(REG)
-
USB
Enable
+
+
USB
Sense
Element
VBAT(PTM)
Charge
Pump
Fastcharge
Precharge
75mA
1.5V
300mV
IFULL
+
VOVP
VIN
+
CHG
CHARGE
CONTROL
Q3
50ms deglitch
for rising and
falling edges
PG
Digital
Decode
EN/SET
Q4
260kW
LDO
Enabled
VIN
Q5
LDO
VSS
+
VREF
6
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TYPICAL APPLICATION CIRCUITS
USB or TA
VBUS
GND
D+
D-
bq25040
C1
1 mF
R1
680 W
IN
BAT
ISET
R2
2 kW
VCHG
R3
1 kW
VSS
R4
1 kW
C2
1 mF
+
ABB
PG
CHG
IFULL
EN/SET
GPIO
VCHG DET
LDO
C2
1 mF
PWRPD
USB DET
VUSBIN
Figure 1. Typical Application Circuit With Battery Always Installed, ICHRG = 780mA, ICHGDONE = 78mA
R3
1 kW
SYSTEM
USB or TA
VBUS
GND
D+
D-
PG
C1
22 mF
R1
680 W
CHG
IN
BAT
C2
1 mF
ISET
bq25040
R2
2 kW
Bulk Capacitance
needed for
operation without
battery
R4
1 kW
VSS
+
-
VCHG
>40 mF
ABB
Battery Not
Installed for PTM
IFULL
GPIO
EN/SET
LDO
PWRPD
VCHG DET
C2
1 mF
USB DET
VUSBIN
Figure 2. Typical Application Circuit for PTM or With No Battery Installed,
ICHRG = 780mA, ICHGDONE = 39mA
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TYPICAL CHARACTERISTICS
USB500 Mode, Circuit of Figure 2, TA = 25°C
Adapter Plugin With Battery Connected Showing Startup
With PG, CHG, LDO
VEN/SET = 0V
Charger Enable Using EN/SET
VEN/SET = 0 V
5 V/div
VIN
5 V/div
VEN/SET
VLDO
5 V/div
VLDO
5 V/div
200 mA/div
200 mA/div
IOUT
IOUT
VCHG
2 V/div
2 V/div
VPG
2 V/div
VCHG
20 ms/div
20 ms/div
Figure 3.
Figure 4.
Charger Disable Using EN/SET
PTM Load Transient
ROUT = 100Ω to 2.3Ω
Circuit of Figure 2
ROUT = 100 W to 2.3 W
VEN/SET
5 V/div
200 mA/div
VOUT
VLDO
5 V/div
IOUT
200 mA/div
VCHG
2 V/div
IOUT
1 A/div
400 ms/div
40 ms/div
Figure 5.
Figure 6.
USB500 to ISET Mode Transition
Using EN/SET
USB500 to USB100 Mode Transition
Using EN/SET
5 V/div
VEN/SET
5 V/div
VEN/SET
ISET Mode
200 mA/div
IOUT
USB500
IOUT
USB500
200 mA/div
USB100
1 ms/div
1 ms/div
Figure 7.
8
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
USB500 Mode, Circuit of Figure 2, TA = 25°C
UB500 to PTM Transition
Using EN/SET
ROUT=8.4Ω, No battery connected
LDO Load Transient
RLDO = 1kΩ to 100Ω
ROUT = 8.4 W
VEN/SET
5 V/div
VOUT
1 V/div
VLDO
100 mV/div
PTM
USB500
IOUT
200 mA/div
ILDO
50 mA/div
1 ms/div
40 ms/div
Figure 9.
Figure 10.
Complete Charge Cycle
OVP Fault
VIN = 5V to 12V
4.5
0.81
CHG
Voltage
3.5
VIN = 5 V to 10 V
0.72
Battery Voltage
5 V/div
VLDO
0.63
0.54
3
0.45
2.5
Battery Current
2
0.36
1.5
0.27
2 V/div
Battery Current - A
Battery and CHG Voltage - V
4
VIN
500 mA/div
0.18
1
2 V/div
RISET = 1.18 kW,
0.5
0.09
RIFULL = 4.02 kW
IOUT
0
0
0
50
100
150
200
250
300
t - Time - min
350
400
100 ms/div
450
Figure 11.
Figure 12.
Thermal Regulation
Dropout Voltage
vs
Temperature
1
125
0.9
100
0.8
ILOAD = 1.8 A
75
VDO IN-BAT - V
IBAT - mA
0.7
50
0.6
0.5
0.4
0.3
25
ILOAD = 1 A
0.2
0.1
0
25
0
50
75
100
125
TA - Free-Air Temperature - °C
150
0
Figure 13.
25
50
75
100
TA - Free-Air Temperature - °C
125
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
USB500 Mode, Circuit of Figure 2, TA = 25°C
Output Regulation Voltage
vs
Temperature
IC in PTM or CV Regulation
Output Regulation Voltage
vs
Input Voltage
IC in PTM or CV Regulation
4.21
4.35
ILOAD = 1 A
4.208
4.3
ILOAD = 1 A
4.206
4.204
VOUT REG - V
VOUT REG - V
4.25
4.2
4.15
4.202
4.2
4.198
4.196
4.194
4.1
4.192
4.05
0
25
50
75
TA - Free-Air Temperature - °C
100
4.19
4.5
125
5
5.5
6
VI - Input Voltage - V
6.5
7
Figure 15.
Figure 16.
Overvoltage Protection Threshold
vs
Temperature
Fastcharge Current
vs
Input voltage (USB100, USB500, ISET)
7.4
800
7.3
700
ISET
7.2
600
7
500
VI Rising
IBAT - mA
VOVP - V
7.1
6.9
6.8
400
USB500
300
VI Falling
6.7
VIN - DPM
200
6.6
USB100
100
6.5
6.4
0
25
50
75
TA - Free-Air Temperature - °C
100
125
0
4.2
Figure 17.
10
4.7
5.2
5.7
VIN - input Voltage - V
6.2
6.7
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
USB500 Mode, Circuit of Figure 2, TA = 25°C
Fastcharge Current
vs
Battery Voltage
Precharge Current
vs
Battery Voltage
800
0.165
RISET = 680 W
790
780
0.16
770
IBAT - A
IBAT - A
760
750
0.155
740
730
0.15
720
710
700
2.5
3
3.5
VBAT - V
4
4.5
0.145
1.5
1.7
2.1
1.9
2.3
2.5
VBAT - V
Figure 19.
Figure 20.
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DETAILED FUNCTIONAL DESCRIPTION
The bq25040 has a single power output that charges a single cell Li-Ion battery from a USB or AC Adapter
source. A system load can be placed in parallel with the battery. The charge current is programmed using the
ISET and EN/SET inputs. The charge current is programmable to USB100, USB500 or a user programmed
charge current up to 1.1A. A Production Test mode is available that supplies up to 2.3A at 4.2V. Additionally, a
4.9V, 50mA linear regulator (LDO) is integrated into the IC for supplying low power external circuitry. The charger
power stage and charge current sense functions are fully integrated. The charger function has high accuracy
current and voltage regulation loops, charge status display, and charge termination.
Battery Charge Control (BAT)
Charging begins when a battery with a voltage less than VRCH is installed, a valid input source is connected and
the EN/SET input is low. A valid input source is defined as VIN greater than VBAT + 80mV and less than VOVP.
Additionally, VIN must be above the UVLO. The battery is charged in three phases: conditioning precharge,
constant current fast charge (current regulation) and constant voltage tapering (voltage regulation). In all charge
phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an
internal temperature threshold is exceeded. Figure 21 shows a typical charge profile.
PRECHARGE
CC FAST CHARGE
CV TAPER
VOUT(REG)
IFASTCHG
Battery
Current
Battery
Voltage
VLOWV
Battery Full
CHG + Hi-Z
IPRECHG
ICHGDONE
Figure 21. Typical Charge Cycle
When the battery is first installed, the device enters precharge mode. While VBAT is less than VLOWV, the bq25040
remains in precharge mode where the current limit is set to 20% of the current limit programmed at ISET. Once
VBAT exceeds VLOWV, the bq25040 enters fast charge mode where the current limit is set by the EN/SET input
(USB100, USB500, or ISET. See the Input Current Limit section for details). After the battery is charged up to the
VBAT(REG), the device enters voltage regulation. VBAT is regulated to VBAT(REG) as the charge current is reduced.
Once IBAT decreases to the termination current threshold set by IFULL, the CHG output goes high impedance but
charging continues. Figure 21 graphically illustrates a typical charge cycle. The bq25040 does not contain charge
safety timers, so all safety timers must be done by the host processor.
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Single Input Interface (EN/SET)
EN/SET is used to enable/disable the device as well as select the input current limit and Production Test mode.
EN/SET is pulled low to enable the device. After the 50µs deglitch expires, the IC enters the 32ms WAIT state.
EN/SET may be used to program the current limit during this time. Once tWAIT expires, the IC starts up. If no
command is sent to EN/SET during tWAIT, the IC starts up in USB500 mode.
Programming the different modes is done by pulsing the EN/SET input. See Table 1 for a map of the different
modes. A valid high pulse is between 100µs and 700µs. The time between pulses must be between 100µs and
700µs to be properly read. Once EN/SET is held low for 1.5ms, the number of pulses is passed to the control
logic and decoded and then the mode changes. If during the pulse counting, more than 3 pulses occur, the
USB100 mode is immediately selected on the fourth pulse, and the 1.5ms timer does not have to expire. See
Figure 22 for a flow diagram of the EN/SET interface.
Once a mode has been programmed once, further pulses on EN/SET are ignored until power is toggled, or the
device is disabled and then enabled.
Table 1. Pulse Counting Map for EN/SET Interface
NO. OF PULSES
MODE CONTROL
VALUE
0
Current Limit
USB500 Mode
(default for startup)
1
Current Limit
ISET Programmed
2
Current Limit
USB100 Mode
3
Production Test Mode
Enabled
≥4
Current Limit
USB100 Mode
If, at any time, the EN/SET input is held high for more than 1.5ms, the IC is disabled. When disabled, charging is
suspended and the bq25040 input quiescent current is reduced.
BITs decoded once EN/SET
pulled low for 1.5ms
Charge disabled if EN/SET
pulled high for >1.5ms
IC can be
programmed during
tWAIT
tHIGH
Additional pulses on EN/SET
ignored after mode programmed
1.5 ms
EN/SET
1.5 ms
tDGL
tWAIT
tLOW
USB500
IBAT
USB100
Figure 22. EN/SET Timing Diagram
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Any
State
IC Enabled
EN/SET
Rising Edge
Detected?
IC Disabled
NO
EN/SET = 0?
YES
NO
YES
Begin 1.5ms OFF
Timer
USB500 Mode
ICHARGE = 395mA
NO
Falling Edge
Detected?
NO
Has 1.5ms OFF
Timer Expired?
YES
Increment Pulse
Counter
Begin Battery
Charging
Disable IC
Turn off Charge
CHG = Hi-Z
Go to IC Disabled
Routine
YES
Is Pulse Counter
> 3?
USB100 Mode
ICHARGE = 100mA
NO
Begin 1.5ms
LATCH Timer
NO
EN/SET
Rising Edge
Detected?
NO
YES
Has 1.5ms
LATCH Timer
Expired?
YES
Send Pulse
Counter Info to
Decode Block
YES
User Program
Mode
ICHARGE = ISET
YES
USB100 Mode
ICHARGE = 100mA
# PULSE = 1?
NO
# PULSE = 2?
NO
PTM Enabled
VOUT = 4.2V
IIN(LIMIT) > 2.3A
Figure 23. EN/SET State Diagram
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Input Current Limit (ISET, EN/SET)
The fast charge current is programmed using the EN/SET and ISET inputs. The EN/SET input allows the user to
select USB100 mode, USB500 mode, or the user programmable current set by ISET. The user programmable
current is set by connecting a resistor from ISET to VSS. The value of the resistor is determined by:
K
RIS ET = ISET
ICHG
(1)
The fast charge current (ICHG) must be programmed between 100mA and 1.1A. If the current at ISET is
programmed to be less than the USB500 current limit, the current will be limited to the ISET current limit
threshold when USB500 mode is selected. Additionally, the precharge current is always 20% of the current
programmed by ISET, not 20% of the mode selected by EN/SET. However, if USB100 mode is selected, the
precharge current may be restricted to the USB100 limit.
Charge Done Threshold (IFULL)
The charge done threshold is programmed using the IFULL input. The user programmable charge done
threshold is set by connecting a resistor from IFULL to VSS. The value of the resistor is determined by:
RIFULL = IFULL% x KIFULL
(2)
The charge done threshold (IFULL%) is defined as a percentage of the fast charge current programmed at ISET.
IFULL% must be programmed between 5% and 50%. The CHG output goes high once IBAT falls below the
threshold set by IFULL signaling to the microprocessor that the battery is fully charged and the charge cycle
should be terminated, but charging continues until disabled by the EN/SET input.
Production Test Mode (PTM)
The EN/SET interface input for the bq25040 allows the user to select the Production Test mode (PTM). In PTM,
BAT is regulated to 4.2V and supplies up to 2.3A for powering external loads with no battery installed. This
allows the user to supply loads with no battery connected as in production tests. The IC will not handle
continuous dc current of 2.3A. When using currents greater than 1.5A in PTM, the user must limit the duty cycle
at the maximum current to 20% with a maximum period of 10ms. In PTM, thermal regulation is disabled;
however, thermal shutdown is still active.
Undervoltage Lockout
The bq25040 remains in power down mode when the input voltage is below the undervoltage lockout threshold
(UVLO). During this mode, the control input (EN/SET) is ignored. The charge FET connected between IN and
BAT is off and the status outputs (CE and PG) are high impedance. Once the input voltage rises above UVLO,
the internal circuitry is turned on and the normal operating procedures are followed.
Input Overvoltage Protection
The bq25040 contains an input overvoltage protection circuit that disables the LDO output and charging when
the input voltage rises above VOVP. This prevents damage from faulty adapters. The OVP circuitry contains a
115µs deglitch that prevents ringing on the input from line transients from tripping the OVP circuitry falsely. If an
adapter with an output greater than VOVP is plugged in, the IC completes soft-start power up and then shuts
down if the voltage remains above VOVP after 115µs. The LDO remains off and charging remains disabled until
the input voltage falls below VOVP.
Input DPM Mode (VIN-DPM)
The bq25040 uses the VIN-DPM mode for operation from current-limited USB ports. When in USB100 or USB500
mode, VIN-DPM is enabled, the input voltage is monitored. If VIN falls to VIN-DPM, the input current limit is
reduced to prevent the input voltage from falling further. This prevents the bq25040 from crashing poorly
designed or incorrectly configured USB sources. Figure 24 shows the VIN-DPM behavior to a current limited
source. In this figure, the input source has a 250mA current limit and the device is configured with the 395mA
current limit (USB500 mode).
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500mV/div
VISET
2V/div
VIN
200mA/div
IOUT
USB500
Time - 1ms/div
Figure 24. VIN-DPM Protects from Crashing Poor Input Sources
50 mA LDO (LDO)
The LDO output of the bq25040 is a low dropout linear regulator (LDO) that supplies up to 50mA while regulating
to VLDO. The LDO is active whenever the input voltage is between UVLO and VOVP. It is not affected by the
EN/SET input. The LDO output is used to power circuitry such as USB transceivers in dead battery conditions.
This allows the user to operate the product immediately after plugging the adapter in, instead of waiting for the
battery to charge to useable levels. Note that the LDO current is not monitored by the input current limit. The
LDO current is limited separately and is in addition to the input current limit.
Charge Done Indicator (CHG)
The bq25040 contains an open drain CHG output that indicates when a charge cycle is complete. When charging
a battery in precharge, fastcharge or CV mode, the CHG output is pulled to VSS. Once the BAT output reaches
regulation and the charge current falls below the termination threshold, CHG goes high impedance to signal the
battery is fully charged. The CHG output remains high during subsequent battery refresh charges. Connect CHG
to the required logic level voltage through a 1kΩ to 100kΩ resistor to use the signal with a microprocessor.
Additionally, CHG may be used to drive an LED for a visual charging status signal. ICHG must be below 15mA.
CHG may be pulled up to any voltage rail less than the maximum rating on the CHG output. Many LED
applications choose to pull up CHG to the battery voltage. This is acceptable; however, note that at low battery
conditions, the LED may appear dim. Another option is to pull up CHG to the LDO output. This is also
acceptable; however, note that the LDO current is not limited by the input current limit and the additional current
may cause the bq25040 input current to exceed the maximum USB100 specification.
Power Good (PG)
The bq25040 contains a PG signal that indicates when a valid input source is connected. The PG output goes
low when an input source between (VBAT + 80mV) and VOVP is connected. Additionally, the input source must be
greater than the UVLO voltage threshold. See Table 2 for the nominal PG deglitches under different conditions.
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Table 2.
CONDITION
PG DEGLITCH (MEASURED FROM EVENT TO PG HIGH OR LOW)
bq25040 ENABLED (EN/SET low)
bq25040 DISABLED (EN/SET high)
Entering OVP (VIN = 5.5V→10V)
100 µs
0
Leaving OVP (VIN = 10V→5.5V)
450 µs
500 µs
Entering SLEEP (VIN = 5.5V→3.6V)
32 ms
0
Leaving SLEEP(VIN = 3.6V→5.5V)
500 µs
500 µs
Entering UVLO (VIN = 5.5V→2.5V)
0
0
Leaving UVLO (VIN = 2.5V→5.5V)
230 µs
230 µs
PG may be pulled up to any voltage rail less than the maximum rating on the PG output. Many LED applications
choose to pull up PG to the battery voltage. This is acceptable, however note that at low battery conditions, the
LED may appear dim. Another option is to pull up PG to the LDO output. This is also acceptable, however note
that the LDO current is not limited by the input current limit and the additional current may cause the bq25040
input current to exceed the maximum USB100 specification.
Thermal Regulation and Thermal Shutdown
The bq25040 contain a thermal regulation loop that monitors the die temperature continuously. If the temperature
exceeds TJ(REG), the device automatically reduces the charging current to prevent the die temperature from
increasing further. The LDO current is not modified by thermal regulation. If the die temperature continues to rise
despite the operation of the thermal loop, and increases to TJ(OFF), the IC is turned off. Once the device die
temperature cools by TJ(OFF-HYS), the device turns on and returns to thermal regulation. Continuous
over-temperature conditions result in the pulsing of the load current. If the junction temperature of the device
exceeds TJ(OFF), the charge FET is turned off. The FET is turned back on when the junction temperature falls
below TJ(OFF) – TJ(OFF-HYS).
Note that these features monitor the die temperature of the bq25040. This is not synonymous with ambient
temperature. Self heating exists due to the power dissipated in the IC because of the linear nature of the battery
charging algorithm. Battery NTC monitoring must be done by the host processor.
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APPLICATION INFORMATION
Selection of Input/Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. For
normal charging applications, a 1µF ceramic capacitor, placed in close proximity to the IN pin and GND pad
works best. For Production Test mode applications, where the current is up to 2.3A, a 22µF input capacitor is
required. In some applications, depending on the power supply characteristics and cable length, it may be
necessary to increase the input filter capacitor to avoid exceeding the OVP voltage threshold during adapter hot
plug events where the ringing exceeds the deglitch time.
The charger in the bq25040 requires a capacitor from BAT to GND for loop stability. Connect a 1µF ceramic
capacitor from BAT to GND close to the pins for best results. For Production Test mode applications up to 2.3A,
a 40µF capacitor from BAT to GND is required. More output capacitance may be required to minimize the output
droop during large load transients.
The LDO also requires an output capacitor for loop stability. Connect at least a 1µF ceramic capacitor from LDO
to GND close to the pins. For improved transient response, this capacitor may be increased.
b25040 Charger Design Example
The following sections provide an example for determining the component values for use with the bq25040.
Requirements
Refer to Figure 1 for Schematics of the Design Example.
•
•
•
Supply voltage = 5V
Fast charge current of approximately 780 mA; ISET - pin 2
Full Current Threshold = 10% of Fast Charge; IFULL – pin 5
Calculations
Program the Fast Charge Current (ISET)
RISET = KISET / ICHG
KISET = 530AΩ from the electrical characteristics table.
RISET = 530AΩ/0.78A = 679Ω
Select the closest standard value, which for this case is 680Ω. Connect this resistor between ISET (pin 2) and
VSS.
Program the Charge Done Current (IFULL)
RIFULL = KIFULL × IIFULL%
KIFULL = 200Ω/%.
RIFULL = 200Ω/% × 10% = 2kΩ.
Connect this resistor between IFULL (pin 5) and VSS.
Status Indicators (CHG and PG)
The STAT pins (PG and CHG) are open drain FETs (internal), if used, should be pulled up via a resistor and
possibly a LED to a power source. If monitored by a host, the host VCC source should be used. The PG and
CHG are 7V devices. If used as a LED indicator, the BAT, LDO or IN could be used.
If the IN pin is used a 6.2V zener should be used to clamp the voltage if there is a possibility that the input
voltage could exceed 7V. If the BAT pin is used, as the battery voltage changes the intensity of the LED will
change. The brightness is greatly decreased for a battery voltage less than 3V. The LDO may be the best source
to power the LEDs from since it is a regulated source for high input voltages.
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Thermal Considerations
The bq25040 is packaged in a thermally enhanced SON package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment Application
Note (SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA ) measured (or modeled)
from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θJA
is:
T - TA
J JA = J
PD
(3)
Where:
TJ = chip junction temperature
TA = ambient temperature
PD = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
The device power dissipation, PD, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged:
PD = (VIN – VOUT) × IOUT
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See the charging profile. If the board thermal design is
not adequate the programmed fast charge rate current may not be achieved under maximum input voltage and
minimum battery voltage, as the thermal loop can be active, effectively reducing the charge current to avoid
excessive IC junction temperature
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PCB Layout Considerations
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq25040, with short
trace runs to both IN, OUT and GND (thermal pad).
• All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
• The bq25040 is packaged in a thermally enhanced QFN package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is
also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. Full
PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB
Attachment Application Note (SLUA271).
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ25040DQCR
ACTIVE
WSON
DQC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OAB
BQ25040DQCT
ACTIVE
WSON
DQC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OAB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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