BQ25620, BQ25622
SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
BQ25620/BQ25622 I2C Controlled, 3.5-A, Maximum 18-V Input, Charger with NVDC
Power Path Management and OTG Output
1 Features
•
•
•
3 Description
•
•
•
•
•
•
•
•
•
High-efficiency, 1.5-MHz, synchronous switching
mode buck charger for single cell battery
– >90% efficiency down to 25-mA output current
from 5-V input
– Charge termination from 10 mA to 620 mA, 10mA steps
– Flexible JEITA profile for safe charging over
temperature
BATFET control to support shutdown, ship mode
and full system reset
– 1.5-μA quiescent current in battery only mode
– 0.15-μA battery leakage current in ship mode
– 0.1-μA battery leakage current in shutdown
Supports USB On-The-Go (OTG)
– Boost mode operation supporting 3.84-V to 9.6V output
– >90% boost efficiency down to 100-mA OTG
current for 5-V VBUS
Supports a wide range of input sources
– 3.9-V to 18-V wide input operating voltage
range with 26-V absolute maximum input
voltage
– Maximizes source power with input voltage
regulation (VINDPM) and input current
regulation (IINDPM)
– VINDPM threshold automatically tracks battery
voltage
Efficient battery operation with 15-mΩ BATFET
Narrow VDC (NVDC) power path management
– System instant-on with depleted or no battery
– Battery supplement when adapter is fully
loaded
Flexible autonomous or I2C-controlled modes
Integrated 12-bit ADC for voltage, current,
temperature monitoring
High accuracy
– ±0.5% charge voltage regulation
– ±5% charge current regulation
– ±5% input current regulation
Safety
– Thermal regulation and thermal shutdown
– Input, system, battery overvoltage protection
– Battery, converter overcurrent protection
– Charging safety timer
2 Applications
•
•
IP Camera, EPOS
Portable Medical Equipment
The BQ25620 and BQ25622 are highly-integrated
3.5-A switch-mode battery charge management and
system power path management devices for single
cell Li-Ion and Li-polymer batteries. The solution is
highly integrated with built-in current sensing, loop
compensation, input reverse-blocking FET (RBFET,
Q1), high-side switching FET (HSFET, Q2), lowside switching FET (LSFET, Q3), and battery FET
(BATFET, Q4) between system and battery. The
devices use narrow VDC power path management,
regulating the system slightly above the battery
voltage without dropping below a configurable
minimum system voltage. The low impedance power
path optimizes switch-mode operation efficiency,
reduces battery charging time, extends battery life
during discharging phase, and the ultra-low 0.15-μA
ship mode current extends battery shelf life. The I2C
serial interface with charging and system settings
makes the BQ25620 and BQ25622 truly flexible
solutions.
Device Information
PACKAGE(1)
PART NUMBER
BODY SIZE (NOM)
BQ25620
WQFN (18)
2.50 mm × 3.00 mm
BQ25622
WQFN (18)
2.50 mm × 3.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
1 uH
3.4 - 18V
USB
USB
Detection
VBUS
D+/D- (620)
TS_BIAS (622)
ILIM (622)
Host
PG
BTST
SYS
REGN
2
I C Bus
System
Load
SW
2.6 – 4.85V
REGN (620)
TS_BIAS (622)
BQ25620
BQ25622
CE
TS
QON
BAT
1.8 – 4.8V
GND
Optional
BQ25620/2 Simplified Application Diagram
Tablet
Gaming and Computer Accessories
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ25620, BQ25622
www.ti.com
SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison......................................................... 4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................ 16
8.7 Typical Characteristics.............................................. 18
9 Detailed Description......................................................20
9.1 Overview................................................................... 20
9.2 Functional Block Diagram......................................... 21
9.3 Feature Description...................................................22
9.4 Device Functional Modes..........................................33
9.5 Programming............................................................ 35
9.6 Register Maps...........................................................38
10 Application and Implementation................................ 65
10.1 Application Information........................................... 65
10.2 Typical Application.................................................. 65
11 Power Supply Recommendations..............................71
12 Layout...........................................................................72
12.1 Layout Guidelines................................................... 72
12.2 Layout Example...................................................... 72
13 Device and Documentation Support..........................75
13.1 Device Support....................................................... 75
13.2 Documentation Support.......................................... 75
13.3 Receiving Notification of Documentation Updates..75
13.4 Support Resources................................................. 75
13.5 Trademarks............................................................. 75
13.6 Electrostatic Discharge Caution..............................75
13.7 Glossary..................................................................75
14 Mechanical, Packaging, and Orderable
Information.................................................................... 76
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2022) to Revision A (October 2022)
Page
• Changed BQ25622 from Preview to Production Data........................................................................................ 1
2
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BQ25620, BQ25622
SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
5 Description (continued)
The BQ25620 supports a wide range of input sources, including standard USB host port, USB charging port,
and USB compliant high voltage adapter. It sets the default input current limit based on the built-in D+/D- USB
adapter detection interface. BQ25622 has an ILIM pin to set the default input current limit and a TS_BIAS
pin for controlled thermistor bias. The device is compliant with USB 2.0 and USB 3.0 power specifications for
input current and voltage regulation and meets USB On-the-Go (OTG) operation power rating specification with
constant current limit up to 3.2 A.
The power path management regulates the system slightly above battery voltage but does not drop below
the programmable minimum system voltage. With this feature, the system maintains operation even when the
battery is completely depleted or removed. When the input current limit or input voltage limit is reached, the
power path management automatically reduces the charge current. As the system load continues to increase,
the battery starts to discharge until the system power requirement is met. This supplement mode prevents
overloading the input source.
The BQ25620 and BQ25622 initiate and complete a charging cycle without host control. By sensing the battery
voltage, it charges the battery in four different phases: trickle charge, pre-charge, constant current (CC) charge,
and constant voltage (CV) charge. At the end of the charging cycle, the charger automatically terminates when
the charge current is below a preset threshold and the battery voltage is higher than the recharge threshold.
Termination is supported for all TS pin temperature zones.
The BQ25620 and BQ25622 provide various safety features for battery charging and system operations,
including battery negative temperature coefficient thermistor monitoring, charging safety timer, and overvoltage
and overcurrent protections. The thermal regulation reduces charge current when the junction temperature
exceeds the programmable threshold. The STAT output reports the charging status and any fault conditions.
Other safety features include battery temperature sensing for charge mode and OTG boost mode, thermal
shutdown and input UVLO and overvoltage protection. The PG output indicates if a good power source is
present. The INT output notifies the host when a fault occurs or status changes.
The BQ25620 and BQ25622 are available in a 18-pin, 2.5 mm × 3.0 mm WQFN package.
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
6 Device Comparison
Table 6-1. Device Comparison
FUNCTION
BQ25611D
BQ25616
BQ25620
BQ25622
Input Voltage Range
4V - 13.5V
4V - 13.5V
3.9V - 18V
3.9V - 18V
I2C
I2C
Part Configuration
I2C
Standalone
3.5 - 4.3V (100mV per
step); 4.3 - 4.52V (10mV
per step)
4.1V / 4.2V / 4.35V
D+/D- USB Detection
Yes
Yes
Yes
No
ILIM Pin
No
Yes
No
Yes
TS Profile
JEITA
HOT/COLD
JEITA
JEITA
Quiescent Battery Current
9.5μA
9.5μA
1.5μA
1.5μA
Programmable Charge
Voltage
OTG
Yes
Yes
Yes
Yes
OTG Current Limit
1.2A
1.2A
3.2A
3.2A
ADC
Package
4
3.5 - 4.8V (10mV per step) 3.5 - 4.8V (10mV per step)
None
None
12-bit ADC
12-bit ADC
4x4mm2 QFN (24)
4x4mm2 QFN (24)
2.5x3mm2 QFN (18)
2.5x3mm2 QFN (18)
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
VBUS
PMID
SW
GND
18
17
16
15
7 Pin Configuration and Functions
BTST
1
14
CE
REGN
2
13
SCL
PG
3
12
SDA
D-
4
11
INT
D+
5
10
STAT
6
7
8
9
TS
QON
BAT
SYS
BQ25620
RYK
2.5mm x 3mm
VBUS
PMID
SW
GND
18
17
16
15
Figure 7-1. BQ25620 Pinout, 18-Pin WQFN Top View
BTST
1
14
CE
REGN
2
13
SCL
PG
3
12
SDA
ILIM
4
11
INT
TS_BIAS
5
10
STAT
6
7
8
9
TS
QON
BAT
SYS
BQ25622
RYK
2.5mm x 3mm
Figure 7-2. BQ25622 Pinout, 18-Pin WQFN Top View
Table 7-1. Pin Functions
NAME
BQ25622
BQ25620
BTST
REGN
NO.
TYPE(1)
DESCRIPTION
1
P
High Side Switching MOSFET Gate Driver Power Supply – Connect a 10V or higher
rating, 47nF ceramic capacitor between SW and BTST as the bootstrap capacitor for driving
high side switching MOSFET (Q2).
P
The Charger Internal Linear Regulator Output – Internally, REGN is connected to the
anode of the boost-strap diode. Connect a 10V or higher rating, 4.7μF ceramic capacitor
from REGN to power ground, The capacitor should be placed close to the IC. The REGN
LDO output is used for the internal MOSFETs gate driving voltage and for biasing the
external TS pin thermistor in BQ25620.
2
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Table 7-1. Pin Functions (continued)
NAME
BQ25622
BQ25620
PG
ILIM
D-
NO.
TYPE(1)
3
DO
4
AIO
DESCRIPTION
Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10kΩ
resistor. LOW indicates an input source of VVBUS_UVLO < VBUS < VVBUS_OVP. Failing poor
source detection or triggering the sleep comparator ( VBUS < VBAT + VSLEEP ) also causes
PG to transition HIGH.
Input Current Limit Setting Input Pin – ILIM pin sets the input current limit as IINREG =
KILIM / RILIM, where RILIM is connected from ILIM pin to GND. The input current is limited to
the lower of the two values set by ILIM pin and IINDPM register bits. The ILIM pin can also
be used to monitor input current. The input current is proportional to the voltage on ILIM pin
and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8). The ILIM pin function is disabled
when EN_EXTILIM bit is set to 0.
Negative Line of the USB Data Line Pair – D+/D- based USB host/charging port detection.
The detection includes data contact detection (DCD), primary and secondary detection in
BC1.2.
P
TS_BIAS
D+
TS
(1)
6
5
6
Bias for the TS Resistor Voltage Divider – Provides the bias voltage for the TS resistor
voltage divider.
AIO
Positive Line of the USB Data Line Pair – D+/D- based USB host/charging port detection.
The detection includes data contact detection (DCD), primary and secondary detection in
BC1.2.
AI
Temperature Qualification Voltage Input – Connect a negative temperature coefficient
thermistor. Program temperature window with a resistor divider from TS pin bias reference
(REGN in BQ25620, TS_BIAS in BQ25622) to TS, then to GND. Charge suspends when TS
pin voltage is out of range. Recommend a 103AT-2 10kΩ thermistor.
QON
7
DI
BATFET Enable or System Power Reset Control Input – If the charger is in ship mode, a
logic low on this pin with tSM_EXIT duration forces the device to exit ship mode. If the charger
is not in ship mode, a logic low on this pin with tRST initiates a full system power reset if either
VVBUS < VVBUS_UVLO or BATFET_CTRL_WVBUS = 1. QON has no effect during shutdown
mode. The pin contains an internal pull-up to maintain default high logic.
BAT
8
P
The Battery Charging Power Connection – Connect to the positive terminal of the battery
pack. The internal BATFET is connected between SYS and BAT.
SYS
9
P
The Charger Output Voltage to System –The Buck converter output connection point to
the system. The internal BATFET is connected between SYS and BAT.
STAT
10
DO
Open Drain Charge Status Output – It indicates various charger operations. Connect to the
pull up rail via 10kΩ resistor. LOW indicates charging in progress. HIGH indicates charging
completed or charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz.
Setting DIS_STAT = 1 disables the STAT pin function, causing the pin to be pulled HIGH.
Leave floating if unused.
INT
11
DO
Open Drain Interrupt Output. – Connect to the pull up rail via 10kΩ resistor. The INT pin
sends an active low, 256μs pulse to the host to report the charger device status and faults.
SDA
12
DIO
I2C Interface Data – Connect SDA to the logic rail through a 10 kΩ resistor.
SCL
13
DI
I2C Interface Clock – Connect SCL to the logic rail through a 10 kΩ resistor.
CE
14
DI
Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and
CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating.
GND
15
P
Ground Return
SW
16
P
Switching Node Connecting to Output Inductor – Internally SW is connected to the
source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 47 nF
bootstrap capacitor from SW to BTST.
PMID
17
P
HSFET Drain Connection – Internally PMID is connected to the drain of the reverse
blocking MOSFET (RBFET) and the drain of HSFET.
VBUS
18
P
Charger Input Voltage – The internal n-channel reverse block MOSFET (RBFET) is
connected between VBUS and PMID with VBUS on source.
AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,
P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VBUS (converter not switching)
–2
26
V
PMID (converter not switching)
–0.3
26
V
BAT, SYS (converter not switching)
Voltage range (with
respect to GND)
Output Sink Current
Differential Voltage
UNIT
–0.3
6
V
–2 (50ns)
21
V
BTST (when converter switching)
–0.3
27
V
CE, STAT, SCL, SDA, INT, REGN, QON
–0.3
6
V
D+, D-, ILIM, PG, TS, TS_BIAS
–0.3
6
V
6
mA
SW
INT, STAT, PG
BTST-SW
–0.3
6
V
PMID-VBUS
–0.3
6
V
SYS-BAT
–0.3
6
V
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
V(ESD)
(1)
(2)
Electrostatic discharge
pins(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VVBUS
Input voltage
18
V
VBAT
Battery voltage
4.8
V
IVBUS
Input current
3.2
A
ISW
Output current (SW)
3.5
A
Fast charging current
IBAT
3.9
NOM
3.5
A
RMS discharge current (continuously)
6
A
Peak discharge current (up to 50ms)
10
A
IREGN
Maximum REGN Current
20
mA
TA
Ambient temperature
–40
85
°C
TJ
Junction temperature
–40
125
°C
LSW
Inductor for the switching regulator
0.68
2.2
µH
CVBUS
VBUS capacitor (without de-rating)
1
CPMID
PMID capacitor (without de-rating)
10
CSYS
SYS capacitor (without de-rating)
20
µF
µF
500
µF
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8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
CBAT
BAT capacitor (without de-rating)
NOM
MAX
UNIT
10
µF
8.4 Thermal Information
BQ25620, BQ25622
THERMAL METRIC(1)
RYK (QFN)
UNIT
18 pins
RθJA
Junction-to-ambient thermal resistance
60.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.1
°C/W
RθJB
Junction-to-board thermal resistance
13.0
°C/W
ΨJT
Junction-to-top characterization parameter
1.3
°C/W
ΨJB
Junction-to-board characterization parameter
12.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
IQ_BAT
Quiescent battery current (BAT,
SYS, SW) when the charger is in
the battery only mode, BATFET is
enabled, ADC is disabled
VBAT = 4V, No VBUS, BATFET is
enabled, I2C enabled, ADC disabled,
system is powered by battery. -40 °C <
TJ < 60 °C
1.5
IQ_BAT_ADC
Quiescent battery current (BAT,
SYS, SW) when the charger is in
the battery only mode, BATFET is
enabled, ADC is enabled
VBAT = 4V, No VBUS, BATFET is
enabled, I2C enabled, ADC enabled,
system is powered by battery. -40 °C <
TJ < 60 °C
260
IQ_BAT_SD
Quiescent battery current (BAT)
when the charger is in shutdown
mode, BATFET is disabled, ADC
is disabled
VBAT = 4V, No VBUS, BATFET is
disabled, I2C disabled, in shutdown
mode, ADC disabled, TJ < 60 °C
0.1
0.2
µA
IQ_BAT_SHIP
Quiescent battery current (BAT)
when the charger is in ship
mode, BATFET is disabled, ADC
is disabled
VBAT = 4V, No VBUS, BATFET is
disabled, I2C disabled, in ship mode,
ADC disabled, TJ < 60 °C
0.15
0.5
µA
IQ_VBUS
Quiescent input current (VBUS)
VBUS = 5V, VBAT = 4V, charge disabled,
converter switching, ISYS = 0A, PFM
enabled
450
IQ_VBUS_HIZ
VBUS = 5V, VBAT = 4V, HIZ mode, ADC
Quiescent input current (VBUS) in disabled
HIZ
VBUS = 15V, VBAT = 4V, HIZ mode, ADC
disabled
IQ_OTG
Quiescent battery current (BAT,
SYS, SW) in boost OTG mode
VBAT = 4.2V, VBUS = 5V, OTG
mode enabled, converter switching,
PFM enabled, IVBUS = 0A, TS float,
TS_IGNORE = 1
3
µA
µA
µA
5
20
µA
20
35
µA
250
µA
VBUS / VBAT SUPPLY
8
VVBUS_OP
VBUS operating range
VVBUS_UVLO
VBUS falling to turn off I2C, no
battery
3.9
VBUS falling
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3.0
3.15
18
V
3.3
V
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
3.2
3.35
3.5
V
6.1
6.4
6.7
V
VVBUS_UVLOZ
VBUS rising for active I2C, no
battery
VVBUS_OVP
VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 0
VVBUS_OVPZ
VBUS overvoltage falling hreshold VBUS rising, VBUS_OVP = 0
5.8
6.0
6.2
V
VVBUS_OVP
VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 1
18.2
18.5
18.8
V
VVBUS_OVPZ
VBUS overvoltage falling
threshold
VBUS falling, VBUS_OVP = 1
17.4
17.7
18.0
V
VSLEEP
Enter Sleep mode threshold
(VBUS - VBAT), VBUS falling
9
45
85
mV
VSLEEPZ
Exit Sleep mode threshold
(VBUS - VBAT), VBUS rising
115
220
340
mV
VBAT_UVLOZ
BAT voltage for active I2C, turn on
VBAT rising
BATFET, no VBUS
2.3
2.4
2.5
V
VBAT_UVLO
BAT voltage to turnoff I2C, turn off VBAT falling, VBAT_UVLO = 0
BATFET, no VBUS
VBAT falling, VBAT_UVLO = 1
2.1
2.2
2.3
V
VBUS rising
1.7
1.8
1.9
V
BAT voltage rising threshold to
enable OTG mode
VBAT rising, VBAT_OTG_MIN = 0
2.9
3.0
3.1
V
VBAT rising, VBAT_OTG_MIN = 1
2.5
2.6
2.7
V
VBAT_OTGZ
BAT voltage falling threshold to
disable OTG mode
VBAT falling, VBAT_OTG_MIN = 0
2.7
2.8
2.9
V
VBAT falling, VBAT_OTG_MIN = 1
2.3
2.4
2.5
V
VPOORSRC
Bad adapter detection threshold
VBUS falling
3.6
3.7
V
IPOORSRC
Bad adapter detection current
source
10
mA
ISYS = 0A, VBAT > VSYSMIN, Charge
Disabled. Offset above VBAT
50
mV
ISYS = 0A, VBAT < VSYSMIN, Charge
Disabled. Offset above VSYSMIN
230
mV
VBAT_OTG
POWER-PATH MANAGEMENT
VSYS_REG_ACC
Typical system voltage regulation
VSYSMIN_RNG
VSYSMIN register range
2.56
VSYSMIN_REG_STEP
VSYSMIN register step size
VSYSMIN_REG_ACC
Minimum DC system voltage
output
VSYS_SHORT
VSYS_SHORTZ
3.84
80
ISYS = 0A, VBAT < VSYSMIN = B00h
(3.52V), Charge Disabled
3.52
V
mV
3.75
V
VSYS short voltage falling
threshold to enter forced PFM
0.9
V
VSYS short voltage rising
threshold to exit forced PFM
1.1
V
BATTERY CHARGER
VREG_RANGE
Typical charge voltage regulation
range
VREG_STEP
Typical charge voltage step
VREG_ACC
Charge voltage accuracy
ICHG_RANGE
Typical charge current regulation
range
ICHG_STEP
Typical charge current regulation
step
ICHG_ACC
Charge current accuracy
3.50
4.80
10
V
mV
TJ = 25°C
–0.3
0.3
%
TJ = –10°C - 85°C
–0.4
0.4
%
0.08
3.52
A
80
mA
VBAT = 3.1V or 3.8V, ICHG = 1760mA, TJ
= –10°C - 85°C
–5
5
%
VBAT = 3.1V or 3.8V, ICHG = 1040mA, TJ
= –10°C - 85°C
–5.5
5.5
%
VBAT = 3.1V or 3.8V, ICHG = 320mA, TJ
= –10°C - 85°C
–5.5
5.5
%
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IPRECHG_RANGE
Typical pre-charge current range
IPRECHG_STEP
Typical pre-charge current step
IPRECHG_ACC
MIN
TYP
20
MAX UNIT
620
20
mA
mA
VBAT = 2.5V, IPRECHG = 500mA, TJ =
–10°C - 85°C
–12
12
%
Pre-charge current accuracy when VBAT = 2.5V, IPRECHG = 200mA, TJ =
VBAT below VSYSMIN setting
–10°C - 85°C
–12
12
%
VBAT = 2.5V, IPRECHG = 100mA, TJ =
–10°C - 85°C
–15
15
%
620
mA
ITERM_RANGE
Typical termination current range
ITERM_STEP
Typical termination current step
10
ITERM_ACC
Termination current accuracy
VBAT_SHORTZ
Battery short voltage rising
threshold to start pre-charge
VBAT rising
2.25
V
VBAT_SHORT
Battery short voltage falling
threshold to stop pre-charge
VBAT falling, VBAT_UVLO=0
2.05
V
VBAT_SHORT
Battery short voltage falling
threshold to stop pre-charge
VBAT falling, VBAT_UVLO=1
1.85
V
IBAT_SHORT
Battery short trickle charging
current
VBAT < VBAT_SHORTZ, ITRICKLE = 0
VBAT < VBAT_SHORTZ, ITRICKLE = 1
VBAT_LOWVZ
Battery voltage rising threshold
Transition from pre-charge to fast charge
VBAT_LOWV
Battery voltage falling threshold
Transition from fast charge to pre-charge
2.7
VRECHG
Battery recharge threshold below
VREG
VBAT falling, VRECHG = 0
IPMID_LOAD
PMID discharge load current
20
IBAT_LOAD
Battery discharge load current
ISYS_LOAD
System discharge load current
10
mA
ITERM = 20mA, TJ = –10°C - 85°C
–60
60
%
ITERM = 100mA, TJ = –10°C - 85°C
–15
15
%
ITERM = 300mA, TJ = –10°C - 85°C
–13
13
%
15
25
35
mA
62
82
102
mA
2.9
3.0
3.1
V
2.8
2.9
V
100
mV
200
mV
30
mA
20
30
mA
20
30
mA
VBAT falling, VRECHG = 1
BATFET
RBATFET
MOSFET on resistance from SYS
to BAT
15
25
mΩ
BATTERY PROTECTIONS
VBAT_OVP
Battery overvoltage rising
threshold
As percentage of VREG
103
104
105
%
VBAT_OVPZ
Battery overvoltage falling
threshold
As percentage of VREG
101
102
103
%
IBATFET_OCP
BATFET over-current rising
threshold
IBAT_PK
Battery discharging peak current
rising threshold
6
A
IBAT_PK = 00
1.5
A
IBAT_PK = 01
3
A
IBAT_PK = 10
6
A
IBAT_PK = 11
12
A
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE
Typical input voltage regulation
range
VINDPM_STEP
Typical input voltage regulation
step
10
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16.8
40
V
mV
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VINDPM_ACC
TEST CONDITIONS
Input voltage regulation accuracy
VINDPM_BAT_TRACK
Battery tracking VINDPM accuracy
IINDPM_RANGE
Typical input current regulation
range
IINDPM_STEP
Typical input current regulation
step
MIN
TYP
MAX UNIT
VINDPM=4.6V
–4
4
%
VINDPM=8V
–3
3
%
VINDPM=16V
–2
2
%
4.45
V
3.2
A
VBAT = 3.9V, VINDPM_BAT_TRACK=1,
VINDPM = 4V
4.15
4.3
0.04
20
IINDPM = 500mA, VBUS=5V
450
475
mA
500
mA
IINDPM = 900mA, VBUS=5V
810
855
900
mA
IINDPM = 1500mA, VBUS=5V
1350
1425
1500
mA
ILIM Pin Scale Factor, IINREG =
KILIM / RILIM
INREG = 1.6 A
2250
2500
2750
AΩ
VD+D-_0p6V_SRC
D+/D- voltage source (600 mV)
1 mA load on D+/D-
400
600
800
mV
ID+D-_LKG
Leakage current into D+/D-
HiZ mode
–1
1
µA
VD+D-_2p8
D+/D- comparator threshold for
non-standard adapter
2.55
2.85
V
VD+D-_2p0
D+/D- comparator threshold for
non-standard adapter
1.85
2.15
V
IINDPM_ACC
KILIM
Input current regulation accuracy
D+ / D- DETECTION
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG = 1
120
°C
TREG = 0
60
°C
140
°C
30
°C
TREG
Junction temperature regulation
accuracy
TSHUT
Thermal Shutdown Rising
Threshold
Temperature Increasing
TSHUT_HYS
Thermal Shutdown Falling
Hysteresis
Temperature Decreasing by TSHUT_HYS
THERMISTOR COMPARATORS (CHARGE MODE)
VTS_COLD
VTS_COLDZ
TS pin rising voltage threshold
for TH1 comparator to
transition from TS_COOL to
TS_COLD. Charge suspended
above this voltage.
TS pin falling voltage threshold
for TH1 comparator to
transition from TS_COLD to
TS_COOL. TS_COOL charge
settings resume below this
voltage.
As Percentage to TS pin bias reference
(-5°C w/ 103AT), TS_TH1_TH2_TH3
= 100, 101, 110
75.0
75.5
76.0
%
As Percentage to TS pin bias reference
(0°C w/ 103AT), Fixed JEITA threshold or
TS_TH1_TH2_TH3 = 000, 001, 010, 011,
111
72.8
73.3
73.8
%
As Percentage to TS pin bias reference
(-2.5°C w/ 103AT), TS_TH1_TH2_TH3
= 100, 101, 110
73.9
74.4
74.9
%
As Percentage to TS pin bias reference
(2.5°C w/ 103AT), Fixed JEITA threshold
or TS_TH1_TH2_TH3 = 000, 001, 010,
011, 111
71.7
72.2
72.7
%
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VTS_COOL
VTS_COOLZ
VTS_PRECOOL
VTS_PRECOOLZ
VTS_PREWARM
VTS_PREWARMZ
12
TS pin rising voltage threshold
for TH2 comparator to
transition from TS_PRECOOL to
TS_COOL. TS_COOL charging
settings used above this voltage.
TS pin falling voltage threshold
for TH2 comparator to
transition from TS_COOL to
TS_PRECOOL. TS_PRECOOL
charging settings resume below
this voltage.
TS pin rising voltage threshold
for TH3 comparator to
transition from TS_NORMAL to
TS_PRECOOL. TS_PRECOOL
charge settings used above this
voltage.
TS pin falling voltage threshold
for TH3 comparator to
transition from TS_PRECOOL to
TS_NORMAL. Normal charging
resumes below this voltage.
TS pin falling voltage threshold
for TH4 comparator to
transition from TS_NORMAL to
TS_PREWARM. TS_PREWARM
charging settings used below this
voltage.
TS pin rising voltage threshold
for TH4 comparator to
transition from TS_PREWARM to
TS_NORMAL. Normal charging
resumes above this voltage.
TEST CONDITIONS
MIN
TYP
MAX UNIT
As Percentage to TS pin bias reference
(5°C w/ 103AT), TS_ISET_COOL = 00 or
TS_TH1_TH2_TH3 = 000, 100
70.6
71.1
71.6
%
As Percentage to TS pin bias reference
(10°C w/ 103AT), TS_ISET_COOL = 01
or TS_TH1_TH2_TH3 = 001, 101, 110,
111
67.9
68.4
68.9
%
As Percentage to TS pin bias reference
(15°C w/ 103AT), TS_ISET_COOL = 10
or TS_TH1_TH2_TH3 = 010
65.0
65.5
66.0
%
As Percentage to TS pin bias reference
(20°C w/ 103AT), TS_ISET_COOL = 11
or TS_TH1_TH2_TH3 = 011
61.9
62.4
62.9
%
As Percentage to TS pin bias reference
(7.5°C w/ 103AT), TS_ISET_COOL = 00
or TS_TH1_TH2_TH3 = 000, 100
69.3
69.8
70.3
%
As Percentage to TS pin bias reference
(12.5°C w/ 103AT), TS_ISET_COOL = 01
or TS_TH1_TH2_TH3 = 001, 101, 110,
111
66.6
67.1
67.6
%
As Percentage to TS pin bias reference
(17.5°C w/ 103AT), TS_ISET_COOL = 10
or TS_TH1_TH2_TH3 = 010
63.7
64.2
64.7
%
As Percentage to TS pin bias reference
(22.5°C w/ 103AT), TS_ISET_COOL = 11
or TS_TH1_TH2_TH3 = 011
60.6
61.1
61.6
%
As Percentage to TS pin bias reference
(15°C w/ 103AT), TS_TH1_TH2_TH3 =
000, 001, 100, 101
65.0
65.5
66.0
%
As Percentage to TS pin bias reference
(20°C w/ 103AT), TS_TH1_TH2_TH3 =
010, 011, 110, 111
61.9
62.4
62.9
%
As Percentage to TS pin bias reference
(17.5°C w/ 103AT), TS_TH1_TH2_TH3 =
000, 001, 100, 101
63.7
64.2
64.7
%
As Percentage to TS pin bias reference
(22.5°C w/ 103AT), TS_TH1_TH2_TH3 =
010, 011, 110, 111
60.6
61.1
61.6
%
As Percentage to TS pin bias reference
(35°C w/ 103AT), TS_TH4_TH5_TH6 =
000, 001, 010, 100, 101
51.5
52.0
52.5
%
As Percentage to TS pin bias reference
(40°C w/ 103AT), TS_TH4_TH5_TH6 =
011, 110, 111
47.9
48.4
48.9
%
As Percentage to TS pin bias reference
(32.5°C w/ 103AT), TS_TH4_TH5_TH6 =
000, 001, 010, 100, 101
53.3
53.8
54.3
%
As Percentage to TS pin bias reference
(37.5°C w/ 103AT), TS_TH4_TH5_TH6 =
011, 110, 111
49.2
49.7
50.2
%
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VTS_WARM
VTS_WARMZ
VTS_HOT
VTS_HOTZ
TEST CONDITIONS
TS pin falling voltage threshold
for TH5 comparator to
transition from TS_PREWARM to
TS_WARM. TS_WARM charging
settings used below this voltage.
TS pin rising voltage threshold
for TH5 comparator to
transition from TS_WARM to
TS_PREWARM. TS_PREWARM
charging settings resume above
this voltage.
TS pin falling voltage threshold
for TH6 comparator to
transition from TS_WARM to
TS_HOT. Charging is suspended
below this voltage.
TS pin rising voltage threshold
for TH6 comparator to
transition from TS_HOT to
TS_WARM. TS_WARM charging
settings resume above this
voltage.
MIN
TYP
MAX UNIT
As Percentage to TS pin bias reference
(40°C w/ 103AT), TS_ISET_WARM = 00
or TS_TH4_TH5_TH6 = 000, 100
47.9
48.4
48.9
%
As Percentage to TS pin bias reference
(45°C w/ 103AT), TS_ISET_WARM = 01
or TS_TH4_TH5_TH6 = 001, 101, 110
44.3
44.8
45.3
%
As Percentage to TS pin bias reference
(50°C w/ 103AT), TS_ISET_WARM = 10
or TS_TH4_TH5_TH6 = 010, 111
40.7
41.2
41.7
%
As Percentage to TS pin bias reference
(55°C w/ 103AT), TS_ISET_WARM = 11
or TS_TH4_TH5_TH6 = 011
37.2
37.7
38.2
%
As Percentage to TS pin bias reference
(37.5°C w/ 103AT), TS_ISET_WARM =
00 or TS_TH4_TH5_TH6 = 000, 100
49.2
49.7
50.2
%
As Percentage to TS pin bias reference
(42.5°C w/ 103AT), TS_ISET_WARM =
01 or TS_TH4_TH5_TH6 = 001, 101, 110
45.6
46.1
46.6
%
As Percentage to TS pin bias reference
(47.5°C w/ 103AT), TS_ISET_WARM =
10 or TS_TH4_TH5_TH6 = 010, 111
42.0
42.5
43.0
%
As Percentage to TS pin bias reference
(52.5°C w/ 103AT), TS_ISET_WARM =
11 or TS_TH4_TH5_TH6 = 011
38.5
39
39.5
%
As Percentage to TS pin bias reference
(50°C w/ 103AT), TS_TH4_TH5_TH6 =
100 or 101
40.7
41.2
41.7
%
As Percentage to TS pin bias reference
(60°C w/ 103AT), Fixed JEITA threshold
or TS_TH4_TH5_TH6 = 000, 001, 010,
011, 110 or 111
33.9
34.4
34.9
%
As Percentage to TS pin bias reference
(47.5°C w/ 103AT), TS_TH4_TH5_TH6 =
100 or 101
42.0
42.5
43.0
%
As Percentage to TS pin bias reference
(57.5°C w/ 103AT), Fixed JEITA threshold
or TS_TH4_TH5_TH6 = 000, 001, 010,
011, 110 or 111
35.2
35.7
36.2
%
As Percentage to TS pin bias reference
(–20°C w/ 103AT), TS_TH_OTG_COLD =
0
79.5
80.0
80.5
%
As Percentage to TS pin bias reference
(–10°C w/ 103AT), TS_TH_OTG_COLD =
1
76.6
77.1
77.6
%
As Percentage to TS pin bias reference
(–15°C w/ 103AT), TS_TH_OTG_COLD =
0
78.2
78.7
79.2
%
As Percentage to TS pin bias reference
(–5°C w/ 103AT), TS_TH_OTG_COLD =
1
75.0
75.5
76.5
%
THERMISTOR COMPARATORS (OTG MODE)
VTS_ OTG_ COLD
VTS_OTG_COLDZ
TS pin rising voltage
threshold to transition
from TS_OTG_NORMAL to
TS_OTG_COLD. OTG suspended
above this voltage.
TS pin falling voltage threshold
to transition from TS_OTG_COLD
to TS_OTG_NORMAL. OTG
resumes below this voltage.
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VTS_OTG_HOT
VTS_OTG_HOTZ
TEST CONDITIONS
TS pin falling voltage
threshold to transition
from TS_OTG_NORMAL to
TS_OTG_HOT. OTG suspended
below this voltage.
TS pin rising voltage threshold
to transition from TS_OTG_HOT
to TS_OTG_NORMAL. OTG
resumes above this threshold.
MIN
TYP
MAX UNIT
As Percentage to TS pin
bias reference (55°C w/ 103AT),
TS_OTG_HOT = 00
37.2
37.7
38.2
%
As Percentage to TS pin bias reference
(60°C w/ 103AT), TS_OTG_HOT = 01
33.9
34.4
34.9
%
As Percentage to TS pin bias reference
(65°C w/ 103AT), TS_OTG_HOT = 10
30.8
31.3
31.8
%
As Percentage to TS pin bias reference
(52.5°C w/ 103AT), TS_OTG_HOT = 00
38.5
39.0
39.5
%
As Percentage to TS pin bias
reference (57.5°C w/ 103AT),
TS_OTG_HOT = 01
35.2
35.7
36.2
%
As Percentage to TS pin bias
reference (62.5°C w/ 103AT),
TS_OTG_HOT = 10
32.0
32.5
33.0
%
Oscillator frequency
1.35
1.5
SWITCHING CONVERTER
FSW
PWM switching frequency
1.65 MHz
MOSFET TURN-ON RESISTANCE
RQ1_ON
VBUS to PMID on resistance
Tj = –40°C-85°C
26
34
mΩ
RQ2_ON
Buck high-side switching MOSFET
turn on resistance between PMID Tj = –40°C-85°C
and SW
55
78
mΩ
RQ3_ON
Buck low-side switching MOSFET
turn on resistance between SW
Tj = –40°C-85°C
and PGND
60
90
mΩ
9.6
V
OTG MODE CONVERTER
VOTG_RANGE
Typical OTG mode voltage
regulation range
VOTG_STEP
Typical OTG mode voltage
regulation step
VOTG_ACC
OTG mode voltage regulation
accuracy
IVBUS = 0A, VOTG = 9V
–2
2
%
VOTG_ACC
OTG mode voltage regulation
accuracy
IVBUS = 0A, VOTG = 5V
–3
3
%
IOTG_RANGE
Typical OTG mode current
regulation range
0.1
3.2
A
IOTG_STEP
Typical OTG mode current
regulation step
IOTG_ACC
OTG mode current regulation
accuracy
3.8
80
mV
20
IOTG = 1.8A
VOTG_UVP
OTG mode undervoltage falling
threshold at PMID
VOTG_VBUS_OVP
OTG mode overvoltage rising
threshold at VBUS
–3
mA
3
%
IOTG = 1.5A
–5
5
%
IOTG = 0.5A
–10
10
%
3.4
10.5
11.0
VVBUS = 5V, IREGN = 20mA
4.4
4.6
VVBUS = 9V, IREGN = 20mA
4.8
5.0
V
11.5
V
REGN LDO
VREGN
REGN LDO output voltage
VREGNZ_OK
REGN not good falling threshold
IREGN_LIM
REGN LDO current limit
14
V
5.2
V
Converter switching
3.2
V
Converter not switching
2.3
V
VVBUS = 5V, VREGN = 4.3V
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ITS_BIAS_FAULT
Rising threshold to transition from
TSBIAS good condition to fault
condition
REGN=5V; ISINK applied on TS_BIAS
pin
2.5
4.5
8
mA
ITS_BIAS_FAULTZ
Falling threshold to transition from
REGN=5V; ISINK applied on TS_BIAS
TSBIAS fault condition to good
pin
condition
2
3.85
7
mA
ADC MEASUREMENT ACCURACY AND PERFORMANCE
tADC_CONV
Conversion-time, Each
Measurement
ADC_SAMPLE = 00
24
ms
ADC_SAMPLE = 01
12
ms
ADC_SAMPLE = 10
6
ms
ADC_SAMPLE = 11
ADCRES
Effective Resolution
3
ms
12
bits
10
11
bits
9
10
bits
8
9
bits
ADC_SAMPLE = 00
11
ADC_SAMPLE = 01
ADC_SAMPLE = 10
ADC_SAMPLE = 11
ADC MEASUREMENT RANGE AND LSB
IBUS_ADC
ADC Bus Current Reading (both
forward and OTG)
VBUS_ADC
ADC VBUS Voltage Reading
VPMID_ADC
ADC PMID Voltage Reading
VBAT_ADC
ADC BAT Voltage Reading
VSYS_ADC
ADC SYS Voltage Reading
IBAT_ADC
ADC BAT Current Reading
TS_ADC
TDIE_ADC
Range
–4
LSB
Range
0
LSB
Range
Range
ADC TS Voltage Reading
Range as a percent of REGN (–40 ℃ to
85 ℃ for 103AT)
ADC TS Voltage Reading
LSB
ADC Die Temperature Reading
Range
19.85
0
V
mV
5.572
1.99
0
V
mV
5.572
1.99
-7.5
LSB
V
mV
3.97
LSB
Range
19.85
0
LSB
A
mA
3.97
LSB
Range
4
2
V
mV
4.0
2
20.9
A
mA
83.2
%
150
°C
0.0961
–40
LSB
%
0.5
°C
I2C INTERFACE (SCL, SDA)
VIH
Input high threshold level, SDA
and SCL
VIL
Input low threshold level, SDA and
SCL
VOL_SDA
Output low threshold level
Sink current = 5mA, 1.2V VDD
IBIAS
High-level leakage current
Pull up rail 1.8V
CBUS
Capacitive load for each bus line
0.78
V
0.42
V
0.3
V
1
µA
400
pF
0.3
V
1
µA
LOGIC OUTPUT PIN (INT , PG, STAT)
VOL
Output low threshold level
Sink current = 5mA
IOUT_BIAS
High-level leakage current
Pull up rail 1.8V
LOGIC INPUT PIN (CE, QON)
VIH_CE
Input high threshold level, /CE
0.78
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIL_CE
Input low threshold level, /CE
IIN_BIAS_CE
High-level leakage current, /CE
VIH_QON
Input high threshold level, /QON
VIL_QON
Input low threshold level, /QON
VQON
Internal /QON pull up
RQON
Internal /QON pull up resistance
MIN
TYP
Pull up rail 1.8V
MAX UNIT
0.4
V
1
µA
1.3
V
0.4
/QON is pulled up internally
V
5
V
250
kΩ
8.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VBUS / VBAT POWER UP
tVBUS_OVP_PROP
VBUS_OVP propagation delay to
stop converter, VBUS rising (no
deglitch)
130
ns
tVBUS_OVP
VBUS OVP deglitch time
to set VBUS_OVP_STAT and
VBUS_OVP_FLAG
200
µs
tPOORSRC
Bad adapter detection duration
30
ms
tPOORSRC_RETRY
Bad adapter detection retry wait
time
2
s
tPOORSRC_RESTART
Restart the bad adapter detection
after latchoff
15
min
tVBUS_PD
The duration of the pull down
current source applied on VBUS
30
ms
50
ms
256
ms
BATTERY CHARGER
tTERM_DGL
Deglitch time for charge
termination
tRECHG_DGL
Deglitch time for recharge
threshold at VBAT falling
tTOP_OFF
Typical top-off timer accuracy
tSAFETY_TRKCHG
Charge safety timer accuracy in
trickle charge
tSAFETY_PRECHG
Charge safety timer accuracy in
pre-charge
12
15
18
min
24
30
36
min
36
45
54
min
0.85
1
1.1
hr
PRECHG_TMR = 0
1.75
2
2.2
hr
PRECHG_TMR = 1
0.43
0.5
0.55
hr
Charge safety timer accuracy in
fast charge
CHG_TMR = 0
10.5
11.5
12.5
hr
CHG_TMR = 1
21.0
22.5
24.5
hr
Time after writing to
BATFET_CTRL before BATFET
turned off for ship mode or
shutdown
BATFET_DLY = 1
10
s
tBATFET_DLY
BATFET_DLY = 0
20
ms
tSM_EXIT
Deglitch time for QON to be pulled
low in order to exit from Ship
Mode
tQON_RST
Time QON is held low to initiate
system power reset
tBATFET_RST
Duration that BATFET is disabled
during system power reset
tSAFETY
BATFET CONTROL
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0.55
0.65
0.75
s
9.0
10
11.5
s
350
ms
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8.6 Timing Requirements (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
I2C INTERFACE
fSCL
SCL clock frequency
1.0 MHz
DIGITAL CLOCK AND WATCHDOG
tLP_WDT
Watchdog Reset time (EN_HIZ =
1, WATCHDOG = 160s)
100
160
s
tWDT
Watchdog Reset time (EN_HIZ =
0, WATCHDOG = 160s)
136
160
s
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8.7 Typical Characteristics
CVBUS = 1µF, CPMID= 10µF, CSYS= 20µF, CBAT= 1µF, L= 1µH (unless otherwise specified)
100
100
95
90
85
VBUS = 5V
VBUS = 9V
VBUS = 12V
VBUS = 15V
80
System Efficiency (%)
Charge Efficiency (%)
95
90
85
80
75
70
VBUS = 5V
VBUS = 9V
VBUS = 12V
VBUS = 15V
65
60
75
55
0
0.5
1
VBAT = 3.8
1.5
2
2.5
Charge Current (A)
3
3.5
5
DCR = 15mΩ
10
50
100
System Current (mA)
VSYSMIN = 3.52V
Figure 8-1. Charge Efficiency vs. Charge Current
500
1000
DCR = 15mΩ
Figure 8-2. System Light Load Efficiency vs. System Current
100
10
VBAT = 3.0V
VBAT = 3.8V
8
95
4
Accuracy (%)
Boost Efficiency (%)
6
90
85
80
0
-2
-4
75
-6
VBAT = 3.2V
VBAT = 3.8V
VBAT = 4.2V
70
-8
-10
65
5
10
50
100
Boost Current (mA)
VOTG = 5.04V
500
0
1000 2000
1
1.5
2
ICHG Setting (A)
2.5
3
3.5
Figure 8-4. Charge Current Accuracy vs. ICHG Setting
4.3
4.35
4.2
4.3
4.1
System Voltage (V)
4.4
4.25
4.2
4.15
4.1
4
3.9
3.8
3.7
VREG = 4.1V
VREG = 4.2V
VREG = 4.35V
4.05
4
-40
0.5
VBUS = 5V
DCR = 15mΩ
Figure 8-3. Boost Mode Efficiency vs. Boost Output Current
Charge Voltage (V)
2
3.6
VBAT = 3.2V (SYSMIN)
VBAT = 4.2V (Charge Done)
3.5
-20
0
20
40
Temperature ( C)
60
80
100
Figure 8-5. Charge Voltage Accuracy vs. VREG Setting
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
System Current (A)
0.8
0.9
1
VBUS = 12V
Figure 8-6. System Load Regulation for SYSMIN and After
Charge Done
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8.7 Typical Characteristics (continued)
CVBUS = 1µF, CPMID= 10µF, CSYS= 20µF, CBAT= 1µF, L= 1µH (unless otherwise specified)
3
1
-1
-40 C
25 C
85 C
2
Accuracy (%)
Accuracy (%)
-3
-5
-7
-9
1
0
-1
-11
-40 C
25 C
85 C
-13
-15
0.75
1
1.25
1.5
1.75 2 2.25 2.5
IINDPM Setting (A)
2.75
3
-2
3.25
-3
4.5
VBUS = 5V
5
5.5
6
6.5
7
7.5
VOTG Setting (V)
8
8.5
9
9.5
VBAT = 3.8V
Figure 8-7. Input Current Regulation Accuracy vs. IINDPM
Setting
Figure 8-8. Boost Voltage Regulation vs VOTG Setting
10
-40 C
25 C
85 C
8
6
Accuracy (%)
4
2
0
-2
-4
-6
-8
-10
0.5
1
VBAT = 3.8V
1.5
IOTG Setting (A)
2
2.5
VOTG = 5.04V
Figure 8-9. Boost Current Regulation Accuracy vs. IOTG Setting
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9 Detailed Description
9.1 Overview
BQ25620 and BQ25622 are highly-integrated 3.5A switch-mode battery chargers for single-cell Li-ion and
Li-polymer batteries. The device includes input reverse-blocking FET (RBFET, Q1), high-side switching FET
(HSFET, Q2), low-side switching FET (LSFET, Q3), battery FET (BATFET, Q4), and bootstrap diode for the
high-side gate driver.
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9.2 Functional Block Diagram
PMID
VBUS
VVBUS_UVLO
IBUS
VVBUS
VBAT + VSLEEP
VVBUS
VVBUS
VVBUS_OV
RBFET (Q1)
+
VBUS_UVLO
Q1 Gate
Control
–
+
REGN
EN_REGN
SLEEP
REGN
LDO
–
EN_HIZ
+
VBUS_OV
–
BTST
VO_REF
VVBUS
VVBUS
VOTG
VVBUS
VINDPM
IBUS
IINDPM
IC_TJ
TREG
SYS
VSYSMIN
VOTG_OVP
+
IQ2
–
VOTG_HSZCP
–
IQ3
+
VOTG_BAT
+
+
VBUS_OVP_BOOST
–
+
Q2_UCP_BOOST
SW
+
Q3_OCP_BOOST
–
BATSNS
–
VBAT_OVP
+
–
+
+
–
–
+
–
HSFET (Q2)
–
ILSFET_UCP
BATSNS
VBAT_REG
IQ3
+
BATOVP
REGN
CONVERTER
Control
LSFET (Q3)
–
+
UCP
+
Q2_OCP
–
–
ICHG
EN_HIZ
REFRESH
ICHG_REG
EN_CHG
+
–
GND
IQ2
IHSFET_OCP
VBTST - VSW
VBTST_REFRESH
SYS
EN_OTG
GND
ICHG
VBAT_REG
ICHG_REG
REF
DAC
Converter
Control State
Machine
+
POORSRC
–
+
TSHUT
ILIM
D+
D-
–
Input
Source
Detection
VPOORSRC
BAT
VVBUS
IC_TJ
BATSNS
TSHUT
IBUS
VBUS
VPMID
IBAT
USB
Adapter
ADC
BATFET
(Q4)
Q4 Gate
Control
BATSNS
AMP
VQON
VBAT
VSYS
VTS
PG
QON
TDIE
RECHRG
+
–
STAT
TERMINATION
CHARGE
CONTROL
STATE
MACHINE
–
BATLOWV
BATSHORT
SUSPEND
SCL
SDA
+
–
INT
I2C
Interface
+
+
–
VREG -VRECHG
BQ25620 / 622
Block Diagram
BATSNS
ICHG
ITERM
VBAT_LOWV
REGN
TS_BIAS
BATSNS
VBAT_SHORT
BATSNS
VTS
Battery
Temperature
Sensing
TS
CE
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9.3 Feature Description
9.3.1 Power-On-Reset (POR)
BQ25620 and BQ25622 power internal bias circuits from the higher voltage of VBUS and BAT. When either
voltage rises above its undervoltage lockout (UVLO) threshold, all registers are reset to their POR values and
the I2C interface is enabled for communication. A non-maskable INT pulse is generated, after which the host can
access all of the registers.
9.3.2 Device Power Up from Battery
If only the battery is present and the VBAT is above depletion threshold (VBAT_UVLOZ), BQ25620 and BQ25622
perform a power-on reset then turns on the BATFET to connect the battery to system. The REGN LDO output
remains off to minimize the quiescent current. The low RDSON of BATFET and the low quiescent current on BAT
minimize the conduction loss and maximize the battery run time.
9.3.3 Device Power Up from Input Source
When a valid input source is plugged in with VBAT < VBAT_UVLOZ, BQ25620 and BQ25622 perform a power-on
reset then checks the input source voltage to turn on the REGN LDO and all the bias circuits. It detects and sets
the input current limit before the buck converter is started. The power up sequence from input source is as listed:
1. REGN LDO power up (Section 9.3.3.1)
2. Poor source qualification (Section 9.3.3.2)
3. Input source type detection using D+/D– to set input current limit (IINDPM) register and input source type
(Section 9.3.3.3)
4. Input voltage limit threshold setting (Section 9.3.3.5)
5. Converter power-up (Section 9.3.3.6)
9.3.3.1 REGN LDO Power Up
The REGN LDO regulator supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN
LDO also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well.
The REGN is enabled when all the below conditions are valid:
•
•
•
•
VBUS above VVBUS_UVLOZ
VBUS above VBAT + VSLEEPZ
EN_HIZ = 0
After 220-ms delay is completed
If any one of the above conditions is not valid, the REGN LDO and the converter power stage remain off with the
converter disabled. In this state, the battery supplies power to the system.
9.3.3.2 Poor Source Qualification
After the REGN LDO powers up, the device checks the current capability of the input source. The input source
has to meet the following requirements in order to move forward to the next power on steps.
1. VBUS voltage below VVBUS_OVP
2. VBUS voltage above VPOORSRC when pulling IPOORSRC
Once these conditions are met, BQ25620 and BQ25622 proceed to input source type detection.
If a poor source is detected (when pulling IPOORSRC, VVBUS drops below VPOORSRC), BQ25620 and BQ25622
wait for tPOORSRC_RETRY and then repeat the poor source qualification routine. After 7 consecutive failures, the
device sets EN_HIZ = 1 and goes to HIZ mode. VBUS_STAT remains at 000 (not powered from VBUS) and
there is no change to VBUS_FLAG.
After tPOORSRC_RESTART (15 minutes typical) in HIZ latchoff from seven consecutive poor source failures, the poor
source detection routine restarts.
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9.3.3.3 D+/D– Detection Sets Input Current Limit (BQ25620 Only)
After the REGN LDO is powered, the adapter has been qualified as a good source, and AUTO_INDET_EN bit
= 1 (POR default), BQ25620 runs input source detection through D+/D– lines to detect USB Battery Charging
Specification 1.2 (BC1.2) input sources (CDP / SDP / DCP) and non-standard adapters. If DCP is detected,
BQ25620 runs HVDCP detection if either EN_9V or EN_12V is 1. The detection algorithm runs automatically
each time that VBUS is plugged in, updating the IINDPM according to Table 9-2. If AUTO_INDET_EN = 0, the
detection algorithm is not run and IINDPM remains unchanged. The host can force the detection algorithm to run
and update IINDPM by setting FORCE_INDET to 1.
The USB BC1.2 is able to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and
Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the
non-standard adapter detection is applied to set the input current limit.
The secondary detection is used to distinguish two types of charging ports (CDP and DCP). Most of the time, a
CDP requires the portable device (such as smart phone, tablet) to send back an enumeration within 2.5 seconds
of CDP plug-in. Otherwise, the port reverts back to SDP even though the D+/D– detection indicates CDP.
Upon the completion of input source type detection, the following registers are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. VBUS_STAT bits are updated to indicate the detected input source type
After detection completes, the host can over-write the IINDPM register to change the input current limit if
needed.
Divider 1: 1A
Divider 2: 2.1A
Divider 3: 2.4A
Divider 4: 1A
Non-Standard
Adapter
Adapter Plug-in
or
FORCE_INDET
Data Contact
Detec on
VBUS Detecon
Primary Detecon
DCP/CDP
Secondary
Detection
DCP
(1.5A)
HVDCP
(1.5A)
HVDCP
USB BC1.2 Standard
SDP
(500mA)
CDP
(1.5A)
DCP
(1.5A)
Figure 9-1. D+/D– Detection Flow
If DCP is detected (VBUS_STAT = 011), BQ25620 turns on VD+D-_0p6V_SRC on D+ if EN_DCP_BIAS is set to
1. Setting EN_DCP_BIAS to 0 while VBUS_STAT = 011 disables the VD+D-_0p6V_SRC on D+ pin, and setting
EN_DCP_BIAS to 1 while VBUS_STAT = 011 enables the VD+D-_0p6V_SRC on D+ pin. The EN_HIZ bit has priority
over EN_DCP_BIAS.
High Voltage Dedicated Charging Port (HVDCP) is used to negotiate either 9V or 12V from the power source if
BC1.2 DCP support is detected.
In order to remain in 9V or 12V HVDCP, BQ25620 must maintain a bias on D+ and D-, resulting in higher
quiescent current. The host may remove this bias and associated quiescent current by setting EN_9V and
EN_12V to 0 at any time. Setting EN_9V and EN_12V to 0 when an HVDCP adapter is providing either 9V or
12V causes the adapter to revert to 5V DCP operation.
The non-standard detection is used to distinguish vendor specific adapters based on their unique dividers on the
D+/D- pins. Comparators detect the voltage applied on each pin and determine the input current limit according
to Table 9-1.
Table 9-1. Non-Standard Adapter Detection
NON-STANDARD ADAPTER
D+ THRESHOLD
D– THRESHOLD
INPUT CURRENT
LIMIT (A)
Divider 1
VD+ within VD+D-_2p0
VD– within VD+D-_2p8
1
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Table 9-1. Non-Standard Adapter Detection (continued)
NON-STANDARD ADAPTER
D+ THRESHOLD
D– THRESHOLD
INPUT CURRENT
LIMIT (A)
Divider 2
VD+ within VD+D-_2p8
VD– within VD+D-_2p0
2.1
Divider 3
VD+ within VD+D-_2p8
VD– within VD+D-_2p8
2.4
Table 9-2. Input Current Limit Setting from D+/D– Detection
D+/D– DETECTION
INPUT CURRENT LIMIT (IINLIM)
VBUS_STAT
USB SDP (USB500)
500 mA
0x1
USB CDP
1.5 A
0x2
USB DCP
1.5 A
0x3
Divider 1
1A
0x5
Divider 2
2.1 A
0x5
Divider 3
2.4 A
0x5
HVDCP
1.5 A
0x6
Unknown 5-V Adapter
500mA
0x4
9.3.3.4 ILIM Pin (BQ25622 Only)
The ILIM pin clamps the input current limit to IINREG = KILIM / RILIM, where RILIM is connected from the ILIM pin
to GND. The ILIM pin can be used to limit the input current limit from 100 mA - 3.2 A. The input current is limited
to the lower of the two values set by the ILIM pin and IINDPM register bits. The ILIM pin can also be used to
monitor input current. The input current is proportional to the voltage on the ILIM pin and can be calculated by
IIN = (KILIM x VILIM) / (RILIM x 0.8). The ILIM pin function is disabled when the EN_EXTILIM bit is set to 0.
An RC filter in parallel with RILIM is required when the input current setting on the ILIM pin is either:
•
•
below 400 mA or
above 2 A when using a 2.2-μH inductor
The value for the RC filter is 1.2 kΩ and 330 nF, respectively.
9.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
BQ25620 and BQ25622 support a wide range of input voltage limit (3.8 V – 16.8V). Its POR default VINDPM
threshold is set at 4.6V. BQ25620 and BQ25622 also support dynamic VINDPM tracking, which tracks the
battery voltage to ensure a sufficient margin between input and battery voltages for proper operation of the buck
converter. This function is enabled via the VINDPM_BAT_TRACK register bit. When enabled, the actual input
voltage limit is the higher of the VINDPM register or VINDPM_BAT_TRACK (VBAT + 400 mV typical offset.)
9.3.3.6 Converter Power-Up
After the input current and voltage limits are set, the converter is enabled and the HSFET and LSFET start
switching. If battery charging is disabled, the BATFET turns off. Otherwise, the BATFET stays on to charge the
battery. Converter startup requires the following conditions:
• VBUS has passed poor source qualification ( Section 9.3.3.2 )
• VBUS > VBAT + VSLEEPZ
• VVBUS < VVBUS_OVP
• EN_HIZ = 0
• VSYS < VSYS_OVP
• TJ < TSHUT
BQ25620 and BQ25622 provide soft start when the system rail is ramped up by setting IINDPM to its lowest
programmable value and stepping up through each available setting until reaching the value set by IINDPM
register. Concurrently, the system short protection limits the output current to approximately 0.5A when the
system rail is below VSYS_SHORT.
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These devices use a highly efficient 1.5 MHz, fixed frequency pulse width modulated (PWM) step-down
switching regulator. The internally compensated feedback loop keep tight control of the switching frequency
under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter
design.
The device switches to pulse frequency modulation (PFM) control at light load condition. The PFM_FWD_DIS
and PFM_OTG_DIS bits can be used to disable the PFM operation in buck and boost respectively.
9.3.4 Power Path Management
BQ25620 and BQ25622 accommodate a wide range of input sources from USB, wall adapter, wireless charger,
to car charger. They provide automatic power path selection to supply the system from input source, battery, or
both.
9.3.4.1 Narrow VDC Architecture
BQ25620 and BQ25622 use the Narrow VDC architecture (NVDC) with BATFET separating system from battery.
The minimum system voltage is set by VSYSMIN register setting. Even with a fully depleted battery, the system
is regulated to the minimum system voltage. If charging is enabled, the BATFET operates in linear mode (LDO
mode). The default minimum system voltage at POR is 3.52 V.
As the battery voltage rises above the minimum system voltage, the BATFET is turned fully on. When battery
charging is disabled and VBAT is above the minimum system voltage setting, or charging is terminated, the
system is regulated 50mV (typical) above battery voltage.
9.3.4.2 Dynamic Power Management
To meet the USB maximum current limit and avoid overloading the adapter, the device features Dynamic Power
Management (DPM), which continuously monitors the input current and input voltage. When the input source
is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below the input
voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input
current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts
to drop. Once the system voltage falls below the battery voltage by VSUPP, the device automatically enters the
supplement mode where the BATFET turns on and the battery starts discharging so that the system is supported
from both the input source and battery.
9.3.4.3 High Impedance Mode
The host may place BQ25620 and BQ25622 into high impedance mode by writing EN_HIZ = 1. In high
impedance mode, RBFET (Q1), HSFET (Q2) and LSFET (Q3) are turned off. The RBFET and HSFET block
current flow to and from VBUS, putting the VBUS pin into a high impedance state. The BATFET (Q4) is turned
on to connect the BAT to SYS. During high impedance mode, REGN is disabled and the digital clock is slowed to
conserve power.
9.3.5 Battery Charging Management
BQ25620 and BQ25622 charge 1-cell Li-Ion battery with up to 3.5 A charge current. The 15 mΩ BATFET
improves charging efficiency and minimizes the voltage drop during discharging.
9.3.5.1 Autonomous Charging Cycle
When battery charging is enabled (EN_CHG bit = 1 and CE pin is LOW), BQ25620 and BQ25622 autonomously
complete a charging cycle without host involvement. The device default charging parameters are listed in Table
9-3. The host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
Table 9-3. Charging Parameter Default Setting
BQ25620
VREG
VRECHG
ITRICKLE
IPRECHG
ICHG
ITERM
TOPOFF
TIMER
4.2V
VREG - 100 mV
20 mA
100 mA
1040 mA
60 mA
Disabled
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Table 9-3. Charging Parameter Default Setting (continued)
BQ25622
VREG
VRECHG
ITRICKLE
IPRECHG
ICHG
ITERM
TOPOFF
TIMER
4.2V
VREG - 100 mV
20 mA
100 mA
1040 mA
60 mA
Disabled
A new charge cycle starts when the following conditions are valid:
•
•
•
•
•
Converter starts per the conditions in Section 9.3.3.6
EN_CHG = 1
CE pin is low
No thermistor fault on TS
No safety timer fault
BQ25620 and BQ25622 automatically terminate the charging cycle when the charging current is below
termination threshold, battery voltage is above recharge threshold, and device not is in DPM or thermal
regulation. When a fully charged battery is discharged below VRECHG, the device automatically starts a new
charging cycle. After charging terminates, toggling CE pin or EN_CHG bit also initiates a new charging cycle.
The STAT output indicates the charging status. Refer to Section 9.3.8.2 for details of STAT pin operation.
In addition, the status register (CHG_STAT) indicates the different charging phases: 00-charging disabled or
terminated, 01-constant current, 10 constant voltage, 11-topoff charging.
9.3.5.2 Battery Charging Profile
BQ25620 and BQ25622 charges the battery in five phases: trickle charge, pre-charge, constant current, constant
voltage and an optional top-off charging phase. At the beginning of a charging cycle, the device checks the
battery voltage and regulates current and voltage accordingly.
Regulaon Voltage
VREG
Baery Voltage
Charge Current
ICHG
Charge Current
VBAT_LOWVZ (3 V)
VBAT_SHORTZ (2.25 V)
IPRECHG
ITERM
IBAT_SHORT
Trickle Charge
Pre-charge
Fast Charge and Voltage Regula on
Top-o Timer
(oponal)
Safety Timer
Expiraon
Figure 9-2. Battery Charging Profile
9.3.5.3 Charging Termination
BQ25620 and BQ25622 terminate a charge cycle when the battery voltage is above recharge threshold, the
converter is in constant-voltage regulation and the current is below ITERM. Because constant-voltage regulation
is required for termination, BQ25620 and BQ25622 do not terminate while IINDPM, VINDPM or thermal
regulation loops are active. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and the BATFET can turn on again to engage supplement mode. Termination can
be permanently disabled by writing 0 to EN_TERM bit prior to charge termination.
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At low termination currents, due to the comparator offset, the actual termination current may be 10 mA-20 mA
higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer
can be applied after termination is detected. The top-off timer follows safety timer constraints, such that if the
safety timers suspend, so does the top-off timer. Similarly, if the safety timers count at half-clock rate, so does
the top-off timer. Refer to Section 9.3.5.5 for the list of conditions. The host can read CHG_STAT to find out the
termination status.
Top-off timer gets reset by any of the following conditions:
1. Charging cycle stop and restart (toggle CE pin, toggle EN_CHG bit, charged battery falls below recharge
threshold or adapter removed and replugged)
2. Termination status low to high
3. REG_RST register bit is set
The top-off timer settings are read in after is detected by the charger. Programming a top-off timer value after
termination has no effect unless a recharge cycle is initiated. CHG_FLAG is set to 1 when entering top-off timer
segment and again when the top-off timer expires.
9.3.5.4 Thermistor Qualification
BQ25620 and BQ25622 provide a single thermistor input for battery temperature monitoring. The TS pin input of
the battery temperature can be ignored by the charger if TS_IGNORE = 1. When the TS pin feedback is ignored,
the charger considers the TS to always be valid for charging and OTG modes, and TS_STAT always reports
000. The TS pin may be left floating if TS_IGNORE is set to 1.
When TS_IGNORE=1, the TS_ADC channel is disabled, with TS_ADC_DIS forced to 1; Attempting to write to 0
is ignored.
When TS_IGNORE = 0, the charger adjusts the charging profile based on the TS pin feedback information
according to the configurable profile described in Section 9.3.5.4.1. When the battery temperature crosses from
one temperature range to another, TS_STAT is updated accordingly, and the charger sets the FLAG bit for the
newly-entered temperature range. If TS_MASK is set to 0, any change to TS_STAT, including a transition to
TS_NORMAL, generates an INT pulse.
9.3.5.4.1 Advanced Temperature Profile in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and
high temperature ranges. As battery technology continues to evolve, battery manufacturers have released
temperature safety specifications that extend beyond the JEITA standard. BQ25620 and BQ25622 feature
a highly flexible temperature-based charging profile to meet these advanced specifications while remaining
backwards compatible with the original JEITA standard. Figure 8-3 shows the programmability for charger
behavior under different battery temperature (TS) operating regions.
Percentage of
ICHG / CHG_RATE
Charging Voltage
100%
programmable
programmable
programmable
VREG
VREG -100mV
VREG -200mV
TS_VSET_SYM
VREG -300mV
40%
20%
suspend
TH1
TS_COLD
TH2
TH4
TH3
TS_COOL TS_PRECOOL
TS_NORMAL
TH5
TH6
TS_PREWARM TS_WARM
TS_HOT
TH1
TS_COLD
TH2
TH4
TH3
TS_COOL TS_PRECOOL
TS_NORMAL
TH5
TH6
TS_PREWARM TS_WARM
TS_HOT
TS Temperature
TS Temperature
Figure 9-3. TS Charging Values
Charging safety timer is adjusted within the temperature zones to reflect changes to the charging current. When
IPRECHG and ICHG are reduced to 20% or 40% in the cool or warm temperature zones, the charging safety
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timer counts at half rate. If charging is suspended, the safety timer is suspended, the STAT pin blinks and
CHG_STAT is set to 00 (not charging or charge terminated.)
9.3.5.4.2 TS Pin Thermistor Configuration
The typical TS resistor network is illustrated below.
RT1
REGN
10 kΩ
RT2
TS
Figure 9-4. TS Resistor Network
The value of RT1 and RT2 are determined from the resistance of the thermistor at 0 and 60 ºC (RTH0degC and
RTH60degC) and the corresponding voltage thresholds VTS_0degC and VTS_60degC (expressed as percentage of
REGN with value between 0 and 1.) For the most accurate thermistor curve fitting, use the rising threshold for
VTS_COLD at 0 ºC and the falling threshold for VTS_HOT at 60 ºC, regardless of the actual register settings for
TS_TH1_TH2_TH3 and TS_TH4_TH5_TH6.
1
RTH0degC × RTH60degC × V 1
−
TS_0degC VTS_60degC
RT2 =
1
RTH60degC × V
− 1 − RTH0degC × V 1
−1
TS_60degC
TS_0degC
1
VTS_0degC − 1
RT1 = 1
1
RT2 + RTH0degC
(1)
(2)
Assuming a 103AT NTC thermistor on the battery pack, the RT1 and RT2 are calculated to be 5.30 kΩ and 31.1
kΩ respectively.
9.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
For battery protection during boost OTG, BQ25620 and BQ25622 monitor the battery temperature to be within
the TS_TH_OTG_COLD to TS_TH_OTG_HOT register settings. For a 103AT NTC thermistor with RT1 of 5.3
kΩ and RT2 of 31.1 kΩ, TS_TH_OTG_COLD default is -10°C and TS_TH_OTG_HOT default is 60°C. When
temperature is outside of this range, the OTG mode is suspended with REGN remaining on. In addition,
VBUS_STAT bits are set to 000, TS_STAT is set to 001 (TS_OTG_COLD) or 010 (TS_OTG_HOT), and
TS_FLAG is set. Once the battery temperature returns to normal temperature, the boost OTG is restarted and
TS_STAT returns to 000 (TS_NORMAL).
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Boost Current
Limit
IOTG
Suspended
TH_OTG_COLD
TS_OTG_COLD
TH_OTG_HOT
TS_NORMAL
TS_OTG_HOT
TS Temperature
Figure 9-5. TS Pin Thermistor Sense Threshold in Boost Mode
9.3.5.4.4 JEITA Charge Rate Scaling
The TS_ISET_PRECOOL, TS_ISET_COOL, TS_ISET_PREWARM and TS_ISET_WARM cool and warm
charge current fold backs are based on a 1C charging rate.
A setting of TS_ISET_COOL = 01 sets ICHG_COOL = 20% ICHG1C. When the battery enters the TS_COOL
temperature zone, the current is reduced to 20% of the 1C charging rate. In order to convert the charging
foldback, the host must set the CHG_RATE register to the C rate for the battery. This scales the fold back
accordingly, producing an ICHG_COOL as shown in Equation 3:
ICHG_COOL
ICHG = CHG_RATE
× JEITA_ISETC
(3)
When TS_ISET_PRECOOL, TS_ISET_COOL, TS_ISET_PREWARM or TS_ISET_WARM is set to either 00
(suspend) or 11 (unchanged), the CHG_RATE setting has no effect. A summary is provided in Table 9-4.
Table 9-4. ICHG Fold Back
TS_ISET_PRECOOL, TS_ISET_COOL,
TS_ISET_PREWARM or TS_ISET_WARM
CHG_RATE
FOLD-BACK CURRENT AS PERCENTAGE
OF ICHG
00
Any
0% (Suspended)
01 (20%)
00 (1C)
20%
01 (2C)
10%
10 (4C)
5%
11 (6C)
3.3%
00 (1C)
40%
01 (2C)
20%
10 (4C)
10%
11 (6C)
6.6%
Any
100%
10 (40%)
11
9.3.5.4.5 TS_BIAS Pin (BQ25622 Only)
The BQ25622 has the TS_BIAS pin to isolate the battery temperature sensing thermistor and associated
resistor-divider from REGN. The 103AT thermistor with typical resistor-divider network requires about 400 μA
to bias. The BQ25622 provides the TS_BIAS pin, which is internally connected to the REGN LDO via a back-toback MOSFET switch. When no temperature measurement is being taken, the switch is disabled to disconnect
the thermistor and resistor-divider from the REGN LDO, saving the 400 μA bias current from being expended
unnecessarily.
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The TS_BIAS pin has short-circuit protection. If a short is detected on the TS_BIAS pin, the switch is disabled
to disconnect the short from REGN. If this condition occurs, TS_STAT register is set to 0x3. Charging and OTG
modes are suspended until the short is removed.
9.3.5.5 Charging Safety Timers
BQ25620 and BQ25622 have three built-in safety timers to prevent extended charging cycle due to abnormal
battery conditions. The fast charge safety timer and pre-charge safety timers are set through I2C CHG_TMR and
PRECHG_TMR fields, respectively. The trickle charge timer is fixed at 1 hour.
The trickle charging, pre-charging and fast charging safety timers can be disabled by setting
EN_SAFETY_TMRS = 0. EN_SAFETY_TMRS can be enabled anytime regardless of which charging stage
the charger is in. Each timer starts to count as soon as the following two conditions are simultaneously true:
EN_SAFETY_TMRS=1 and the corresponding charging stage is active.
When either the fast charging, trickle charging or pre-charging safety timer expires, the SAFETY_TMR_STAT
and SAFETY_TMR_FLAG bits are set to 1.
Events that cause a reduction in charging current also cause the charging safety timer to count at half-clock rate
if TMR2X_EN bit is set.
During faults which suspend charging, the charge, pre-charge and trickle safety timers are also suspended,
regardless of the state of the TMR2X_EN bit. Once the fault goes away, charging resumes and the safety timer
resumes from where it stopped.
The charging safety timer and the charging termination can be disabled at the same time. Under this condition,
the charging keeps running until it is disabled by the host.
9.3.6 USB On-The-Go (OTG)
9.3.6.1 Boost OTG Mode
BQ25620 and BQ25622 support boost converter operation to deliver power from the battery to VBUS. The
output voltage and maximum current are set in the VOTG and IOTG registers, respectively. VBUS_STAT is set
to 111 upon a successful entry into boost OTG. The boost operation is enabled when the following conditions are
met:
1.
2.
3.
4.
5.
6.
7.
BAT above VBAT_OTG
VBUS less than VBAT+VSLEEP
Boost mode operation is enabled (EN_OTG = 1)
VTS_OTG_HOT < VTS < VTS_OTG_COLD
VREGN > VREGN_OK
30 ms delay after EN_OTG = 1
Boost mode regulation voltage in REG0x0C is greater than 105% of battery voltage.
9.3.7 Integrated 12-Bit ADC for Monitoring
BQ25620 and BQ25622 provide an integrated 12-bit ADC for the host to monitor various system parameters.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is disabled by default (ADC_EN=0) to conserve
power. The ADC is allowed to operate if either VBUS > VPOORSRC or VBAT > VBAT_LOWV is valid. If ADC_EN
is set to ‘1’ before VBUS or VBAT reach their respective valid thresholds, then ADC_EN stays '0'. When the
charger enters HIZ mode, the ADC is disabled. The host can re-enable the ADC during HIZ mode by setting
ADC_EN =1.
At battery only condition, if the TS_ADC channel is enabled, the ADC only operates when the battery voltage is
higher than 3.2V (the minimal value to turn on REGN), otherwise, the ADC operates when the battery voltage is
higher than VBAT_LOWV.
The ADC_DONE_STAT, ADC_DONE_FLAG bits are set when a conversion is complete in one-shot mode only.
During continuous conversion mode, the ADC_DONE_STAT, ADC_DONE_FLAG bits have no meaning and
remain at 0. In one-shot mode, the ADC_EN bit is set to 0 at the completion of the conversion, at the same time
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as the ADC_DONE_FLAG bit is set. In continuous mode, the ADC_EN bit remains at 1 until the user disables
the ADC by setting it to 0.
9.3.8 Status Outputs ( PG, STAT, INT)
9.3.8.1 PG Pin Power Good Indicator
The PG pin (BQ25620 and BQ25622) goes LOW to indicate a good input source when:
•
•
•
•
VVBUS is above VVBUS_UVLOZ
VVBUS is above battery (not in sleep)
VVBUS is below VVBUS_OVP threshold
VVBUS is above VPOORSRC when IPOORSRC current is applied (not a poor source)
9.3.8.2 Charging Status Indicator (STAT)
BQ25620 and BQ25622 indicates charging state on the open drain STAT pin. The STAT pin can drive an LED.
The STAT pin function can be disabled via the DIS_STAT bit.
Table 9-5. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including recharge)
LOW
Not charging, no fault detected. (Includes charging complete, Charge Disabled, no adapter present, in OTG mode.)
HIGH
Charge suspend
Boost Mode suspend
Blinking at 1 Hz
9.3.8.3 Interrupt to Host ( INT)
In many applications, the host does not continually poll the charger status registers. Instead, the INT pin may
be used to notify the host of a status change with a 256-μs INT pulse. Upon receiving the interrupt pulse,
the host may read the flag registers (Charger_Flag_X and FAULT_Flag_X) to determine the event that caused
the interrupt, and for each flagged event, read the corresponding status registers (Charger_Status_X and
FAULT_Status_X) to determine the current state. Once set to 1, the flag bits remain latched at 1 until they are
read by the host, which clears them. The status bits, however, are updated whenever there is a change to status
and always represent the current state of the system.
All of the INT events can be masked off to prevent INT pulses from being sent out when they occur, with the
exception of the initial power-up interrupt. Interrupt events are masked by setting their mask bit in registers
(Charger_Mask_X and FAULT_Mask_X.) Events always cause the corresponding flag bit to be set to 1,
regardless of whether or not the interrupt pulse has been masked.
9.3.9 BATFET Control
BQ25620 and BQ25622 have an integrated, bi-directionally blocking BATFET that can be turned off to remove
leakage current from the battery to the system. The BATFET is controlled by the BATFET_CTRL register bits,
and supports shutdown mode, ship mode and system power reset.
Table 9-6. BATFET Control Modes
MODE
Normal
BATFET
On
I2C
Active
ENTRY, NO ADAPTER
N/A
ENTRY, WITH ADAPTER, ENTRY, WITH ADAPTER,
BATFET_CTRL_WVBUS BATFET_CTRL_WVBUS
=0
=1
N/A
N/A
EXIT
N/A
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Table 9-6. BATFET Control Modes (continued)
MODE
I2C
BATFET
ENTRY, NO ADAPTER
ENTRY, WITH ADAPTER, ENTRY, WITH ADAPTER,
BATFET_CTRL_WVBUS BATFET_CTRL_WVBUS
=0
=1
EXIT
Ship mode
Off
Off
Writing BATFET_CTRL =
10 turns off BATFET after
BATFET_DLY and enters
ship mode.
Writing BATFET_CTRL =
10 has no effect while
adapter is present. When
both BATFET_DLY has
expired and the adapter
is removed, the device
turns off BATFET and
enters ship mode. Writing
BATFET_CTRL = 00
before adapter is removed
aborts ship mode.
Writing BATFET_CTRL = QON or
10 turns off BATFET
adapter
after BATFET_DLY. When plug-in
both BATFET_DLY has
expired and adapter is
removed, the device
enters ship mode. Writing
BATFET_CTRL = 00
before adapter is removed
turns BATFET on and
aborts ship mode.
System reset
On to Off
to On
Active
Writing BATFET_CTRL
= 11 initiates
system reset after
BATFET_DLY. Holding
QON low for tQON_RST
initiates immediate reset
(BATFET_DLY is not
applied.)
Writing BATFET_CTRL
= 11 is ignored and
BATFET_CTRL resets to
00. Holding QON low for
tQON_RST is ignored.
Writing BATFET_CTRL
N/A
= 11 initiates
system reset after
BATFET_DLY. Holding
QON low for tQON_RST
initiates immediate reset.
Converter is placed in HIZ
during system reset and
exits HIZ when system
reset completes.
Shutdown mode
Off
Off
Writing BATFET_CTRL =
01 turns off BATFET after
BATFET_DLY and enters
shutdown.
Writing BATFET_CTRL = 01 with adapter present
is ignored, regardless of BATFET_CTRL_WVBUS
setting, and BATFET_CTRL is reset to 00.
Adapter
plug-in
9.3.9.1 Shutdown Mode
For the lowest battery leakage current, the host can shut down BQ25620 and BQ25622 by setting the register
bits BATFET_CTRL to 01. In this mode, the BATFET is turned off to prevent the battery from powering the
system, the I2C is disabled and the charger is totally shut down. BQ25620 and BQ25622 can only be woken up
by plugging in an adapter. When the adapter is plugged in, BQ25620 and BQ25622 start back up with all register
settings in their POR default.
After the host sets BATFET_CTRL to 01, the BATFET turns off after waiting either 20 ms or 10 s as configured
by BATFET_DLY register bit. Shutdown mode can only be entered when VVBUS < VVBUS_UVLO, regardless of the
BATFET_CTRL_WVBUS setting, which has no effect on shutdown mode entry. If the host writes BATFET_CTRL
= 01 with VVBUS > VVBUS_UVLOZ, the request is ignored and the BATFET_CTRL bits are set back to 00.
If the host writes BATFET_CTRL to 01 while boost OTG, BQ25620 and BQ25622 first exit from boost OTG by
setting EN_OTG = 0 and then enters shutdown mode.
QON has no effect during shutdown mode. The internal pull-up on the QON pin is disabled during shutdown to
prevent leakage through the pin.
9.3.9.2 Ship Mode
The host may place BQ25620 and BQ25622 into ship mode by setting BATFET_CTRL = 10. In ship mode, the
BATFET is turned off to prevent the battery from powering the system, and the I2C is disabled. Ship mode has
slightly higher quiescent current than shutdown mode, but QON may be used to exit from ship mode. BQ25620
and BQ25622 are taken out of ship mode by either of these methods:
• Pulling the QON pin low for tSM_EXIT
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VVBUS > VVBUS_UVLOZ (adapter plug-in)
When BQ25620 and BQ25622 exit from ship mode, the registers are reset to their POR values.
Ship mode is only entered when the adapter is not present. Setting BATFET_CTRL = 10 while VVBUS >
VVBUS_UVLOZ (adapter present) either disables the BATFET or has no immediate effect depending on the setting
of BATFET_CTRL_WVBUS.
When BATFET_CTRL_WVBUS is set to 0 and VVBUS > VVBUS_UVLO (adapter present), setting BATFET_CTRL
= 10 has no immediate effect. If the adapter is removed while BATFET_CTRL is set to 10, then the BATFET is
disabled and the device enters ship mode. The BATFET turns off either after tBATFET_DLY or when the adapter is
removed, whichever comes later.
When BATFET_CTRL_WVBUS is set to 1 and VVBUS > VVBUS_UVLO (adapter present), setting BATFET_CTRL
= 10 turns off the BATFET after tBATFET_DLY. The converter continues to run while the adapter is present,
supplying SYS power from the adapter. If the adapter is removed while BATFET_CTRL is set to 10, BQ25620
and BQ25622 enters ship mode. Ship mode is entered either after tBATFET_DLY or when the adapter is removed,
whichever comes later.
9.3.9.3 System Power Reset
The BATFET functions as a load switch between battery and system when the converter is not running. By
changing the state of BATFET from on to off, systems connected to SYS can be power cycled. Any of the
following conditions initiates a system power reset:
• BATFET_CTRL_WVBUS = 1 and QON is pulled low for tQON_RST
• BATFET_CTRL_WVBUS = 1 and BATFET_CTRL = 11
• BATFET_CTRL_WVBUS = 0 and VBUS < VVBUS_UVLO simultaneously with QON pulled low for tQON_RST
• BATFET_CTRL_WVBUS = 0 and VBUS < VVBUS_UVLO and BATFET_CTRL = 11
BATFET_CTRL
_WVBUS
Adapter
tQON_RST
tQON_RST
tQON_RST
/QON
ON
ON
BATFET
OFF
ON
OFF
tBATFET_RST
OFF
Enter HIZ tBATFET_RST
BATFET Reset with
BATFET_CTRL_WVBUS=0
Enter HIZ
tBATFET_RST
BATFET Reset with
BATFET_CTRL_WVBUS=1
Figure 9-6. System Power Reset Timing
When BATFET_CTRL_WVBUS is set to 1, system power reset proceeds if either BATFET_CTRL is set to 11 or
QON is pulled low for tQON_RST, regardless of whether VBUS is present or not . There is a delay of tBATFET_DLY
before initiating the system power reset. If QON is pulled low, there is no delay after the tQON_RST completes,
regardless of BATFET_DLY setting.
The system power reset can be initiated from the battery only condition, from OTG mode or from the forward
charging mode with adapter present. If the system power is reset when the charger is in boost OTG mode, the
boost OTG mode is first stopped by setting EN_OTG = 0.
9.4 Device Functional Modes
9.4.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the
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charger is in default mode, WD_STAT bit becomes HIGH, WD_FLAG is set to 1, and an INT is asserted low to
alert the host (unless masked by WD_MASK). The WD_FLAG bit would read as 1 upon the first read and then 0
upon subsequent reads. When the charger is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the
default settings.
In default mode, the device keeps charging the battery with default 1-hour trickle charging safety timer, 2-hour
pre-charging safety timer and the 12-hour fast charging safety timer. At the end of the 1-hour or 2-hour or
12-hour timer expired, the charging is stopped and the buck converter continues to operate to supply system
load.
A write to any I2C register transitions the charger from default mode to host mode, and initiates the watchdog
timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has
to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set),
or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog expires, the device returns to default mode. The ICHG value is divided in half when the
watchdog timer expires, and a number of other fields are reset to their POR default values as shown in the notes
column of the register tables in Section 9.6. When watchdog timer expires, WD_STAT and WD_FLAG is set to 1,
and an INT is asserted low to alert the host (unless masked by WD_MASK).
Reset
Selective
Registers
Default Mode
WD_STAT=1
POR
I2C Write
Reset
Watchdog
Timer
Yes
Host Mode
WD_STAT=0
I2C Write to
WD_RST
No
No
Watchdog Timer Expired?
Yes
Figure 9-7. Watchdog Timer Flow Chart
9.4.2 Register Bit Reset
Beside the register reset by the watchdog timer in the default mode, the register and the timer could be reset to
the default value by writing the REG_RST bit to 1. The register bits, which can be reset by the REG_RST bit, are
noted in the Register Map section. After the register reset, the REG_RST bit goes back from 1 to 0 automatically.
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9.5 Programming
9.5.1 Serial Interface
BQ25620 and BQ25622 uses I2C compatible interface for flexible charging parameter programming and
instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus
lines are required: a serial data line (SDA), and a serial clock line (SCL).
The device has 7-bit I2C address 0x6B , receiving control inputs from a host device such as a micro-controller
or digital signal processor through register addresses 0x02 – 0x38. The host device initiates all transfers and the
charger responds. Register reads outside of these addresses return 0xFF. When the bus is free, both SDA and
SCL lines are HIGH.
The I2C interface supports standard mode (up to 100 kbits/s), fast mode (up to 400 kbits/s) and fast mode plus
(up to 1 Mbits/s.) These lines are pulled up to a reference voltage via pull-up resistor. The device I2C detection
thresholds support a communication reference voltage from 1.2 V to 5 V.
9.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of data
allowed
Figure 9-8. Bit Transfer on the I2C Bus
9.5.1.2 START and STOP Conditions
All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the host. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
STOP (P)
START (S)
Figure 9-9. START and STOP Conditions on the I2C Bus
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9.5.1.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the
Most Significant Bit (MSB) first. If target cannot receive or transmit another complete byte of data until it has
performed some other function, it can hold the SCL line low to force the host into a wait state (clock stretching).
Data transfer then continues when the target is ready for another byte of data and releases the SCL line.
Acknowledgement
signal from host
Acknowledgement
signal from target
MSB
SDA
SCL
1
S or Sr
START or
Repeated
START
2
7
8
9
2
1
8
9
ACK
P or Sr
ACK
STOP or
Repeate
d START
Figure 9-10. Data Transfer on the I2C Bus
9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The ACK signaling takes place after each transmitted byte. The ACK bit allows the target to signal the host that
the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge
9th clock pulse, are generated by the host.
The host releases the SDA line during the acknowledge clock pulse so the target can pull the SDA line LOW and
it remains stable LOW during the HIGH period of this 9th clock pulse.
A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The host can then generate
either a STOP to abort the transfer or a repeated START to start a new transfer.
9.5.1.5 Target Address and Data Direction Bit
After the START signal, a target address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/ W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1101 011' (0x6B).
SDA
SCL
S
START
1-7
8
9
ADDRESS
R/W
ACK
8
1-7
DATA
9
1-7
8
DATA
ACK
Figure 9-11. Complete Data Transfer on the
I2C
9
P
ACK
STOP
Bus
9.5.1.6 Single Write and Read
S
Target Addr
0
ACK
Reg Addr
ACK
Data to Addr
ACK
P
Figure 9-12. Single Write
36
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Target Addr
0
ACK
Reg Addr
ACK
S
Target Addr
1
ACK
NCK
Data
P
Figure 9-13. Single Read
If the register address is not defined, the charger IC sends back NACK and returns to the idle state.
9.5.1.7 Multi-Write and Multi-Read
The charger device supports multi-byte read and multi-byte write of all registers. These multi-byte operations are
allowed to cross register boundaries. For instance, the entire register map may be read in a single operation with
a 39-byte read that starts at register address 0x01.
S
Target Addr
0
ACK
Data to Addr
Reg Addr
ACK
ACK
Data to Addr+1
Data to Addr+N
ACK
ACK
P
Figure 9-14. Multi-Write
S
Target Addr
0
ACK
Data @ Addr
Reg Addr
ACK
ACK
Data @ Addr+1
S
Target Addr
ACK
1
Data @ Addr+N
ACK
NCK
P
Figure 9-15. Multi-Read
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9.6 Register Maps
I2C Device Address: 0x6B.
9.6.1 Register Programming
The BQ25620 and BQ25622 contain 8-bit and 16-bit registers. When writing to 16-bit registers, I2C transactions
follow the little endian format, starting at the address of the least significant byte and writing both register bytes in
a single 16-bit transaction.
38
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9.6.2 BQ25620 Registers
Table 9-7 lists the memory-mapped registers for the BQ25620 registers. All register offset addresses not listed in
Table 9-7 should be considered as reserved locations and the register contents should not be modified.
Table 9-7. BQ25620 Registers
Address Acronym
Register Name
Section
0x2
REG0x02_Charge_Current_Limit
Charge Current Limit
Go
0x4
REG0x04_Charge_Voltage_Limit
Charge Voltage Limit
Go
0x6
REG0x06_Input_Current_Limit
Input Current Limit
Go
0x8
REG0x08_Input_Voltage_Limit
Input Voltage Limit
Go
0xA
REG0x0A_IOTG_regulation
IOTG regulation
Go
0xC
REG0x0C_VOTG_regulation
VOTG regulation
Go
0xE
REG0x0E_Minimal_System_Voltage
Minimal System Voltage
Go
0x10
REG0x10_Pre-charge_Control
Pre-charge Control
Go
0x12
REG0x12_Termination_Control
Termination Control
Go
0x14
REG0x14_Charge_Control_0
Charge Control 0
Go
0x15
REG0x15_Charge_Timer_Control
Charge Timer Control
Go
0x16
REG0x16_Charger_Control_1
Charger Control 1
Go
0x17
REG0x17_Charger_Control_2
Charger Control 2
Go
0x18
REG0x18_Charger_Control_3
Charger Control 3
Go
0x19
REG0x19_Charger_Control_4
Charger Control 4
Go
0x1A
REG0x1A_NTC_Control_0
NTC Control 0
Go
0x1B
REG0x1B_NTC_Control_1
NTC Control 1
Go
0x1C
REG0x1C_NTC_Control_2
NTC Control 2
Go
0x1D
REG0x1D_Charger_Status_0
Charger Status 0
Go
0x1E
REG0x1E_Charger_Status_1
Charger Status 1
Go
0x1F
REG0x1F_FAULT_Status_0
FAULT Status 0
Go
0x20
REG0x20_Charger_Flag_0
Charger Flag 0
Go
0x21
REG0x21_Charger_Flag_1
Charger Flag 1
Go
0x22
REG0x22_FAULT_Flag_0
FAULT Flag 0
Go
0x23
REG0x23_Charger_Mask_0
Charger Mask 0
Go
0x24
REG0x24_Charger_Mask_1
Charger Mask 1
Go
0x25
REG0x25_FAULT_Mask_0
FAULT Mask 0
Go
0x26
REG0x26_ADC_Control
ADC Control
Go
0x27
REG0x27_ADC_Function_Disable_0
ADC Function Disable 0
Go
0x28
REG0x28_IBUS_ADC
IBUS ADC
Go
0x2A
REG0x2A_IBAT_ADC
IBAT ADC
Go
0x2C
REG0x2C_VBUS_ADC
VBUS ADC
Go
0x2E
REG0x2E_VPMID_ADC
VPMID ADC
Go
0x30
REG0x30_VBAT_ADC
VBAT ADC
Go
0x32
REG0x32_VSYS_ADC
VSYS ADC
Go
0x34
REG0x34_TS_ADC
TS ADC
Go
0x36
REG0x36_TDIE_ADC
TDIE ADC
Go
0x38
REG0x38_Part_Information
Part Information
Go
Complex bit access types are encoded to fit into small table cells. Table 9-8 shows the codes that are used for
access types in this section.
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Table 9-8. BQ25620 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
9.6.2.1 REG0x02_Charge_Current_Limit Register (Address = 0x2) [Reset = X]
REG0x02_Charge_Current_Limit is shown in Figure 9-16 and described in Table 9-9.
Return to the Summary Table.
Charge Current Limit
Figure 9-16. REG0x02_Charge_Current_Limit Register
15
14
7
13
12
11
10
RESERVED
ICHG
R-0x0
R/W-X
6
5
4
3
2
ICHG
RESERVED
R/W-X
R-0x0
9
8
1
0
Table 9-9. REG0x02_Charge_Current_Limit Register Field Descriptions
Bit
15:12
40
Field
Type
Reset
RESERVED
R
0x0
11:5
ICHG
R/W
X
4:0
RESERVED
R
0x0
Notes
Description
Reserved
WATCHDOG Timer
Expiration sets ICHG to
1/2 its previous value
(rounded down)
Reset by:
REG_RESET
Charge Current Regulation Limit:
This 16-bit register follows the little-endian convention.
ICHG[5:2] falls in REG0x03[3:0], and ICHG[1:0] falls in
REG0x02[7:6].
POR: 1040mA (1Ah)
Range: 80mA-3520mA (2h-58h)
Clamped Low
Clamped High
Bit Step: 80mA (2h)
NOTE: When Q4_FULLON=1, this register has a
minimum value of 160mA
Reserved
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9.6.2.2 REG0x04_Charge_Voltage_Limit Register (Address = 0x4) [Reset = 0x0D20]
REG0x04_Charge_Voltage_Limit is shown in Figure 9-17 and described in Table 9-10.
Return to the Summary Table.
Charge Voltage Limit
Figure 9-17. REG0x04_Charge_Voltage_Limit Register
15
14
7
13
12
11
10
RESERVED
VREG
R-0x0
R/W-0x1A4
6
5
4
3
2
9
8
1
0
VREG
RESERVED
R/W-0x1A4
R-0x0
Table 9-10. REG0x04_Charge_Voltage_Limit Register Field Descriptions
Bit
15:12
Field
Type
Reset
RESERVED
R
0x0
11:3
VREG
R/W
0x1A4
2:0
RESERVED
R
0x0
Notes
Description
Reserved
Reset by:
REG_RESET
Battery Voltage Regulation Limit:
This 16-bit register follows the little-endian convention.
VREG[8:5] falls in REG0x05[3:0], and VREG[4:0] falls
in REG0x04[7:3].
POR: 4200mV (1A4h)
Range: 3500mV-4800mV (15Eh-1E0h)
Clamped Low
Clamped High
Bit Step: 10mV
Reserved
9.6.2.3 REG0x06_Input_Current_Limit Register (Address = 0x6) [Reset = 0x0A00]
REG0x06_Input_Current_Limit is shown in Figure 9-18 and described in Table 9-11.
Return to the Summary Table.
Input Current Limit
Figure 9-18. REG0x06_Input_Current_Limit Register
15
14
7
13
12
11
10
RESERVED
IINDPM
R-0x0
R/W-0xA0
6
5
4
3
2
IINDPM
RESERVED
R/W-0xA0
R-0x0
9
8
1
0
Table 9-11. REG0x06_Input_Current_Limit Register Field Descriptions
Bit
15:12
Field
Type
Reset
RESERVED
R
0x0
Notes
Description
Reserved
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Table 9-11. REG0x06_Input_Current_Limit Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
11:4
IINDPM
R/W
0xA0
Reset by:
REG_RESET
Adapter Removal
Input Current Regulation Limit:
This 16-bit register follows the little-endian convention.
IINDPM[7:4] falls in REG0x07[3:0], and IINDPM[3:0]
falls in REG0x06[7:4]. BQ25620: Based on D+/Ddetection results:
USB SDP = 500mA
USB CDP = 1.5A
USB DCP = 1.5A
USB HVDCP = 1.5A
Unknown Adapter = 500mA
Non-Standard Adapter = 1A/2.1A/2.4A
POR: 3200mA (A0h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
When the adapter is removed, IINDPM is reset to its
POR value of 3.2 A.
3:0
RESERVED
R
0x0
Reserved
9.6.2.4 REG0x08_Input_Voltage_Limit Register (Address = 0x8) [Reset = 0x0E60]
REG0x08_Input_Voltage_Limit is shown in Figure 9-19 and described in Table 9-12.
Return to the Summary Table.
Input Voltage Limit
Figure 9-19. REG0x08_Input_Voltage_Limit Register
15
14
13
12
11
RESERVED
10
9
8
2
1
0
VINDPM
R-0x0
R/W-0x73
7
6
5
4
3
VINDPM
RESERVED
R/W-0x73
R-0x0
Table 9-12. REG0x08_Input_Voltage_Limit Register Field Descriptions
Bit
Field
Type
Reset
15:14
RESERVED
R
0x0
Notes
Description
Reserved
13:5
VINDPM
R/W
0x73
Absolute Input Voltage Regulation Limit:
This 16-bit register follows the little-endian convention.
VINDPM[8:3] falls in REG0x09[5:0], and VINDPM[2:0]
falls in REG0x08[7:5].
POR: 4600mV (73h)
Range: 3800mV-16800mV (5Fh-1A4h)
Clamped Low
Clamped High
Bit Step: 40mV
4:0
RESERVED
R
0x0
Reserved
9.6.2.5 REG0x0A_IOTG_regulation Register (Address = 0xA) [Reset = 0x0320]
REG0x0A_IOTG_regulation is shown in Figure 9-20 and described in Table 9-13.
Return to the Summary Table.
IOTG regulation
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Figure 9-20. REG0x0A_IOTG_regulation Register
15
14
7
13
12
11
10
RESERVED
IOTG
R-0x0
R/W-0x32
6
5
4
3
2
IOTG
RESERVED
R/W-0x32
R-0x0
9
8
1
0
Table 9-13. REG0x0A_IOTG_regulation Register Field Descriptions
Bit
15:12
Field
Type
Reset
RESERVED
R
0x0
11:4
IOTG
R/W
0x32
3:0
RESERVED
R
0x0
Notes
Description
Reserved
Reset by:
REG_RESET
WATCHDOG
OTG mode current regulation limit:
This 16-bit register follows the little-endian convention.
IOTG[7:4] falls in REG0x0B[3:0], and IOTG[3:0] falls in
REG0x0A[7:4].
POR: 1000mA (32h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
Reserved
9.6.2.6 REG0x0C_VOTG_regulation Register (Address = 0xC) [Reset = 0x0FC0]
REG0x0C_VOTG_regulation is shown in Figure 9-21 and described in Table 9-14.
Return to the Summary Table.
VOTG regulation
Figure 9-21. REG0x0C_VOTG_regulation Register
15
14
13
12
11
10
RESERVED
VOTG
R-0x0
R/W-0x3F
7
6
5
4
3
2
VOTG
RESERVED
R/W-0x3F
R-0x0
9
8
1
0
Table 9-14. REG0x0C_VOTG_regulation Register Field Descriptions
Bit
Field
Type
Reset
15:13
RESERVED
R
0x0
12:6
VOTG
R/W
0x3F
5:0
RESERVED
R
0x0
Notes
Description
Reserved
Reset by:
REG_RESET
OTG mode regulation voltage:
This 16-bit register follows the little-endian convention.
VOTG[6:2] falls in REG0x0D[4:0], and VOTG[1:0] falls
in REG0x0C[7:6].
POR: 5040mV (3Fh)
Range: 3840mV-9600mV (30h-78h)
Clamped Low
Clamped High
Bit Step: 80mV
Reserved
9.6.2.7 REG0x0E_Minimal_System_Voltage Register (Address = 0xE) [Reset = 0x0B00]
REG0x0E_Minimal_System_Voltage is shown in Figure 9-22 and described in Table 9-15.
Return to the Summary Table.
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Minimal System Voltage
Figure 9-22. REG0x0E_Minimal_System_Voltage Register
15
14
7
13
12
11
10
RESERVED
VSYSMIN
R-0x0
R/W-0x2C
6
5
4
3
2
VSYSMIN
RESERVED
R/W-0x2C
R-0x0
9
8
1
0
Table 9-15. REG0x0E_Minimal_System_Voltage Register Field Descriptions
Bit
Field
Type
Reset
RESERVED
R
0x0
11:6
VSYSMIN
R/W
0x2C
5:0
RESERVED
R
0x0
15:12
Notes
Description
Reserved
Reset by:
REG_RESET
Minimal System Voltage:
This 16-bit register follows the little-endian
convention. VSYSMIN[5:2] falls in REG0x0F[3:0], and
VSYSMIN[1:0] falls in REG0x0E[7:6].
POR: 3520mV (2Ch)
Range: 2560mV-3840mV (20h-30h)
Clamped Low
Clamped High
Bit Step: 80mV
Reserved
9.6.2.8 REG0x10_Pre-charge_Control Register (Address = 0x10) [Reset = 0x0050]
REG0x10_Pre-charge_Control is shown in Figure 9-23 and described in Table 9-16.
Return to the Summary Table.
Pre-charge Control
Figure 9-23. REG0x10_Pre-charge_Control Register
15
14
13
12
11
10
9
RESERVED
R-0x0
7
6
5
4
8
IPRECHG
R/W-0xA
3
2
1
IPRECHG
RESERVED
R/W-0xA
R-0x0
0
Table 9-16. REG0x10_Pre-charge_Control Register Field Descriptions
Bit
Field
Type
Reset
15:9
RESERVED
R
0x0
8:3
IPRECHG
R/W
0xA
2:0
RESERVED
R
0x0
Notes
Description
Reserved
Reset by:
REG_RESET
Pre-charge current regulation limit:
This 16-bit register follows the little-endian convention.
IPRECHG[4] falls in REG0x11[0], and IPRECHG[3:0]
falls in REG0x10[7:4]
POR: 100mA (Ah)
Range: 20mA-620mA (2h-3Eh)
Clamped Low
Bit Step: 20mA (2h)
NOTE: When Q4_FULLON=1, this register has a
minimum value of 80mA
Reserved
9.6.2.9 REG0x12_Termination_Control Register (Address = 0x12) [Reset = 0x0030]
REG0x12_Termination_Control is shown in Figure 9-24 and described in Table 9-17.
44
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Return to the Summary Table.
Termination Control
Figure 9-24. REG0x12_Termination_Control Register
15
14
7
13
6
12
5
11
10
9
8
RESERVED
ITERM
R-0x0
R/W-0xC
4
3
2
1
0
ITERM
RESERVED
R/W-0xC
R-0x0
Table 9-17. REG0x12_Termination_Control Register Field Descriptions
Bit
Field
Type
Reset
15:9
RESERVED
R
0x0
8:2
ITERM
R/W
0xC
1:0
RESERVED
R
0x0
Notes
Description
Reserved
Reset by:
REG_RESET
Termination Current Threshold:
This 16-bit register follows the little-endian convention.
ITERM[5] falls in REG0x13[0], and ITERM[4:0] falls in
REG0x12[7:3].
POR: 60mA (Ch)
Range: 10mA-620mA (2h-7Ch)
Clamped Low
Bit Step: 10mA (2h)
NOTE: When Q4_FULLON=1, this register has a
minimum value of 120mA, so Reset value becomes
120mA in this case
Reserved
9.6.2.10 REG0x14_Charge_Control_0 Register (Address = 0x14) [Reset = 0x06]
REG0x14_Charge_Control_0 is shown in Figure 9-25 and described in Table 9-18.
Return to the Summary Table.
Charge Control 0
Figure 9-25. REG0x14_Charge_Control_0 Register
7
6
5
2
1
0
Q1_FULLON
Q4_FULLON
ITRICKLE
4
TOPOFF_TMR
3
EN_TERM
VINDPM_BAT_TRAC
K
VRECHG
R-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x1
R/W-0x1
R/W-0x0
Table 9-18. REG0x14_Charge_Control_0 Register Field Descriptions
Bit
Field
Type
Reset
Notes
7
Q1_FULLON
R
0x0
Forces RBFET (Q1) into low resistance state (26 mΩ) ,
regardless of IINDPM setting.
0x0 = RBFET RDSON determined by IINDPM setting
(default)
0x1 = RBFET RDSON is always 26 mΩ
6
Q4_FULLON
R/W
0x0
Forces BATFET (Q4) into low resistance state (15
mΩ), regardless of ICHG setting. (Only applies when
VBAT > VSYSMIN. Otherwise BATFET operates in
linear mode.)
0x0 = BATFET RDSON determined by charge current
(default)
0x1 = BATFET RDSON is always 15 mΩ
5
ITRICKLE
R/W
0x0
Reset by:
REG_RESET
Description
Trickle charging current setting:
0b = 20mA (default)
1b = 80mA
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Table 9-18. REG0x14_Charge_Control_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
4:3
TOPOFF_TMR
R/W
0x0
Reset by:
REG_RESET
Top-off timer control:
0x0 = Disabled (default)
0x1 = 15 mins
0x2 = 30 mins
0x3 = 45 mins
2
EN_TERM
R/W
0x1
Reset by:
REG_RESET
WATCHDOG
Enable termination
0x0 = Disable
0x1 = Enable (default)
1
VINDPM_BAT_TRA
CK
R/W
0x1
Reset by:
REG_RESET
Sets VINDPM to track BAT voltage. Actual VINDPM
is higher of the VINDPM register value and VBAT +
VINDPM_BAT_TRACK.
0x0 = Disable function (VINDPM set by register)
0x1 = VBAT + 400 mV (default)
0
VRECHG
R/W
0x0
Reset by:
REG_RESET
Battery Recharge Threshold Offset (Below VREG)
0x0 = 100mV (default)
0x1 = 200mV
9.6.2.11 REG0x15_Charge_Timer_Control Register (Address = 0x15) [Reset = 0x5C]
REG0x15_Charge_Timer_Control is shown in Figure 9-26 and described in Table 9-19.
Return to the Summary Table.
Charge Timer Control
Figure 9-26. REG0x15_Charge_Timer_Control Register
7
6
5
4
3
2
1
0
DIS_STAT
EN_AUTO_INDET
FORCE_INDET
EN_DCP_BIAS
TMR2X_EN
EN_SAFETY_TMRS
PRECHG_TMR
CHG_TMR
R/W-0x0
R/W-0x1
R/W-0x0
R/W-0x1
R/W-0x1
R/W-0x1
R/W-0x0
R/W-0x0
Table 9-19. REG0x15_Charge_Timer_Control Register Field Descriptions
Bit
46
Field
Type
Reset
Notes
Description
7
DIS_STAT
R/W
0x0
Reset by:
REG_RESET
Disable the STAT pin output
0x0 = Enable (default)
0x1 = Disable
6
EN_AUTO_INDET
R/W
0x1
Reset by:
REG_RESET
WATCHDOG
Automatic D+/D- Detection Enable
0x0 = Disable DPDM detection when VBUS is
plugged-in
0x1 = Enable DPDM detection when VBUS is pluggedin (default)
5
FORCE_INDET
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Force D+/D- detection
0x0 = Do not force DPDM detection (default)
0x1 = Force DPDM algorithm, when DPDM detection
is done, this bit is reset to 0
4
EN_DCP_BIAS
R/W
0x1
Reset by:
REG_RESET
WATCHDOG
Enable 600 mV bias on D+ pin whenever DCP is
detected by BC1.2 detection algorithm (VBUS_STAT
= 011b.)
0x0 = Disable 600 mV bias on D+ pin
0x1 = Enable 600 mV bias on D+ pin if DCP detected
3
TMR2X_EN
R/W
0x1
Reset by:
REG_RESET
2X charging timer control
0x0 = Trickle charge, pre-charge and fast charge
timer not slowed by 2X during input DPM or thermal
regulation.
0x1 = Trickle charge, pre-charge and fast charge timer
slowed by 2X during input DPM or thermal regulation
(default)
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Table 9-19. REG0x15_Charge_Timer_Control Register Field Descriptions (continued)
Bit
Field
Reset
Notes
Description
2
EN_SAFETY_TMRS R/W
Type
0x1
Reset by:
REG_RESET
WATCHDOG
Enable fast charge, pre-charge and trickle charge
timers
0x0 = Disable
0x1 = Enable (default)
1
PRECHG_TMR
R/W
0x0
Reset by:
REG_RESET
Pre-charge safety timer setting
0x0 = 2 hrs (default)
0x1 = 0.5 hrs
0
CHG_TMR
R/W
0x0
Reset by:
REG_RESET
Fast charge safety timer setting
0x0 = 12 hrs (default)
0x1 = 24 hrs
9.6.2.12 REG0x16_Charger_Control_1 Register (Address = 0x16) [Reset = 0xA1]
REG0x16_Charger_Control_1 is shown in Figure 9-27 and described in Table 9-20.
Return to the Summary Table.
Charger Control 1
Figure 9-27. REG0x16_Charger_Control_1 Register
7
6
5
4
3
2
EN_AUTO_IBATDIS
FORCE_IBATDIS
EN_CHG
EN_HIZ
FORCE_PMID_DIS
WD_RST
1
WATCHDOG
0
R/W-0x1
R/W-0x0
R/W-0x1
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x1
Table 9-20. REG0x16_Charger_Control_1 Register Field Descriptions
Bit
Reset
Notes
Description
7
EN_AUTO_IBATDIS R/W
0x1
Reset by:
REG_RESET
Enable the auto battery discharging during the battery
OVP fault
0x0 = The charger does NOT apply a discharging
current on BAT during battery OVP triggered
0x1 = The charger does apply a discharging current on
BAT during battery OVP triggered (default)
6
FORCE_IBATDIS
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Force a battery discharging current (~30mA)
0x0 = IDLE (default)
0x1 = Force the charger to apply a discharging current
on BAT
5
EN_CHG
R/W
0x1
Reset by:
REG_RESET
WATCHDOG
Charger enable configuration
0x0 = Charge Disable
0x1 = Charge Enable (default)
4
EN_HIZ
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Adapter Plug In
Enable HIZ mode.
0x0 = Disable (default)
0x1 = Enable
3
FORCE_PMID_DIS
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Force a PMID discharge current (~30mA.)
0x0 = Disable (default)
0x1 = Enable
2
WD_RST
R/W
0x0
Reset by:
REG_RESET
I2C watch dog timer reset
0x0 = Normal (default)
0x1 = Reset (this bit goes back to 0 after timer reset)
WATCHDOG
R/W
0x1
Reset by:
REG_RESET
Watchdog timer setting
0x0 = Disable
0x1 = 40s (default)
0x2 = 80s
0x3 = 160s
1:0
Field
Type
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9.6.2.13 REG0x17_Charger_Control_2 Register (Address = 0x17) [Reset = 0x4F]
REG0x17_Charger_Control_2 is shown in Figure 9-28 and described in Table 9-21.
Return to the Summary Table.
Charger Control 2
Figure 9-28. REG0x17_Charger_Control_2 Register
7
6
1
0
REG_RST
TREG
5
SET_CONV_FREQ
4
3
SET_CONV_STRN
2
RESERVED
VBUS_OVP
R/W-0x0
R/W-0x1
R/W-0x0
R/W-0x3
R/W-0x1
R/W-0x1
Table 9-21. REG0x17_Charger_Control_2 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
REG_RST
R/W
0x0
REG_RESET
Reset registers to default values and reset timer
Value resets to 0 after reset completes.
0x0 = Not reset (default)
0x1 = Reset
6
TREG
R/W
0x1
Reset by:
REG_RESET
Thermal regulation thresholds.
0x0 = 60C
0x1 = 120C (default)
5:4
SET_CONV_FREQ
R/W
0x0
Reset by:
REG_RESET
Adjust switching frequency of the converter
0x0 = Nominal, 1.5 MHz (default)
0x1 = -10%, 1.35 MHz
0x2 = +10%, 1.65 MHz
0x3 = RESERVED
3:2
SET_CONV_STRN
R/W
0x3
Reset by:
REG_RESET
Adjust the high side and low side drive strength of the
converter to adjust efficiency versus EMI.
0x0 = weak
0x1 = normal
0x2 = RESERVED
0x3 = strong
1
RESERVED
R/W
0x1
0
VBUS_OVP
R/W
0x1
Reserved
Reset by:
REG_RESET
Sets VBUS overvoltage protection threshold
0x0 = 6.3 V
0x1 = 18.5 V
9.6.2.14 REG0x18_Charger_Control_3 Register (Address = 0x18) [Reset = 0x04]
REG0x18_Charger_Control_3 is shown in Figure 9-29 and described in Table 9-22.
Return to the Summary Table.
Charger Control 3
Figure 9-29. REG0x18_Charger_Control_3 Register
7
6
5
4
3
2
RESERVED
EN_OTG
PFM_OTG_DIS
PFM_FWD_DIS
BATFET_CTRL_WV
BUS
BATFET_DLY
1
BATFET_CTRL
0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R-0x0
R/W-0x1
R/W-0x0
Table 9-22. REG0x18_Charger_Control_3 Register Field Descriptions
Bit
48
Field
Type
Reset
Notes
Description
7
RESERVED
R/W
0x0
6
EN_OTG
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
OTG mode control
0b = OTG Disable (default)
1b = OTG Enable
5
PFM_OTG_DIS
R/W
0x0
Reset by:
REG_RESET
Disable PFM in OTG boost mode
0x0 = Enable (Default)
0x1 = Disable
Reserved
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Table 9-22. REG0x18_Charger_Control_3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
4
PFM_FWD_DIS
R/W
0x0
Reset by:
REG_RESET
Disable PFM in forward buck mode
0x0 = Enable (Default)
0x1 = Disable
3
BATFET_CTRL_WV R
BUS
0x0
2
BATFET_DLY
R/W
0x1
Reset by:
REG_RESET
Delay time added to the taking action in bits [1:0] of the
BATFET_CTRL
0x0 = Add 20 ms delay time
0x1 = Add 10s delay time (default)
BATFET_CTRL
R/W
0x0
Reset by:
REG_RESET
BATFET control
The control logic of the BATFET to force the device
enter different modes.
0x0 = Normal (default)
0x1 = Shutdown Mode
0x2 = Ship Mode
0x3 = System Power Reset
1:0
Optionally allows batfet off or system power reset with
adapter present.
0x0 = 0x0
0x1 = 0x1
9.6.2.15 REG0x19_Charger_Control_4 Register (Address = 0x19) [Reset = 0xC0]
REG0x19_Charger_Control_4 is shown in Figure 9-30 and described in Table 9-23.
Return to the Summary Table.
Charger Control 4
Figure 9-30. REG0x19_Charger_Control_4 Register
7
6
5
4
3
2
IBAT_PK
VBAT_UVLO
VBAT_OTG_MIN
EN_9V
EN_12V_or_EN_EXT
ILIM
1
CHG_RATE
0
R/W-0x3
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
Table 9-23. REG0x19_Charger_Control_4 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7:6
IBAT_PK
R/W
0x3
Reset by:
REG_RESET
Battery discharging peak current protection threshold
setting
0x0 = 1.5A
0x1 = 3A
0x2 = 6A
0x3 = 12A (default)
5
VBAT_UVLO
R/W
0x0
Reset by:
REG_RESET
Select the VBAT_UVLO falling threshold and
VBAT_SHORT threshold
0x0 = VBAT_UVLO 2.2V, VBAT_SHORT 2.05V
(default)
0x1 = VBAT_UVLO 1.8V, VBAT_SHORT 1.85V
4
VBAT_OTG_MIN
R/W
0x0
Reset by:
REG_RESET
Select the minimal battery voltage to start the OTG
mode
0x0 = 3V rising / 2.8 falling (default)
0x1 = 2.6V rising / 2.4 falling
3
EN_9V
R/W
0x0
Reset by:
REG_RESET
BQ25620: Enable 9V adapter detection
Host has to set EN_12V=EN_9V=0, followed by proper
setting of EN_12V and EN_9V to start a detection.
After successful 9V detection, if EN_9V is set to
0, charger starts a 12V detection (if EN_12V=1),
or releases D+/D- bias and goes back to DCP (if
EN_12V=0). 0b = Disabled (default)
1b = Enabled
BQ25622: RESERVED with default 0
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Table 9-23. REG0x19_Charger_Control_4 Register Field Descriptions (continued)
Bit
Field
2
1:0
Reset
Notes
Description
EN_12V_or_EN_EX R/W
TILIM
Type
0x0
Reset by:
REG_RESET
WATCHDOG
BQ25620: Enable 12V adapter detection
If EN_12V = EN_9V = 1, charger attempts 12V
negotiation first. If 12V is detected, charger skips 9V
negotiation.
Host has to set EN_12V = EN_9V = 0, followed
by proper setting of EN_12V and EN_9V to start a
negotiation.
After successful 12V negotiation, if EN_12V is set to 0
and EN_9V stays at 1, charger starts 9V negotiation.
0b = Disabled (default)
1b = Enabled
BQ25622:
Enable the external ILIM pin input current regulation
0b = Disabled
1b = Enabled (default)
CHG_RATE
0x0
Reset by:
REG_RESET
The charge rate definition for the fast charge stage.
The charging current fold back value is equal to ICHG
register setting times the fold back ratio, then divided
by the charge rate.
0x0 = 1C (default)
0x1 = 2C
0x2 = 4C
0x3 = 6C
R/W
9.6.2.16 REG0x1A_NTC_Control_0 Register (Address = 0x1A) [Reset = 0x3D]
REG0x1A_NTC_Control_0 is shown in Figure 9-31 and described in Table 9-24.
Return to the Summary Table.
NTC Control 0
Figure 9-31. REG0x1A_NTC_Control_0 Register
7
6
5
4
3
2
1
0
TS_IGNORE
TS_TH_OTG_HOT
TS_TH_OTG_COLD
TS_ISET_WARM
TS_ISET_COOL
R/W-0x0
R/W-0x1
R/W-0x1
R/W-0x3
R/W-0x1
Table 9-24. REG0x1A_NTC_Control_0 Register Field Descriptions
Bit
7
6:5
4
50
Field
Type
Reset
Notes
Description
TS_IGNORE
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Ignore the TS feedback: the charger considers the TS
is always good to allow charging and OTG modes,
TS_STAT reports TS_NORMAL condition.
0x0 = Not ignore (Default)
0x1 = Ignore
TS_TH_OTG_HOT
R/W
0x1
Reset by:
REG_RESET
OTG Mode TS_HOT rising temperature threshold
to transition from normal operation into suspended
OTG mode when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = 55°C
0x1 = 60°C (default)
0x2 = 65°C
0x3 = Disable
TS_TH_OTG_COLD R/W
0x1
Reset by:
REG_RESET
OTG Mode TS_COLD falling temperature threshold
to transition from normal operation into suspended
OTG mode when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = -20°C
0x1 = -10°C (default)
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Table 9-24. REG0x1A_NTC_Control_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
3:2
TS_ISET_WARM
R/W
0x3
Reset by:
REG_RESET
TS_WARM Current Setting
0x0 = Charge Suspend
0x1 = Set ICHG to 20%
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged (default)
1:0
TS_ISET_COOL
R/W
0x1
Reset by:
REG_RESET
TS_COOL Current Setting
0x0 = Charge Suspend
0x1 = Set ICHG to 20% (default)
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged
9.6.2.17 REG0x1B_NTC_Control_1 Register (Address = 0x1B) [Reset = 0x25]
REG0x1B_NTC_Control_1 is shown in Figure 9-32 and described in Table 9-25.
Return to the Summary Table.
NTC Control 1
Figure 9-32. REG0x1B_NTC_Control_1 Register
7
6
5
4
3
2
1
0
TS_TH1_TH2_TH3
TS_TH4_TH5_TH6
TS_VSET_WARM
R/W-0x1
R/W-0x1
R/W-0x1
Table 9-25. REG0x1B_NTC_Control_1 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7:5
TS_TH1_TH2_TH3
R/W
0x1
Reset by:
REG_RESET
TH1, TH2 and TH3 comparator falling temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = TH1 is 0°C, TH2 is 5°C, TH3 is 15°C
0x1 = TH1 is 0°C, TH2 is 10°C, TH3 is 15°C (default)
0x2 = TH1 is 0°C, TH2 is 15°C, TH3 is 20°C
0x3 = TH1 is 0°C, TH2 is 20°C, TH3 20°C
0x4 = TH1 is -5°C, TH2 is 5°C, TH3 is 15°C
0x5 = TH1 is -5°C, TH2 is 10°C, TH3 is 15°C
0x6 = TH1 is -5°C, TH2 is 10°C, TH3 is 20°C
0x7 = TH1 is 0°C, TH2 is 10°C, TH3 is 20°C
4:2
TS_TH4_TH5_TH6
R/W
0x1
Reset by:
REG_RESET
TH4, TH5 and TH6 comparator rising temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = TH4 is 35°C, TH5 is 40°C, TH6 is 60°C
0x1 = TH4 is 35°C, TH5 is 45°C, TH6 is 60°C (default)
0x2 = TH4 is 35°C, TH5 is 50°C, TH6 is 60°C
0x3 = TH4 is 40°C, TH5 is 55°C, TH6 is 60°C
0x4 = TH4 is 35°C, TH5 is 40°C, TH6 is 50°C
0x5 = TH4 is 35°C, TH5 is 45°C, TH6 is 50°C
0x6 = TH4 is 40°C, TH5 is 45°C, TH6 is 60°C
0x7 = TH4 is 40°C, TH5 is 50°C, TH6 is 60°C
1:0
TS_VSET_WARM
R/W
0x1
Reset by:
REG_RESET
TS_WARM Voltage Setting
0x0 = Set VREG to VREG-300mV
0x1 = Set VREG to VREG-200mV (default)
0x2 = Set VREG to VREG-100mV
0x3 = VREG unchanged
9.6.2.18 REG0x1C_NTC_Control_2 Register (Address = 0x1C) [Reset = 0x3F]
REG0x1C_NTC_Control_2 is shown in Figure 9-33 and described in Table 9-26.
Return to the Summary Table.
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NTC Control 2
Figure 9-33. REG0x1C_NTC_Control_2 Register
7
6
RESERVED
TS_VSET_SYM
5
TS_VSET_PREWARM
4
3
TS_ISET_PREWARM
2
1
TS_ISET_PRECOOL
0
R-0x0
R/W-0x0
R/W-0x3
R/W-0x3
R/W-0x3
Table 9-26. REG0x1C_NTC_Control_2 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
RESERVED
R
0x0
6
TS_VSET_SYM
R/W
0x0
Reset by:
REG_RESET
When this bit is set to 0, the voltage regulation
for TS_PRECOOL and TS_COOL is unchanged.
When this bit is set to 1, TS_PRECOOL uses
the TS_VSET_PREWARM setting of TS_PREWARM
and TS_COOL uses the TS_VSET_WARM setting of
TS_WARM .
0x0 = VREG unchanged (default)
0x1 = TS_COOLx matches TS_WARMx
5:4
TS_VSET_PREWAR R/W
M
0x3
Reset by:
REG_RESET
Advanced temperature profile voltage setting for
TS_PREWARM (TH4 - TH5)
0x0 = Set VREG to VREG-300mV
0x1 = Set VREG to VREG-200mV
0x2 = Set VREG to VREG-100mV
0x3 = VREG unchanged (default)
3:2
TS_ISET_PREWAR
M
R/W
0x3
Reset by:
REG_RESET
Advanced temperature profile current setting for
TS_PREWARM zone(TH4 - TH5)
0x0 = Charge Suspend
0x1 = Set ICHG to 20%
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged (default)
1:0
TS_ISET_PRECOO
L
R/W
0x3
Reset by:
REG_RESET
Advanced temperature profile current setting for
TS_PRECOOL zone (TH2 - TH3)
0x0 = Charge Suspend
0x1 = Set ICHG to 20%
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged (default)
RESERVED
9.6.2.19 REG0x1D_Charger_Status_0 Register (Address = 0x1D) [Reset = 0x00]
REG0x1D_Charger_Status_0 is shown in Figure 9-34 and described in Table 9-27.
Return to the Summary Table.
Charger Status 0
Figure 9-34. REG0x1D_Charger_Status_0 Register
7
6
5
4
3
2
1
0
RESERVED
ADC_DONE_STAT
TREG_STAT
VSYS_STAT
IINDPM_STAT
VINDPM_STAT
SAFETY_TMR_STAT
WD_STAT
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
Table 9-27. REG0x1D_Charger_Status_0 Register Field Descriptions
Bit
52
Field
Type
Reset
Notes
Description
7
RESERVED
R
0x0
Reserved
6
ADC_DONE_STAT
R
0x0
ADC Conversion Status (in one-shot mode only)
Note: Always reads 0 in continuous mode
0x0 = Conversion not complete
0x1 = Conversion complete
5
TREG_STAT
R
0x0
IC Thermal regulation status
0x0 = Normal
0x1 = Device in thermal regulation
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Table 9-27. REG0x1D_Charger_Status_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
4
VSYS_STAT
R
0x0
VSYS Regulation Status (forward mode)
0x0 = Not in VSYSMIN regulation (BAT>VSYSMIN)
0x1 = In VSYSMIN regulation (BAT
VBATUVLO connected to BAT.
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12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for lowest switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 12-1) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. For lowest switching noise during forward/charge mode, place the decoupling capacitor CPMID1 and then
bulk capacitor CPMID2 positive terminals as close as possible to PMID pin. Place the capacitor ground
terminal close to the GND pin using the shortest copper trace connection or GND plane on the same layer
as the IC. See Figure 12-2.
2. For lowest switching noise during reverse/OTG mode, place the CSYS1 and CSYS2 output capacitors'
positive terminals near the SYS pin. The capacitors' ground terminals must be via'd down through multiple
vias to an all ground internal layer that returns to IC GND pin through multiple vias under the IC. See Figure
12-2.
3. Since REGN powers the internal gate drivers, place the CREGN capacitor positive terminal close to REGN
pin to minimize switching noise. The capacitor's ground terminal must be via'd down through multiple vias to
an all ground internal layer that returns to IC GND pin through multiple vias under the IC. See Figure 12-2.
4. Place the CVBUS and CBAT capacitors positive terminals as close to the VBUS and BAT pins as possible.
The capacitors' ground terminals must be via'd down through multiple vias to an all ground internal layer that
returns to IC GND pin through multiple vias under the IC. See Figure 12-2.
5. Place the inductor input pin near the positive terminal of the SYS pin capacitors. Due to the PMID capacitor
placement requirements, the inductor's switching node terminal must be via'd down with multiple via's to
a second internal layer with a wide trace that returns to the SW pin with multiple vias. See Figure 12-3.
Using multiple vias ensures that the via's additional resistance is negligible compared to the inductor's
dc resistance and therefore does not impact efficiency. The vias additional series inductance is negligible
compared to the inductor's inductance.
6. Place the BTST capacitor on the opposite side from the IC using vias to connect to the BTST pin and SW
node. See Figure 12-4.
7. A separate analog GND plane for non-power related resistors and capacitors is not required if those
components are placed away from the power components traces and planes.
8. Ensure that the I2C SDA and SCL lines are routed away from the SW node.
Additionally, it is important that the PCB footprint and solder mask for BQ25620 cover the entire length of each
of the pins. GND, SW, PMID, SYS and BAT pins extend further into the package than the other pins. Using the
entire length of these pins reduces parasitic resistance and increases thermal conductivity from the package into
the board.
12.2 Layout Example
+
+
±
Figure 12-1. High Frequency Current Path
72
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Figure 12-2. Layout Example: Top Layer (red) and All PGND Internal Layer 2 (brown)
Figure 12-3. Layout Example: Inner Layer 3 (AGND pour; SW node pour; signal routing)
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Figure 12-4. Layout Example: Bottom Layer X-Ray From Top (PGND pour; BTST capacitor; redundant
SW, SYS and BAT pours)
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• BQ25601 and BQ25601D (PWR877) Evaluation Module User's Guide
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
BQ25620RYKR
ACTIVE
WQFN-HR
RYK
18
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
BQ25620
Samples
BQ25622RYKR
ACTIVE
WQFN-HR
RYK
18
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ25622
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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