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BQ25890H
SLUSCC5A – SEPTEMBER 2016 – REVISED MAY 2018
BQ25890H I2C Controlled Single Cell 5-A Fast Charger with MaxChargeTM Technology for
High Input Voltage and Adjustable Voltage USB On-the-Go Boost Mode
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
High Efficiency 5-A, 1.5-MHz Switch Mode Buck
Charge
– 93% Charge Efficiency at 2 A and 91% Charge
Efficiency at 3 A Charge Current
– Optimize for High Voltage Input (9 V / 12 V)
– Low Power PFM mode for Light Load
Operations
USB On-the-Go (OTG) with Adjustable Output
from 4.5 V to 5.5 V
– Selectable 500-KHz / 1.5-MHz Boost
Converter with up-to 2.4 A Output
– 93% Boost Efficiency at 5 V at 1 A Output
– Accurate Hiccup Mode Overcurent Protection
– Support down-to 2.5V Battery
– Support PWM only or PFM/PWM control for
Light Load Efficiency
Single Input to Support USB Input and Adjustable
High Voltage Adapters
– Support 3.9-V to 14-V Input Voltage Range
– Input Current Limit (100 mA to 3.25 A with 50mA resolution) to Support USB2.0, USB3.0
standard and High Voltage Adapters
– Maximum Power Tracking by Input Voltage
Limit up-to 14V for Wide Range of Adapters
– Auto Detect USB SDP, CDP, DCP, and Nonstandard Adapters
Input Current Optimizer (ICO) to Maximize Input
Power without Overloading Adapters
Resistance Compensation (IRCOMP) from
Charger Output to Cell Terminal
Highest Battery Discharge Efficiency with 11-mΩ
Battery Discharge MOSFET up to 9 A
Integrated ADC for System Monitor
(Voltage, Temperature, Charge Current)
Narrow VDC (NVDC) Power Path Management
– Instant-on Works with No Battery or Deeply
Discharged Battery
– Ideal Diode Operation in Battery Supplement
Mode
BATFET Control to Support Ship Mode, Wake Up,
and Full System Reset
Flexible Autonomous and I2C Mode for Optimal
System Performance
High Integration includes all MOSFETs, Current
•
•
•
Sensing and Loop Compensation
12-µA Low Battery Leakage Current to Support
Ship Mode
High Accuracy
– ±0.5% Charge Voltage Regulation
– ±5% Charge Current Regulation
– ±7.5% Input Current Regulation
Safety
– Battery Temperature Sensing for Charge and
Boost Mode
– Thermal Regulation and Thermal Shutdown
2 Applications
•
•
•
Smart Phone
Tablet PC
Portable Internet Devices
3 Description
The bq25890H is a highly-integrated 5-A switch-mode
battery charge management and system power path
management device for single cell Li-Ion and Lipolymer battery. The devices support high input
voltage fast charging. The low impedance power path
optimizes switch-mode operation efficiency, reduces
battery charging time and extends battery life during
discharging phase.
Device Information(1)
PART NUMBER
bq25890H
PACKAGE
BODY SIZE (NOM)
WQFN (24)
4.00mm x 4.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Input
3.9Vt14V at 3A
USB
SYS 3.5Vt4.5V
VBUS
OTG
5V at 2.4A
SW
SYS
Ichg = 3A
BAT
I2C Bus
Host
QON
bq25890H
Host Control
REGN
Optional
TS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ25890H
SLUSCC5A – SEPTEMBER 2016 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 12
Typical Characteristics ............................................ 13
Detailed Description ............................................ 15
8.1 Functional Block Diagram ....................................... 15
8.2 Feature Description................................................. 16
8.3 Device Functional Modes........................................ 32
8.4 Register Maps ......................................................... 34
9
Application and Implementation ........................ 51
9.1 Application Information............................................ 51
9.2 Typical Application .................................................. 51
9.3 System Examples ................................................... 56
10 Power Supply Recommendations ..................... 57
11 Layout................................................................... 57
11.1 Layout Guidelines ................................................. 57
11.2 Layout Example .................................................... 57
12 Device and Documentation Support ................. 58
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
58
58
58
58
58
58
13 Mechanical, Packaging, and Orderable
Information ........................................................... 58
4 Revision History
Changes from Original (September 2016) to Revision A
Page
•
Added "SW (peak for 10 ns duration)" To the Absolute Maximum Ratings (1) ....................................................................... 6
•
Changed VSYS TYP value From: VBAT + 50 mV To: I(SYS) + 150 mV ...................................................................................... 7
•
Changed the title of Figure 4 From: Charge Current Accuracy To: I2C Setting .................................................................. 13
•
Changed axis title of Figure 8 From: BAT Voltage (V) To: Input Current Limit (mA) ........................................................... 13
•
Changed VVREF to VREGN in Equation 2................................................................................................................................. 24
•
Changed VREF to VREGN in Figure 16 .................................................................................................................................... 25
•
Added sentence to the Battery Monitor secton "In battery only mode, .."............................................................................ 25
•
Changed the Description values of Table 26 From: mV To: mA.......................................................................................... 49
•
Changed the Type values of Bit 7 in Table 28 From: R To: R/W......................................................................................... 50
•
Added VREF system pullup voltage to Table 29 .................................................................................................................... 51
2
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SLUSCC5A – SEPTEMBER 2016 – REVISED MAY 2018
5 Description (continued)
The I2C Serial interface with charging and system settings makes the device a truly flexible solution.
The bq25890H is a highly-integrated 5-A switch-mode battery charge management and system power path
management device for single cell Li-Ion and Li-polymer battery. It features fast charging with high input voltage
support for a wide range of smartphone, tablet and portable devices. Its low impedance power path optimizes
switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging
phase. It also integrates Input Current Optimizer (ICO) and Resistance Compensation (IRCOMP) to deliver
maximum charging power to battery. The solution is highly integrated with input reverse-blocking FET (RBFET,
Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4)
between system and battery. It also integrates the bootstrap diode for the high-side gate drive and battery
monitor for simplified system design. The I2C serial interface with charging and system settings makes the device
a truly flexible solution.
The device supports a wide range of input sources, including standard USB host port, USB charging port, and
USB compliant adjustable high voltage adapter. To support fast charging using adjustable high voltage adapter,
the SN25890H provides support for MaxChargeTM handshake using D+/D- pins and DSEL pin for USB switch
control. In addition, the device include interface to support adjustable high voltage adapter using input current
pulse protocol. To set the default input current limit, device uses the built-in USB interface, such as USB PHY
device. The device is compliant with USB 2.0 and USB 3.0 power spec with input current and voltage regulation.
In addition, the Input Current Optimizer (ICO) supports the detection of maximum power point detection of the
input source without overload. The device also meets USB On-the-Go (OTG) operation power rating specification
by supplying 5 V (Adjustable 4.5 V - 5.5 V) on VBUS with current limit up to 2.4 A.
The power path management regulates the system slightly above battery voltage but does not drop below 3.5V
minimum system voltage (programmable). With this feature, the system maintains operation even when the
battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power
path management automatically reduces the charge current to zero. As the system load continues to increase,
the power path discharges the battery until the system power requirement is met. This Supplemental Mode
operation prevents overloading the input source.
The device initiates and completes a charging cycle without software control. It automatically detects the battery
voltage and charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the
end of the charging cycle, the charger automatically terminates when the charge current is below a preset limit in
the constant voltage phase. When the full battery falls below the recharge threshold, the charger will
automatically start another charging cycle.
The charger provides various safety features for battery charging and system operations, including battery
temperature negative thermistor monitoring, charging safety timer and overvoltage/overcurrent protections. The
thermal regulation reduces charge current when the junction temperature exceeds 120°C (programmable). The
STAT output reports the charging status and any fault conditions. The INT immediately notifies host when fault
occurs.
The device also provides a 7-bit analog-to-digital converter (ADC) for monitoring charge current and
input/battery/system (VBUS, BAT, SYS, TS) voltages. The QON pin provides BATFET enable/reset control to
exit low power ship mode or full system reset function.
The device family is available in 24-pin, 4 x 4 mm2 x 0.75 mm thin WQFN package.
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BQ25890H
SLUSCC5A – SEPTEMBER 2016 – REVISED MAY 2018
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6 Pin Configuration and Functions
DSEL
PMID
REGN
BTST
SW
SW
BQ25890H
RTW (WQFN)
Top View
24
23
22
21
20
19
VBUS
1
18
PGND
D+
2
17
PGND
D–
3
16
SYS
STAT
4
15 SYS
SCL 5
14
SDA
13 BAT
10
11
12
TS
QON
OTG
9
ILIM
8
CE
7
INT
6
BAT
Pin Functions
PIN
(1)
4
TYPE (1)
DESCRIPTION
1
P
Charger Input Voltage.
The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on
source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
D+
2
AIO
Positive line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary
and secondary detection in BC1.2, and Adjustable high voltage adapter. The pin can be configured as output
driver by DP_DAC register bits when input source is plugged-in or during OTG mode.
D–
3
AIO
Negative line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary
and secondary detection in BC1.2, and Adjustable high voltage adapter. The pin can be configured as output
driver by DM_DAC register bits when input source is plugged-in or during OTG mode.
STAT
4
DO
Open drain charge status output to indicate various charger operation.
Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge
complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz.
The STAT pin function can be disabled when STAT_DIS bit is set.
SCL
5
DI
I2C Interface clock.
Connect SCL to the logic rail through a 10-kΩ resistor.
SDA
6
DIO
I2C Interface data.
Connect SDA to the logic rail through a 10-kΩ resistor.
INT
7
DO
Open-drain Interrupt Output.
Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report
charger device status and fault.
OTG
8
DI
Active high enable pin during boost mode.
The boost mode is activated when OTG_CONFIG =1 and OTG pin is high
CE
9
DI
Active low Charge Enable pin.
Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low.
NAME
No.
VBUS
DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)
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Pin Functions (continued)
PIN
NAME
No.
TYPE (1)
DESCRIPTION
ILIM
10
AI
Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input current
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected
from ILIM pin to ground to set the maximum limit as IINMAX = KILIM/RILIM . The actual input current limit is the
lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500
mA is not support on ILIM pin.
ILIM pin can also be used to monitor input current when the voltage is below 0.8V. The input current is
proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8)
The ILIM pin function can be disabled when EN_ILIM bit is 0.
TS
11
AI
Temperature qualification voltage input.
Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider
from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2
thermistor.
QON
12
DI
BATFET enable/reset control input.
When BATFET is in ship mode, a logic low of tSHIPMODE (typical 1sec) duration turns on BATFET to exit
shipping mode. .
When VBUS is not plugged-in, a logic low of tQON_RST (typical 15sec) duration resets SYS (system power) by
turning BATFET off for tBATFET_RST (typical 0.3sec) and then re-enable BATFET to provide full system power
reset.
The pin contains an internal pull-up to maintain default high logic
BAT
13,14
P
Battery connection point to the positive terminal of the battery pack.
The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin.
SYS
15,16
P
System connection point.
The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system
voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20uF closely to the
SYS pin.
PGND
17,18
P
Power ground connection for high-current power converter node.
Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to
ground connection of input and output capacitors of the charger. A single point connection is recommended
between power PGND and the analog GND near the IC PGND pin.
SW
19,20
P
Switching node connecting to output inductor.
Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET.
Connect the 0.047µF bootstrap capacitor from SW to BTST.
BTST
21
P
PWM high side driver positive supply.
Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047 µF bootstrap
capacitor from SW to BTST.
REGN
22
P
PWM low side driver positive supply output.
Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7 µF (10 V rating) ceramic
capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as
bias rail of TS pin.
PMID
23
DO
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.
Given the total input capacitance, put 1µF on VBUS to PGND, and the rest capacitance on PMID to PGND.
DO
Active high D+/D- multiplexer selection control.
Connect a 47-nF (6V rating) ceramic capacitor from DSEL to analog GND. The pin is normally low. During
input source type detection, the pin drives high to indicate the device D+/D- detection is in progress and needs
to take control of D+, D- signals. When detection is completed, the pin keeps high when DCP, MaxCharge or
HVDCP is detected. The pin returns to low when other input source type is detected.
P
Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on
the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.
DSEL
PowerPAD™
24
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage range (with respect to GND)
Output sink current
MIN
MAX
VALUE
VBUS (converter not switching)
–2
22
V
PMID (converter not switching)
–0.3
22
V
STAT
–0.3
20
V
DSEL
–0.3
7
V
BTST
–0.3
20
V
SW
–2
16
V
SW (peak for 10 ns duration)
–3
16
V
BAT, SYS (converter not switching)
–0.3
6
V
SDA, SCL, INT, OTG, REGN, TS, CE, QON
–0.3
7
V
D+, D–
–0.3
7
V
BTST TO SW
–0.3
7
V
PGND to GND
–0.3
0.3
V
ILIM
–0.3
5
V
6
mA
INT, STAT
2
mA
Junction temperature
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
DSEL
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
7.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
VESD
(1)
(2)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
(1)
VALUE
UNIT
±2000
V
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
IIN
Input current (VBUS)
ISYS
Output current (SW)
VBAT
Battery voltage
3.9
Fast charging current
IBAT
TA
(1)
6
Discharging current with internal MOSFET
Operating free-air temperature range
–40
NOM
MAX
UNIT
14 (1)
V
3.25
A
5
A
4.608
V
5
A
Up to 6 (continuos)
A
9 (peak)
(Up to 1 sec duration)
A
85
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight
layout minimizes switching noise.
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7.4 Thermal Information
BQ25890H
THERMAL METRIC (1)
RTW (WQFN)
UNIT
24-PINS
RθJA
Junction-to-ambient thermal resistance
31.8
°C/W
RθJC((op)
Junction-to-case (top) thermal resistance
27.9
°C/W
RθJB
Junction-to-board thermal resistance
8.7
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
VBAT = 4.2 V, V(VBUS) < V(UVLO), leakage
between BAT and VBUS
IBAT
I(VBUS_HIZ)
I(VBUS)
I(BOOST)
Battery discharge current (BAT, SW, SYS) in buck mode
Input supply current (VBUS) in buck mode when High-Z mode
is enabled
Input supply current (VBUS) in buck mode
5
µA
12
23
µA
High-Z mode, no VBUS, BATFET enabled
(REG09[5]=0), battery monitor disabled, TJ <
85°C
32
60
µA
V(VBUS)= 5 V, High-Z mode, no battery, battery
monitor disabled
15
35
µA
V(VBUS)= 12 V, High-Z mode, no battery,
battery monitor disabled
25
50
µA
VBUS > V(UVLO), VBUS > VBAT, converter not
switching
1.5
3
mA
High-Z mode, no VBUS, BATFET disabled
(REG09[5]=1), battery monitor disabled, TJ <
85°C
VBUS > V(UVLO), VBUS > VBAT, converter
switching, VBAT = 3.2 V, ISYS = 0A
3
mA
VBUS > V(UVLO), VBUS > VBAT, converter
switching, VBAT = 3.8 V, ISYS = 0 A
3
mA
VBAT = 4.2 V, boost mode, I(VBUS)= 0 A,
converter switching, PFM_OTG_DIS=0
3
mA
VBAT = 4.2 V, boost mode, I(VBUS)= 0 A,
converter switching, PFM_OTG_DIS=1
15
mA
Battery discharge current in boost mode
VBUS/BAT POWER UP
V(VBUS_OP)
VBUS operating range
3.9
V(VBUS_UVLOZ)
VBUS for active I2C, no battery
3.6
V(SLEEP)
Sleep mode falling threshold
25
65
V(SLEEPZ)
Sleep mode rising threshold
130
250
V(ACOV)
14
V
120
mV
V
370
mV
VBUS over-voltage rising threshold
14
14.6
V
VBUS over-voltage falling threshold
13.5
14
V
VBAT(UVLOZ)
Battery for active I2C, no VBUS
2.3
VBAT(DPL)
Battery depletion falling threshold
2.15
2.5
V
V
VBAT(DPLZ)
Battery depletion rising threshold
2.35
2.7
V
V(VBUSMIN)
Bad adapter detection threshold
3.8
V
I(BADSRC)
Bad adapter detection current source
30
mA
POWER-PATH MANAGEMENT
VSYS
VSYS(MIN)
VSYS(MAX)
I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled
(REG09[5]=1)
VBAT+
50 mV
V
I(SYS) = 0 A, VBAT< VSYS(MIN), BATFET Disabled
(REG09[5]=1)
VSYS(MIN) +
150 mV
V
3.65
V
Typical system regulation voltage
Minimum DC system voltage output
VBAT< VSYS(MIN), SYS_MIN = 3.5 V
(REG03[3:1]=101), ISYS= 0 A
Maximum DC system voltage output
VBAT = 4.35 V, SYS_MIN = 3.5V
(REG03[3:1]=101), ISYS= 0 A
3.50
4.40
4.42
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
TYP
MAX
TJ = –40°C to +85°C
27
38
mΩ
RON(RBFET)
Top reverse blocking MOSFET(RBFET) on-resistance
between VBUS and PMID
PARAMETER
TEST CONDITIONS
MIN
TJ = –40°C to +125°C
27
44
mΩ
TJ = –40°C to +85°C
27
39
mΩ
RON(HSFET)
Top switching MOSFET (HSFET) on-resistance between PMID
and SW
TJ = –40°C to +125°C
27
47
mΩ
TJ = –40°C to +85°C
16
24
mΩ
RON(LSFET)
Bottom switching MOSFET (LSFET) on-resistance between
SW and GND
TJ = –40°C to +125°C
16
28
mΩ
V(FWD)
BATFET forward voltage in supplement mode
BAT discharge current 10 mA
30
VBAT(GD)
Battery good comparator rising threshold
VBAT rising
VBAT(GD_HYST)
Battery good comparator falling threshold
VBAT falling
3.4
3.55
UNIT
mV
3.7
100
V
mV
BATTERY CHARGER
VBAT(REG_RANGE)
Typical charge voltage range
VBAT(REG_STEP)
Typical charge voltage step
VBAT(REG)
Charge voltage resolution accuracy
I(CHG_REG_RANGE)
Typical fast charge current regulation range
I(CHG_REG_STEP)
Typical fast charge current regulation step
I(CHG_REG_ACC)
VBAT(LOWV)
Fast charge current regulation accuracy
3.840
4.608
16
VBAT = 4.208 V (REG06[7:2]=010111) or
VBAT = 4.352 V (REG06[7:2]=100000)
TJ = –40°C to +85°C
-0.5%
V
mV
0.5%
0
5056
64
mA
mA
VBAT = 3.1 V or 3.8 V, ICHG = 128 mA
TJ = –40°C to +85°C
-20%
20%
VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = –40°C to +85°C
-10%
10%
VBAT= 3.1 V or 3.8 V, ICHG=1792 mA
TJ = –40°C to +85°C
-5%
5%
Battery LOWV falling threshold
Fast charge to precharge, BATLOWV
(REG06[1]) = 1
2.6
2.8
2.9
V
Battery LOWV rising threshold
Precharge to fast charge, BATLOWV
(REG06[1])=1
(Typical 200-mV hysteresis)
2.8
3
3.1
V
I(PRECHG_RANGE)
Precharge current range
I(PRECHG_STEP)
Typical precharge current step
I(PRECHG_ACC)
Precharge current accuracy
I(TERM_RANGE)
Termination current range
I(TERM_STEP)
Typical termination current step
64
1024
64
VBAT=2.6 V, IPRECHG = 256 mA
–10%
mA
+10%
64
1024
64
ITERM = 256 mA, ICHG 1344 mA
TJ = –20°C to +85°C
–20%
mA
mA
mA
12%
I(TERM_ACC)
Termination current accuracy
V(SHORT)
Battery short voltage
VBAT falling
2
V(SHORT_HYST)
Battery short voltage hysteresis
VBAT rising
200
mV
I(SHORT)
Battery short current
VBAT < 2.2 V
100
mA
VBAT falling, VRECHG (REG06[0]=0) = 0
100
mV
VBAT falling, VRECHG (REG06[0]=0) = 1
200
mV
V(RECHG)
Recharge threshold below VBATREG
ISYS(LOAD)
System discharge load current
RON(BATFET)
SYS-BAT MOSFET (BATFET) on-resistance
VSYS = 4.2 V
20%
V
30
mA
TJ = 25°C
11
13
mΩ
TJ = –40°C to +125°C
11
19
mΩ
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE)
Typical Input voltage regulation range
VIN(DPM_STEP)
Typical Input voltage regulation step
VIN(DPM_ACC)
Input voltage regulation accuracy
IIN(DPM_RANGE)
Typical Input current regulation range
IIN(DPM_STEP)
Typical Input current regulation step
IIN(DPM100_ACC)
Input current 100-mA regulation accuracy
VBAT = 5 V, current pulled from SW
IIN(DPM_ACC)
Input current regulation accuracy
VBAT = 5 V, current pulled from SW
3.9
VINDPM = 4.4 V, 9 V, TJ = –40°C to +105°C
IINLIM (REG00[5:0]) =100 mA
V
mV
3%
3%
100
3250
50
mA
mA
85
90
100
mA
USB150, IINLIM (REG00[5:0]) = 150 mA
125
135
150
mA
USB500, IINLIM (REG00[5:0]) = 500 mA
440
470
500
mA
USB900, IINLIM (REG00[5:0]) = 900 mA
750
825
900
mA
1300
1400
1500
mA
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500
mA
8
15.3
100
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IIN(START)
Input current regulation during system start up
VSYS = 2.2 V, IINLIM (REG00[5:0])> = 200 mA
KILIM
IINMAX = KILIM/RILIM
Input current regulation by ILIM pin = 1.5 A
V(0P0_VSRC)
D+/D– voltage source (0 V)
I(DP) < 1 mA; DP_DAC=001 or
DM_DAC=001
V(0P6_VSRC)
D+/D– voltage source (0.6 V)
I(DP) < 1 mA; DP_DAC=010
or
I(DM) < 1 m; ADM_DAC=010
V(1P2_VSRC)
D+/D– voltage source (1.2 V)
V(2P0_VSRC)
TYP
MAX
UNIT
200
mA
315
350
385
AxΩ
-0.15
0
0.15
V
0.5
0.6
0.7
V
I(DP) < 1 mA; DP_DAC=011
or
I(DM) < 1 m; DM_DAC=011
1.075
1.2
1.325
V
D+/D– voltage source (2.0 V)
I(DP) < 1 mA; DP_DAC=100
or
I(DM) < 1 m; DM_DAC=100
1.875
2.0
2.125
V
V(2P7_VSRC)
D+/D– voltage source (2.7 V)
I(DP) < 1 mA; DP_DAC=101
or
I(DM) < 1 m; DM_DAC=101
2.575
2.7
2.825
V
V(3P3_VSRC)
D+/D– voltage source (3.3 V)
I(DP) < 1 mA; DP_DAC=110
or
I(DM) < 1 m; DM_DAC=110
3.15
3.3
3.45
V
V(3p45_VSRC)
D+/D– voltage source (3.45 V)
3.3
3.45
3.6
V
I(10UA_ISRC)
D+ connection check current source
7
10
14
µA
I(100UA_ISINK)
D+/D– current sink (100 µA)
50
100
I(DPDM_LKG)
D+/D– leakage current
D+/D- DETECTION
150
µA
D–, switch open
–1
1
µA
D+, switch open
–1
1
µA
I(1P6MA_ISINK)
D+/D– current sink (1.6 mA)
1.45
V(0P4_VTH)
D+/D– low comparator threshold
V(0P8_VTH)
D+ low comparator threshold
V(2P7_VTH)
1.60
1.75
µA
250
400
mV
0.8
V
D+/D– comparator threshold for non-standard adapter
detection (divider 1, 3, or 4)
2.55
2.85
V
V(2P0_VTH)
D+/D– comparator threshold for non-standard adapter
detection (divider 1, 3)
1.85
2.15
V
V(1P2_VTH)
D+/D– comparator threshold for non-standard adapter
detection (divider 2)
1.05
1.35
V
R(D–_DWN)
D– pulldown for connection check
14.25
24.8
kΩ
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP)
Battery over-voltage threshold
VBAT rising, as percentage of VBAT(REG)
VBAT(OVP_HYST)
Battery over-voltage hysteresis
VBAT falling, as percentage of VBAT(REG)
IBAT(FET_OCP)
System over-current threshold
104%
2%
9
A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG
Junction temperature regulation accuracy
REG08[1:0] = 11
120
°C
TSHUT
Thermal shutdown rising temperature
Temperature rising
160
°C
TSHUT(HYS)
Thermal shutdown hysteresis
Temperature falling
30
°C
JEITA THERMISTOR COMPARATOR (BUCK MODE)
V(T1)
T1 (0°C) threshold, charge suspended T1 below this
temperature.
As percentage to V(REGN)
V(T1_HYS)
Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2])
above this temperature.
As percentage to V(REGN)
V(T2)
T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and
VREG (REG06[7:2]) below this temperature.
As percentage to V(REGN)
V(T2_HYS)
Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2])
above this temperature.
As percentage to V(REGN)
V(T3)
T3 (45°C) threshold, charge back to ICHG (REG04[6:0]) and
VREG-200 mV (REG06[7:2]) above this temperature.
As percentage to V(REGN)
V(T3_HYS)
Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2])
below this temperature.
As percentage to V(REGN)
V(T5)
T5 (60°C) threshold, charge suspended above this
temperature.
As percentage to V(REGN)
V(T5_HYS)
Charge back to ICHG (REG04[6:0]) and VREG-200 mV
(REG06[7:2]) below this temperature.
As percentage to V(REGN)
72.75%
73.25%
73.75%
1.4%
67.75%
68.25%
68.75%
1.4%
44.25v
44.75%
45.25%
1%
33.875%
34.375%
34.875%
1.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V(BCOLD1)
Cold temperature threshold 1, TS pin voltage rising threshold
As percentage to VREGN REG01[5] = 1
(Approximately –20°C w/ 103AT)
V(BCOLD1_HYS)
Cold temperature threshold 1, TS pin voltage falling threshold
As percentage to VREGN REG01[5] = 1
V(BHOT2)
Hot temperature threshold 2, TS pin voltage falling threshold
As percentage to VREGN REG01[7:6] = 10
(Approx. 65°C w/ 103AT)
V(BHOT2_HYS)
Hot temperature threshold 2, TS pin voltage rising threshold
As percentage to VREGN REG01[7:6] =10
FSW
PWM switching frequency, and digital clock
Oscillator frequency
DMAX
Maximum PWM duty cycle
MIN
TYP
MAX
79.5%
80%
80.5%
UNIT
1%
30.75%
31.25%
31.75%
3%
PWM
1.32
1.68
MHz
97%
BOOST MODE OPERATION
V(OTG_REG_RANGE)
Typical boost mode regulation voltage range
V(OTG_REG_STEP)
Typical boost mode regulation voltage step
4.55
V(OTG_REG_ACC)
Boost mode regulation voltage accuracy
I(VBUS) = 0 A, BOOSTV=4.998V
(REG0A[7:4] = 0111)
–3%
3%
V(OTG_BAT1)
Minimum battery voltage to exit boost mode
BAT falling, MIN_VBAT_SEL=0
2.7
2.9
V
V(OTG_BAT2)
Minimum battery voltage to exit boost mode
BAT falling, MIN_VBAT_SEL=1
2.4
2.6
V
BAT rising, MIN_VBAT_SEL=0
2.9
3.1
V
BAT rising, MIN_VBAT_SEL=1
2.7
2.9
V
0.5
2.45
A
1.65
A
V(OTG_BAT_EN)
Minimum battery voltage to enter boost mode
I(OTG)
Typical boost mode output current range
I(OTG_OCP_ACC)
Boost mode RBFET over-current protection accuracy
BOOST_LIM =1.2 A (REG0A[2:0]=010)
1.2
V(OTG_OVP)
Boost mode over-voltage threshold
Rising threshold
5.8
10
5.55
64
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V
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V
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.4
UNIT
REGN LDO
V(REGN)
I(REGN)
REGN LDO output voltage
REGN LDO current limit
V(VBUS) = 9 V, I(REGN) = 40 mA
5.6
6
V(VBUS) = 5 V, I(REGN) = 20 mA
4.7
4.8
V(VBUS) = 9 V, V(REGN) = 3.8 V
50
V
V
mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES
Resolution
Rising threshold
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
enabled
VBAT(RANGE)
Typical battery voltage range
V(BAT_RES)
Typical battery voltage resolution
V(SYS_RANGE)
Typical system voltage range
V(VBUS) < VBAT + V(SLEEP) and OTG mode is
disabled
2.304
V(VBUS) < VBAT + V(SLEEP) and OTG mode is
disabled
Typical VVBUS voltage range
V(VBUS_RES)
Typical VVBUS voltage resolution
IBAT(RANGE)
Typical battery charge current range
IBAT(RES)
Typical battery charge current resolution
V(TS_RANGE)
Typical TS voltage range
V(TS_RES)
Typical TS voltage resolution
4.848
VSYS_MIN
4.848
4.848
V
VSYS_MIN
4.848
V
2.6
mV
15.3
100
V(VBUS) > VBAT + V(SLEEP) and VBAT >
VBAT(SHORT)
V
mV
20
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
enabled
V
2.304
Typical system voltage resolution
V(VBUS_RANGE)
bits
20
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
enabled
V(SYS_RES)
7
0
mV
6.4
50
21%
V
A
mA
80%
0.47%
LOGIC I/O PIN (OTG, CE, QON)
VIH
Input high threshold level
VIL
Input low threshold level
IIN(BIAS)
High Level Leakage Current
V(QON)
Internal /QON pull-up
1.3
Pull-up rail 1.8 V
Battery only mode
R(QON)
0.4
V
1
µA
BAT
V
V(VBUS) = 9 V
5.8
V
V(VBUS) = 5 V
4.3
V
200
kΩ
Internal /QON pull-up resistance
LOGIC I/O PIN (DSEL)
VOL
VOH
Output low threshold level
IOL = 2 mA, CDSEL= 47 nF
Output high threshold level
IOH = 5 mA, CDSEL= 47 nF, non-switching,
I(REGN) = 30 mA
0.4
4.5
V
V
LOGIC I/O PIN (INT, STAT)
VOL
Output low threshold level
Sink current = 5 mA, sink current
IOUT_BIAS
High level leakage current
Pull-up rail 1.8 V
0.4
V
1
µA
V
I2C INTERFACE (SCL, SDA)
VIH
Input high threshold level, SCL and SDA
Pull-up rail 1.8 V
VIL
Input low threshold level
Pull-up rail 1.8 V
1.3
0.4
VOL
Output low threshold level
Sink current = 5 mA, sink current
0.4
V
IBIAS
High level leakage current
Pull-up rail 1.8 V
1
µA
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7.6 Timing Requirements
MIN
NOM
MAX
UNIT
VBUS/BAT POWER UP
tBADSRC
Bad Adapter detection duration
30
msec
1
µs
20
ms
BAT OVER-VOLTAGE PROTECTION
Battery over-voltage deglitch time to disable
charge
tBATOVP
BATTERY CHARGER
tRECHG
Recharge deglitch time
CURRENT PULSE CONTROL
tPUMPX_STOP
Current pulse control stop pulse
430
570
ms
tPUMPX_ON1
Current pulse control long on pulse
240
360
ms
tPUMPX_ON2
Current pulse control short on pulse
70
130
ms
tPUMPX_OFF
Current pulse control off pulse
70
130
ms
tPUMPX_DLY
Current pulse control stop start delay
80
225
ms
1000
ms
BATTERY MONITOR
tCONV
Conversion time
CONV_RATE(REG02[6]) = 0
8
QON AND SHIPMODE TIMING
tSHIPMODE
QON low time to turn on BATFET and exit ship
mode
TJ = –10°C to +60°C
0.8
tQON_RST
QON low time to enable full system reset
TJ = –10°C to +60°C
15.5
23
s
tBATFET_RST
BATFET off time during full system reset
TJ = –10°C to +60°C
250
400
ms
tSM_DLY
Enter ship mode delay
TJ = –10°C to +60°C
10
15
s
400
kHz
1.3
s
I2C INTERFACE
fSCL
SCL clock frequency
DIGITAL CLOCK and WATCHDOG TIMER
fLPDIG
Digital low power clock
REGN LDO disabled
18
30
45
kHz
fDIG
Digital clock
REGN LDO enabled
1320
1500
1680
kHz
WATCHDOG
(REG07[5:4])=11, REGN LDO
disabled
100
160
s
WATCHDOG
(REG07[5:4])=11, REGN LDO
enabled
136
160
s
tWDT
12
Watchdog reset time
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7.7 Typical Characteristics
95%
95%
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
94%
93%
93%
91%
89%
Efficiency (%)
Efficiency (%)
92%
91%
90%
89%
85%
83%
88%
81%
87%
79%
86%
77%
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
75%
85%
0
1
VBAT = 3.8 V
2
3
Charge Current (A)
4
0
5
0.5
D001
1
1.5
System Load Current (A)
2
D002
DCR = 10 mΩ
Figure 1. Charge Efficiency vs Charge Current
Figure 2. System Light Load Efficiency vs System Light
Load Current
96%
6%
5%
94%
4%
92%
3%
2%
90%
Error (%)
Efficiency (%)
87%
88%
86%
1%
0
-1%
-2%
84%
-3%
82%
-4%
VBUS = 3.2 V
VBUS = 3.8 V
80%
0
0.5
1
1.5
VBUS (A)
2
VBAT = 3.1 V
VBAT = 3.8 V
-5%
-6%
0.5
2.5
1
1.5
D003
2
2.5
3
3.5
Charge Current (A)
4
4.5
5
D005
VBUS = 9 V
Figure 4. Charge Current Accuracy vs Charge Current I2C
Setting
3.7
4.5
3.68
4.45
3.66
4.4
3.64
4.35
SYS Voltage (V)
SYS Voltage (V)
Figure 3. Boost Mode Efficiency vs VBUS Load Current
3.62
3.6
3.58
3.56
4.3
4.25
4.2
4.15
3.54
4.1
3.52
4.05
VBUS = 5 V
3.5
VBUS = 5 V
4
0
0.5
VBAT = 2.9 V
1
1.5
2
System Load Current (A)
VBUS = 5 V
2.5
3
0
0.5
D006
SYSMIN = 3.5 V
Figure 5. SYS Voltage Regulation vs System Load Current
1
1.5
2
System Load Current (A)
2.5
3
D007
VBAT = 4.2 V
Figure 6. SYS Voltage Regulation vs System Load Current
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4.42
4.4
4.38
4.36
4.34
4.32
4.3
4.28
4.26
4.24
4.22
4.2
4.18
4.16
4.14
4.12
4.1
-50
1600
1400
Input Current Limit (mA)
BAT Voltage (V)
Typical Characteristics (continued)
50
Temperature (qC)
100
150
800
600
400
IINLM = 500 mA
IINLM = 900 mA
IINLIM = 1.5 A
0
-60
-40
D008
Figure 7. BAT Voltage vs Temperature
14
1000
200
VBUS = 5 V
VBUS = 12 V
0
1200
-20
0
20 40 60 80
Temperature (qC)
100 120 140150
D009
Figure 8. Input Current Limit vs Temperature
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8 Detailed Description
The device is a highly integrated 5-A siwtch-mode battery charger for single cell Li-Ion and Li-polymer battery. It
is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side siwtching FET (HSFET, Q2) ,
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap
diode for the high-side gate drive.
8.1 Functional Block Diagram
RBFET
(Q1)
VBUS
VVBUS_UVLOZ
PMID
UVLO
Q1 Gate
Control
VBATZ +80mV
SLEEP
REGN
REGN
LDO
EN_HIZ
ACOV
VACOV
BTST
FBO
VINDPM
V
VBUS
V OTG_OVP
VBUS_OVP_BOOST
IQ2
Q2_UCP_BOOST
OTG_HSZCP
SW
IQ3
Q3_OCP_BOOST
V
I INDPM
OTG_BAT
BAT
IC T J
HSFET (Q2)
CONVERTER
CONTROL
REGN
BATOVP
104%xV BAT_REG
BAT
TREG
V BAT_REG
I LSFET_UCP
LSFET (Q3)
UCP
Q2_OCP
IQ3
SYS
VSYSMIN
ICHG_REG
IQ2
PGND
I HSFET_OCP
EN_HIZ
EN_CHARGE
EN_BOOST
REFRESH
V BTST -VSW
V BTST_REFRESH
SYS
I CHG
REF
DAC
V BAT_REG
BAD_SRC
ILIM
DSEL
DSEL
Driver
Converter
Control State
Machine
EN
TSHUT
I BADSRC
I CHG_REG
IDC
Q4 Gate
Control
BATFET
(Q4)
IC TJ
TSHUT
BAT
VQON
BAT
D+
D±
Input
Source
Detection
BAT_GD
USB
Adapter
D+/DOutput
Driver
RECHRG
CHARGE
CONTROL
STATE
MACHINE
INT
I2C
Interface
BAT
I TERM
V BATLOWV
BAT
BATSHORT
SDA
ADC
I CHG
TERMINATION
BATLOWV
VBUS
BAT
SYS
TS
V REG -VRECHG
bq25890H
V SHORT
BAT
SUSPEND
SCL
/QON
I CHG
ADC Control
OTG
STAT
VBATGD
Battery
Sensing
Thermistor
TS
CE
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8.2 Feature Description
8.2.1 Device Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
8.2.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and set BATFET_DIS bit to
indicate BATFET is disabled until the input source plugs in again or one of the methods describe in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.
8.2.3 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started when
AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:
1. Power Up REGN LDO
2. Poor Source Qualification
3. Input Source Type Detection based on D+/D- to set default Input Current Limit (IINLIM) register and input
source type
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up
8.2.3.1 Power Up REGN Regulation (LDO)
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLOZ
2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
3. After 220 ms delay is completed
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
8.2.3.2 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the buck converter.
1. VBUS voltage below VACOV
2. VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.
16
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Feature Description (continued)
8.2.3.3 Input Source Type Detection
After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Input Source Type Detection
when AUTO_DPDM_EN bit is set.
The bq25890H follows the USB Battery Charging Specification 1.2 (BC1.2) and to detect input source
(SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. In addition, when USB DCP is detected, it
initiates adjustable high voltage adapter handshake on D+/D-. The device supports MaxCharge™ handshake
when MAXC_EN or HVDCP_EN is set.
After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin
are changed:
1. Input Current Limit (IINLIM) register is changed to set current limit
2. PG_STAT bit is set
The host can over-write IINLIM register to change the input current limit if needed. The charger input current is
always limited by the lower of IINLIM register or ILIM pin at all-time regardless of Input Current Optimizer (ICO) is
enable or disabled.
When AUTO_DPDM_EN is disabled, the Input Source Type Detection is bypassed. The Input Current Limit
(IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.
8.2.3.3.1 D+/D– Detection Sets Input Current Limit
The bq25890H contains a D+/D– based input source detection to set the input current limit automatically. The
D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter
detections. When input source is plugged-in, the device starts standard USB BC1.2 detections. The USB BC1.2
is capable to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated
Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard
adapter detection is applied to set the input current limit.
When DCP is detected, the device initates adjustable high voltage adapter handshake including MaxCharge™,
etc. The handshake connects combinations of voltage source(s) and/or current sink on D+/D- to signal input
source to raise output voltage from 5 V to 9 V / 12 V. The adjustable high voltage adapter handshake can be
disabled by clearing MAXC_EN and/or HVDCP_EN bits .
Non-Standard Adapter
Non-Standard
Adapter
(Divider 1: 2.1A)
(Divider 2: 2A)
(Divider 3: 1A)
(Divider 4: 2.4A)
Adapter Plug-in
or
EN_DPDM
USB BC1.2
Detection
SDP (USB500)
(500mA)
CDP
(1.5A)
Ajustable High Voltage Adapter
Handshake
0D[&KDUJHΠ$SDSWHU
(1.5A)
DCP
(3.25A)
Figure 9. USB D+/D- Detection
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Table 1. Non-Standard Adapter Detection
NON-STANDARD
ADAPTER
D+ THRESHOLD
D- THRESHOLD
INPUT CURRENT LIMIT
Divider 1
VD+ within V2P7_VTH
VD- within V2P0_VTH
2.1A
Divider 2
VD+ within V1P2_VTH
VD- within V1P2_VTH
2A
Divider 3
VD+ within V2P0_VTH
VD- within V2P7_VTH
1A
Divider 4
VD+ within V2P7_VTH
VD- within V2P7_VTH
2.4A
Table 2. Adjustable High Voltage Adapter D+/D- Output Configurations
ADJUSTABLE HIGH VOLTAGE HANDSHAKE
D+
D-
OUTPUT
MaxCharge (12V)
I1P6MA_ISINK
V3p45_VSRC
12 V
MaxCharge (9V)
V3p45_VSRC
I1P6MA_ISINK
9V
After the Input Source Type Detection is done, an INT pulse is asserted to the host. In addition, the following
registers including Input Current Limit register (IINLIM), VBUS_STAT, and SDP_STAT are updated as below:
Table 3. bq25890H Result
18
D+/D- DETECTION
INPUT CURRENT LIMIT
(IINLIM)
SDP_STAT
VBUS_STAT
USB SDP (USB500)
500 mA
1
001
USB CDP
1.5 A
1
010
USB DCP
3.25 A
1
011
Divider 3
1A
1
110
Divider 1
2.1 A
1
110
Divider 4
2.4 A
1
110
Divider 2
2A
1
110
MaxCharge
1.5 A
1
100
Unknown Adapter
500 mA
1
101
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8.2.3.3.2 Force Input Current Limit Detection
In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is completed,
FORCE_DPDM bit returns to 0 by itself and Input Result is updated.
8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two
methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.
1. Absolute VINDPM (FORCE_VINDPM=1)
By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM
is writable and allows host to set the absolute threshold of VINDPM function.
2. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)
When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM
register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The
algorithm allows a wide range of adapter (VVBUS_OP) to be used with flexible VINDPM threshold.
After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.
8.2.3.5 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the
device limits input current to the lower value of ILIM pin and IILIM register (ICO_EN = 0) or IDPM_LIM register
(ICO_EN = 1).
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal sawtooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SYS and VBUS.
8.2.4 Input Current Optimizer (ICO)
The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without overload
the input source. The algorithm automatically identify maximum input current limit of power source without
entering VINDPM to avoid input source overload.
This feature is enabled by default (ICO_EN=1) and can be disabled by setting ICO_EN bit to 0. After DCP or
MaxCharge type input source is detected based on the procedures previously described (Input Source Type
Detection ). The algorithm runs automatically when ICO_EN bit is set. The algorithm can also be forced to
execute by setting FORCE_ICO bit regardless of input source type detected.
The actual input current limit used by the Dynamic Power Management is reported in IDPM_LIM register while
Input Current Optimizer is enabled (ICO_EN = 1) or set by IINLIM register when the algorithm is disabled
(ICO_EN = 0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin
function.
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8.2.5 Boost Mode Operation from Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA (BOOST_LIM bits =
000) output requirement. The maximum output current is up to 2.4 A. The boost operation can be enabled if the
conditions are valid:
1. BAT above BATLOWV
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG pin HIGH and OTG_CONFIG bit =1)
4. Voltage at TS (thermistor) pin is within range configured by Boost Mode Temperature Monitor as configured
by BHOT and BCOLD bits
5. After 30 ms delay from boost mode enable
In boost mode, the device employs a 500 KHz or 1.5 MHz (selectable using BOOST_FREQ bit) step-up
switching regulator based on system requirements. To avoid frequency change during boost mode operations,
write to boost frequency configuration bit (BOOST_FREQ) is ignored when OTG_CONFIG is set.
During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5V by default
(selectable via BOOSTV register bits) and the output current can reach up to 2.4 A, selected via I2C
(BOOST_LIM bits). The boost output is maintained when BAT is above VOTG_BAT threshold
8.2.6 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.2.6.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage (default 3.5 V).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the
minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the
VDS of BATFET. The status register VSYS_STAT bit goes high when the system is in minimum system voltage
regulation.
4.4
System Voltage (V)
4.2
Minimum System Voltage
SYS (Charge Disabled)
SYS (Charge Enabled)
4
3.8
3.6
3.4
2.7
2.9
3.1
3.3
3.5
3.7
BAT (V)
3.9
4.1
4.3
D011
Figure 10. V(SYS) vs V(BAT)
20
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8.2.6.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below
the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below
the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the Supplement
Mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high.
Figure 11 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V
minimum system voltage setting.
Voltage
VBUS
SYS
3.6V
3.4V
3.2V
3.18V
BAT
Current
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
0.5A
IIN
-0.6A
DPM
DPM
Supplement
Figure 11. DPM Response
8.2.6.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low.
This prevents oscillation from entering and exiting the Supplement Mode. As the discharge current increases, the
BATFET gate is regulated with a higher voltage to reduce RDS(ON) until the BATFET is in full conduction. At this
point onwards, the BATFET VDS linearly increases with discharge current. Figure 12 shows the V-I curve of the
BATFET gate regulation operation. BATFET turns off to exit Supplement Mode when the battery is below battery
depletion threshold.
5.0
4.5
4.0
Current (A)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20 25 30 35
V(BAT_SYS) (mV)
40
45
50
55
D010
Figure 12. BATFET V-I Curve
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8.2.7 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 5-A charge current for high capacity battery. The 11-mΩ
BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.2.7.1 Autonomous Charging Cycle
With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is low), the device autonomously completes
a charging cycle without host involvement. The device default charging parameters are listed in Table 4. The
host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
Table 4. Charging Parameter Default Setting
A
•
•
•
•
•
DEFAULT MODE
bq25890
bq25892
Charging Voltage
4.208 V
4.208 V
Charging Current
2.048 A
2.048 A
Pre-charge Current
128 mA
128 mA
Termination Current
256 mA
256 mA
Temperature Profile
JEITA
JEITA
Safety Timer
12 hour
12 hour
new charge cycle starts when the following conditions are valid:
Converter starts
Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA
No thermistor fault on TS pin
No safety timer fault
BATFET is not forced to turn off (BATFET_DIS bit = 0)
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When
a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device
automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status
register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast
charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an
INT is asserted to notify the host.
8.2.7.2 Battery Charging Profile
The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the
beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.
Table 5. Charging Current Setting
22
VBAT
CHARGING CURRENT
REG DEFAULT SETTING
CHRG_STAT
3V
ICHG
2048 mA
10
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If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less
than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is
counted at half the clock rate.
Regulation Voltage
(3.84V t 4.608V)
Battery Voltage
Fast Charge Current
(128mA-5056mA)
Charge Current
VBAT_LOWV (2.8V/3V)
VBAT_SHORT (2V)
IPRECHARGE (64mA-1024mA)
ITERMINATION (64mA-1024mA)
IBATSHORT (100mA)
Trickle Charge
Pre-charge
Fast Charge and Voltage Regulation
Safety Timer
Expiration
Figure 13. Battery Charging Profile
8.2.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
8.2.7.4 Resistance Compensation (IRCOMP)
For high current charging system, resistance between charger output and battery cell terminal such as board
routing, connector, MOSFETs and sense resistor can force the charging process to move from constant current
to constant voltage too early and increase charge time. To speed up the charging cycle, the device provides
resistance compensation (IRCOMP) feature which can extend the constant current charge time to delivery
maximum power to battery.
The device allows the host to compensate for the resistance by increasing the voltage regulation set point based
on actual charge current and the resistance as shown below. For safe operation, the host should set the
maximum allowed regulation voltage register (VCLAMP) and the minimum resistance compensation (BATCOMP).
VREG_ACTUAL = VREG + min(ICHRG_ACTUAL x BATCOMP, VCLAMP)
(1)
8.2.7.5 Thermistor Qualification
8.2.7.5.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
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The device continuously monitors battery temperature by measuring the voltage between the TS pins and
ground, typically determined by a negative temperature coefficient thermistor (NTC) and an external voltage
divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To
initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the
T1–T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range. At cool temperature (T1–T2), JEITA recommends the charge current to be reduced to at least half of the
charge current or lower. At warm temperature (T3–T5), JEITA recommends charge voltage below nominal
charge voltage.
The device provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm
temperature (T3–T5) can be 200 mV below charge voltage (JEITA_VSET=0). The current setting at cool
temperature (T1–T2) can be further reduced to 20% or 50% of fast charge current (JEITA_ISET bit).
REGN
bq2589x
RT1
TS
RT2
RTH
103AT
Figure 14. TS Resistor Network
VREG
VREG - 200 mV
Figure 15. Charging Values
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 14, the value RT1 and RT2 can be
determined by using Equation 2: :
1 ö
æ 1
VREGN ´ RTHCOLD ´ RTHHOT ´ ç
÷
è VT1 VT5 ø
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç REGN - 1÷ - RTHCOLD ´ ç REGN - 1÷
è VT5
ø
è VT1
ø
VREGN
-1
VT1
RT1 =
1
1
+
RT2 RTHCOLD
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery,
RTHT1 = 27.28 kΩ
RTHT5 = 3.02 kΩ
RT1 = 5.24 kΩ
24
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RT2 = 30.31 kΩ
8.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx to
VBHOT2 thresholds unless boost mode temperature is disabled by setting BHOT bits to 11. When temperature is
outside of the temperature thresholds, the boost mode is suspended. Once temperature is within thresholds, the
boost mode is recovered.
Temperature Range to
Boost
VREGN
V BCOLDx
Boost Disable
( - 10ºC / 20ºC)
Boost Enable
V
BHOTx
(55ºC / 60ºC / 65ºC)
Boost Disable
AGND
Figure 16. TS Pin Thermistor Sense Thresholds in Boost Mode
8.2.7.6 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 4 hours when the battery is below VBATLOWV threshold. The user can program fast charge safety
timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to
11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.
During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will
expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
8.2.8 Battery Monitor
The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system
voltage, thermistor ratio, and charging current, and charging current based on the device modes of operation.
The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be
configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second
continuous conversion.
For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the
conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The
conversion result is ready after tCONV (maximum 1 second).
For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During
active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides
conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when
CONV_RATE is cleared.
When battery monitor is active, the REGN power is enabled and can increase device quiescent current. In
battery only mode, the battery monitor is only active when V(BAT) > SYS_MIN setting in REG03.
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Table 6. Battery Monitor Modes of Operation
MODES OF OPERATION
PARAMETER
REGISTER
CHARGE
MODE
BOOST MODE
DISABLE CHARGE
MODE
BATTERY ONLY
MODE
Battery Voltage (VBAT)
REG0E
Yes
Yes
Yes
Yes
System Voltage (VSYS)
REG0F
Yes
Yes
Yes
Yes
Temperature (TS) Voltage (VTS)
REG10
Yes
Yes
Yes
Yes
VBUS Voltage (VVBUS)
REG11
Yes
Yes
Yes
NA
Charge Current (IBAT)
REG12
Yes
NA
NA
NA
8.2.9 Status/Control Outputs (STAT, INT and DSEL)
8.2.9.1 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in
Figure 47. The STAT pin function can be disable by setting STAT_DIS bit.
Table 7. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including recharge)
LOW
Charging complete
HIGH
Sleep mode, charge disable
HIGH
Charge suspend (Input overvoltage, TS fault, timer fault, input or system overvoltage).
Boost Mode suspend (due to TS Fault)
blinking at 1 Hz
8.2.9.2 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT notifies the system on the
device operation. The following events will generate 256-µs INT pulse.
• USB/adapter source identified (through PSEL or DPDM detection, with OTG pin)
• Good input source detected
– VBUS above battery (not in sleep)
– VBUS below VACOV threshold
– VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Input removed
• Charge Complete
• Any FAULT event in REG0C
When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads
the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively.
The 1st read reports the pre-existing fault register status and the 2nd read reports the current fault register status.
8.2.9.3 D+/D- Multiplexer Selection Control
The DSEL pin is normally grounded and pulled-up by internally to 5V during input source type detection (when
AUTO_DPDM_EN=1 or FORCE_DPDM=1). The pin is normally low and drives high to indicate the D+/Ddetection is in progress. When detection is completed, the pin maintains high logic when DCP, MaxCharge or
HVDCP is detected. The pin returns to logic low when other input source type is detected. In addition, while input
source is plugged in or during OTG mode, the FORCE_DSEL bit can be set to force the DSEL pin to change
from low to high regardless of input source type detected. When in battery discharge mode (not in OTG), the
DSEL pin is always low.
26
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8.2.10 BATET (Q4) Control
8.2.10.1 BATFET Disable Mode (Shipping Mode)
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When
the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configurated
by BATFET_DLY bit.
8.2.10.2 BATFET Enable (Exit Shipping Mode)
When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following
events can enable BATFET to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping
mode
8.2.10.3 BATFET Full System Reset
The BATFET functions as a load switch between battery and system when input source is not plugged-in. By
changing the state of BATFET from off to on, system connects to SYS can be effectively have a power-on-reset.
The QON pin supports push-button interface to reset system power without host by change the state of BATFET.
When the QON pin is driven to logic low for tQON_RST (typical 15 seconds) while input source is not plugged in
and BATFET is enabled (BATFET_DIS=0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to
reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0.
8.2.11 Current Pulse Control Protocol
The device provides the control to generate the VBUS current pulse protocol to communicate with adjustable
high voltage adapter in order to signal adapter to increase or decrease output voltage. To enable the interface,
the EN_PUMPX bit must be set. Then the host can select the increase/decrease voltage pulse by setting one of
the PUMPX_UP or PUMPX_DN bit (but not both) to start the VBUS current pulse sequence. During the current
pulse sequence, the PUMPX_UP and PUMPX_DN bits are set to indicate pulse sequence is in progress and the
device pulses the input current limit between current limit set forth by IINLIM or IDPM_LIM register and the
100mA current limit (IINDPM100_ACC). When the pulse sequence is completed, the input current limit is returned to
value set by IINLIM or IDPM_LIM register and the PUMPX_UP or PUMPX_DN bit is cleared. In addition, the
EN_PUMPX can be cleared during the current pulse sequence to terminate the sequence and force charger to
return to input current limit as set forth by the IINLIM or IDPM_LIM register immediately. When EN_PUMPX bit is
low, write to PUMPX_UP and PUMPX_DN bit would be ignored and have no effect on VBUS current limit.
8.2.12 D+/D- Output Driver
The device provides independent controlled voltage output drivers on D+ and D- pins to interface or emulate
non-standard adapters when input source is plugged-in or OTG mode is enabled. The D+/D- drivers are disabled
in high impedance mode (HiZ) by default or when DP_DAC or DM_DAC bits are set to 000. The drivers are
enabled and controlled independently with predefined voltage threshold when DP_DAC and DM_DAC bits are
set to values between 001 to 110.
When input source is plugged-in, the output drivers control (DP_DAC and DM_DAC) are reset to HiZ (000) to
execute USB BC1.2 and built-in handshake during the input source type detection. The host is recommended to
change DP_DAC and DM_DAC settings after input source type detection when VBUS_STAT/PG_STAT bits are
updated.
When OTG mode is enabled, the drivers can be enabled to provide electrical signature on D+/D- to emulate USB
non-standard adapters (Divider 1-4) as shown in Table 1.
8.2.13 Input Current Limit on ILIM
For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.
The input maximum current is set by a resistor from ILIM pin to ground as:
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IINMAX =
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KILIM
RILIM
(3)
The actual input current limit is the lower value between ILIM setting and register setting (IINLIM). For example, if
the register setting is 111111 for 3.25 A, and ILIM has a 260-Ω resistor (KILIM = 390 max.) to ground for 1.5 A,
the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings
when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters
input current regulation (Refer to Dynamic Power Management section).
The ILIM pin can also be used to monitor input current when EN_ILIM is enabled. The voltage on ILIM pin is
proportional to the input current. ILIM pin can be used to monitor the input current following Equation 4:
IIN =
KILIM x VILIM
RILIM x 0.8 V
(4)
For example, if ILIM pin is set with 260-Ω resistor, and the ILIM voltage is 0.4 V, the actual input current 0.615 A
- 0.75 A (based on KILM specified). If ILIM pin is open, the input current is limited to zero since ILIM voltage
floats above 0.8 V. If ILIM pin is short, the input current limit is set by the register.
The ILIM pin function can be disabled by setting EN_ILIM bit to 0. When the pin is disabled, both input current
limit function and monitoring function are not available.
8.2.14 Thermal Regulation and Thermal Shutdown
8.2.14.1 Thermal Protection in Buck Mode
The device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface
temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit
(TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60ºC to 120ºC
allows the user to optimize the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register
THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host. The
BATFET and converter is enabled to recover when IC temperature is below TSHUT_HYS.
8.2.14.2 Thermal Protection in Boost Mode
The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
surface temperature exceeds TSHUT, the boost mode is disabled (converter is turned off) by setting
OTG_CONFIG bit low and BATFET is turned off. When IC surface temperature is below TSHUT_HYS, the BATFET
is enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.
8.2.15 Voltage and Current Monitoring in Buck and Boost Mode
8.2.15.1 Voltage and Current Monitoring in Buck Mode
The device closely monitors the input and system voltage, as well as HSFET current for safe buck and boost
mode operations.
8.2.15.1.1 Input Overvoltage (ACOV)
The input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops
switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT
is asserted to the host..
8.2.15.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to
clamp the overshoot.
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8.2.15.2 Voltage and Current Monitoring in Boost Mode
The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode
operation.
8.2.15.2.1 VBUS Overcurrent Protection
The charger device closely monitors the RBFET (Q1), and LSFET (Q3) current to ensure safe boost ode
operation. During overcurrent condition when output current exceed (IOTG_OCP) the device operates in hiccup
mode for protection. While in hiccup mode cycle, the device turns off RBFET for tOTG_OCP_OFF (30 ms typical) and
turns on RBFET for tOTG_OCP_ON (250 µs typical) in an attempt to restart. If the overcurrent condition is removed,
the boost converter returns to normal operation. When overcurrent condition continues to exist, the device
repeats the hiccup cycle until overcurrent condition is removed. When overcurrent condition is detected the fault
register bit BOOST_FAULT is set high to indicate fault in boost operation. An INT is also asserted to the host.
8.2.15.2.2 Boost Mode Overvoltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage
protection which stops switching, clears OTG_CONFIG bit and exits boost mode. During the overvoltage
duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also
asserted to the host.
8.2.16 Battery Protection
8.2.16.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT
is asserted to the host.
8.2.16.2 Battery Over-Discharge Protection
When battery is discharged below VBAT_DPL, the BATFET is turned off to protect battery from over discharge. To
recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the
BATFET turns on. Thy is charged with IBATSHORT (typically 100 mA) current when the VBAT < VSHORT, or
precharge current as set in IPRECHG register when the battery voltage is between VSHORT and VBATLOWV.
8.2.16.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (IBAT > IBATOP) so that its current exceeds the overcurrent
limit, the device latches off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET
8.2.17 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals
to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6AH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
8.2.17.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
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SDA
SCL
Change
of data
allowed
Data line stable;
Data valid
Figure 17. Bit Transfer on the I2C Bus
8.2.17.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
STOP (P)
START (S)
Figure 18. START and STOP conditions
8.2.17.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement
signal from revceiver
Acknowledgement
signal from slave
MSB
S or Sr
START or
Repeated
START
1
2
7
8
9
ACK
1
2
8
9
ACK
P or
Sr
STOP or
Repeated
START
Figure 19. Data Transfer on the I2C Bus
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8.2.17.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.2.17.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
SCL
S
1-7
START
ADDRESS
8
9
R/W
8
1-7
ACK
9
DATA
DATA
ACK
9
P
ACK
STOP
8
1-7
Figure 20. Complete Data Transfer
8.2.17.6 Single Read and Write
1
7
1
1
8
1
8
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
Data Addr
ACK
P
Figure 21. Single Write
1
7
1
1
8
1
1
7
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
S
Slave Address
1
ACK
8
1
1
Data
NCK
P
Figure 22. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
8.2.17.7 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.
Figure 23. Multi-Write
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Figure 24. Multi-Read
REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the
fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault
information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and
multi-write.
8.3 Device Functional Modes
8.3.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used an autonomous charger with no host or while host is in sleep mode. When the
charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings.
In default mode, the device keeps charging the battery with 12-hour fast charging safety timer. At the end of the
12-hour, the charging is stopped and the buck converter continues to operate to supply system load. Any write
command to device transitions the charger from default mode to host mode. All the device parameters can be
programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1
to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by
setting WATCHDOG bits=00.
When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all
registers are reset to default values except IINLIM, VINDPM, VINDPM_OS, BATFET_RST_EN, BATFET_DLY,
and BATFET_DIS bits.
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Device Functional Modes (continued)
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Y
I2C Write?
Start watchdog timer
Host programs registers
N
Default Mode
Y
Reset watchdog timer
Reset selective registers
N
WD_RST bit = 1?
Y
N
I2C Write?
Y
Watchdog Timer
Expired?
N
Figure 25. Watchdog Timer Flow Chart
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8.4 Register Maps
I2C Slave Address: 6AH (1101010B + R/W)
8.4.1 REG00
Figure 26. REG00
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. REG00
Bit
34
Field
Type
Reset
Description
7
EN_HIZ
R/W
by REG_RST
by Watchdog
Enable HIZ Mode
0 – Disable (default)
1 – Enable
6
EN_ILIM
R/W
by REG_RST
by Watchdog
Enable ILIM Pin
0 – Disable
1 – Enable (default: Enable ILIM pin (1))
5
IINLIM[5]
R/W
by REG_RST
1600mA
4
IINLIM[4]
R/W
by REG_RST
800mA
3
IINLIM[3]
R/W
by REG_RST
400mA
2
IINLIM[2]
R/W
by REG_RST
200mA
1
IINLIM[1]
R/W
by REG_RST
100mA
0
IINLIM[0]
R/W
by REG_RST
50mA
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Input Current Limit
Offset: 100mA
Range: 100mA (000000) – 3.25A (111111)
Default:0001000 (500mA)
(Actual input current limit is the lower of I2C or ILIM pin)
IINLIM bits are changed automaticallly after input source
type detection is completed
USB Host SDP = 500mA
USB CDP = 1.5A
USB DCP = 3.25A
Adjustable High Voltage (MaxCharge) DCP = 1.5A
Unknown Adapter = 500mA
Non-Standard Adapter = 1A/2A/2.1A/2.4A
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8.4.2 REG01
Figure 27. REG01
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. REG01
Bit
Field
Type
Reset
Description
7
DP_DAC[2]
R/W
by REG_RST
6
DP_DAC[1]
R/W
by REG_RST
5
DP_DAC[0]
R/W
by REG_RST
D+ Pin Output Driver
000 – HiZ mode (Default)
001 – 0V (V0P0_VSRC )
010 – 0.6V (V0P6_VSRC )
011 – 1.2V (V1P2_VSRC )
100 – 2.0V (V2P0_VSRC )
101 – 2.7V (V2P7_VSRC )
110 – 3.3V (V3P3_VSRC )
111 – Reserved
Register bits are reset to default value when input source is plugged-in
and can be changed after D+/D- detection is completed.
4
DM_DAC[2]
R/W
by REG_RST
3
DM_DAC[1]
R/W
by REG_RST
2
DM_DAC[0]
R/W
by REG_RST
1
EN_12V
R/W
by REG_RST
Enable 12V detection for MaxCharge and HVDCP
0 – Disable 12V Detection (default)
1 – Enable 12V Detection
0
VINDPM_OS
R/W
by REG_RST
Input Voltage Limit Offset
0 – 400mV
1 – 600mV (default)
D- Pin Output Driver
000 – HiZ mode (Default)
001 – 0V (V0P0_VSRC )
010 – 0.6V (V0P6_VSRC )
011 – 1.2V (V1P2_VSRC )
100 – 2.0V (V2P0_VSRC )
101 – 2.7V (V2P7_VSRC )
110 – 3.3V (V3P3_VSRC )
111 – Reserved
Register bits are reset to default value when input source is plugged-in
and can be changed after D+/D- detection is completed.
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8.4.3 REG02
Figure 28. REG02
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. REG02
Bit
36
Field
Type
Reset
Description
ADC Conversion Start Control
0 – ADC conversion not active (default).
1 – Start ADC Conversion
This bit is read-only when CONV_RATE = 1. The bit stays high during
ADC conversion and during input source detection.
7
CONV_START
R/W
by REG_RST
by Watchdog
6
CONV_RATE
R/W
by REG_RST
by Watchdog
ADC Conversion Rate Selection
0 – One shot ADC conversion (default)
1 – Start 1s Continuous Conversion
5
BOOST_FREQ
R/W
by REG_RST
by Watchdog
Boost Mode Frequency Selection
0 – 1.5MHz
1 – 500KHz
Note: Write to this bit is ignored when OTG_CONFIG is enabled.
4
ICO_EN
R/W
by REG_RST
Input Current Optimizer (ICO) Enable
0 – Disable ICO Algorithm
1 – Enable ICO Algorithm (default)
3
HVDCP_EN
R/W
by REG_RST
High Voltage DCP Enable
0 – Disable HVDCP handshake
1 – Enable HVDCP handshake (default)
2
MAXC_EN
R/W
by REG_RST
MaxCharge Adapter Enable
0 – Disable MaxCharge handshake
1 – Enable MaxCharge handshake (default)
1
FORCE_DPDM
R/W
by REG_RST
by Watchdog
Force D+/D- Detection
0 – Not in D+/D- or PSEL detection (default)
1 – Force D+/D- detection
0
AUTO_DPDM_EN
R/W
by REG_RST
Automatic D+/D- Detection Enable
0 –Disable D+/D- or PSEL detection when VBUS is plugged-in
1 –Enable D+/D- or PEL detection when VBUS is plugged-in (default)
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8.4.4 REG03
Figure 29. REG03
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
0
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. REG03
Bit
Field
Type
Reset
Description
7
FORCE_DSEL
R/W
by REG_RST
DSEL Pin Control
0 – Allow DSEL pin output to drive low (default)
1 – Force DSEL pin output to drive high
6
WD_RST
R/W
by REG_RST
by Watchdog
I2C Watchdog Timer Reset
0 – Normal (default)
1 – Reset (Back to 0 after timer reset)
5
OTG_CONFIG
R/W
by REG_RST
by Watchdog
Boost (OTG) Mode Configuration
0 – OTG Disable (default)
1 – OTG Enable
4
CHG_CONFIG
R/W
by REG_RST
by Watchdog
Charge Enable Configuration
0 - Charge Disable
1- Charge Enable (default)
3
SYS_MIN[2]
R/W
by REG_RST
0.4V
2
SYS_MIN[1]
R/W
by REG_RST
0.2V
1
SYS_MIN[02]
R/W
by REG_RST
0.1V
0
MIN_VBAT_SEL
R/W
by REG_RST
by Watchdog
Minimum Battery Voltage (falling) to exit boost mode
0 - 2.9V (default)
1- 2.5V
Minimum System Voltage Limit
Offset: 3.0V
Range 3.0V-3.7V
Default: 3.5V (101)
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8.4.5 REG04
Figure 30. REG04
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. REG04
Bit
38
Field
Type
Reset
Description
7
EN_PUMPX
R/W
by Softwareby
by Watchdog
Current pulse control Enable
0 - Disable Current pulse control (default)
1- Enable Current pulse control (PUMPX_UP and PUMPX_DN)
6
ICHG[6]
R/W
by Softwareby
by Watchdog
4096mA
5
ICHG[5]
R/W
by Softwareby
by Watchdog
2048mA
4
ICHG[4]
R/W
by Softwareby
by Watchdog
1024mA
3
ICHG[3]
R/W
by Softwareby
by Watchdog
512mA
2
ICHG[2]
R/W
by Softwareby
by Watchdog
256mA
1
ICHG[1]
R/W
by Softwareby
by Watchdog
128mA
0
ICHG[0]
R/W
by Softwareby
by Watchdog
64mA
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Fast Charge Current Limit
Offset: 0mA
Range: 0mA (0000000) – 5056mA (1001111)
Default: 2048mA (0100000)
Note:
ICHG=000000 (0mA) disables charge
ICHG > 1001111 (5056mA) is clamped to register value
1001111 (5056mA)
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8.4.6 REG05
Figure 31. REG05
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. REG05
Bit
Field
Type
Reset
Description
512mA
7
IPRECHG[3]
R/W
by Softwareby
by Watchdog
6
IPRECHG[2]
R/W
by Softwareby
by Watchdog
256mA
5
IPRECHG[1]
R/W
by Softwareby
by Watchdog
128mA
4
IPRECHG[0]
R/W
by Softwareby
by Watchdog
64mA
3
ITERM[3]
R/W
by Softwareby
by Watchdog
512mA
2
ITERM[2]
R/W
by Softwareby
by Watchdog
256mA
1
ITERM[1]
R/W
by Softwareby
by Watchdog
128mA
0
ITERM[0]
R/W
by Softwareby
by Watchdog
64mA
Precharge Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 128mA (0001)
Termination Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 256mA (0011)
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8.4.7 REG06
Figure 32. REG06
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. REG06
Bit
40
Field
Type
Reset
Description
512mV
7
VREG[5]
R/W
by Softwareby
by Watchdog
6
VREG[4]
R/W
by Softwareby
by Watchdog
256mV
128mV
Charge Voltage Limit
Offset: 3.840V
Range: 3.840V – 4.608V (110000)
Default: 4.208V (010111)
Note:
VREG > 110000 (4.608V) is clamped to register value
110000 (4.608V)
5
VREG[3]
R/W
by Softwareby
by Watchdog
4
VREG[2]
R/W
by Softwareby
by Watchdog
64mV
3
VREG[1]
R/W
by Softwareby
by Watchdog
32mV
2
VREG[0]
R/W
by Softwareby
by Watchdog
16mV
1
BATLOWV
R/W
by Softwareby
by Watchdog
Battery Precharge to Fast Charge Threshold
0 – 2.8V
1 – 3.0V (default)
0
VRECHG
R/W
by Softwareby
by Watchdog
Battery Recharge Threshold Offset
(below Charge Voltage Limit)
0 – 100mV (VRECHG) below VREG (REG06[7:2]) (default)
1 – 200mV (VRECHG) below VREG (REG06[7:2])
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8.4.8 REG07
Figure 33. REG07
7
1
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. REG07
Bit
Field
Type
Reset
Description
7
EN_TERM
R/W
by Softwareby
by Watchdog
Charging Termination Enable
0 – Disable
1 – Enable (default)
6
STAT_DIS
R/W
by Softwareby
by Watchdog
STAT Pin Disable
0 – Enable STAT pin function (default)
1 – Disable STAT pin function
5
WATCHDOG[1]
R/W
by Softwareby
by Watchdog
4
WATCHDOG[0]
R/W
by Softwareby
by Watchdog
3
EN_TIMER
R/W
by Softwareby
by Watchdog
2
CHG_TIMER[1]
R/W
by Softwareby
by Watchdog
1
CHG_TIMER[0]
R/W
by Softwareby
by Watchdog
0
JEITA_ISET (0C-10C)
R/W
by Software
by Watchdog
I2C Watchdog Timer Setting
00 – Disable watchdog timer
01 – 40s (default)
10 – 80s
11 – 160s
Charging Safety Timer Enable
0 – Disable
1 – Enable (default)
Fast Charge Timer Setting
00 – 5 hrs
01 – 8 hrs
10 – 12 hrs (default)
11 – 20 hrs
JEITA Low Temperature Current Setting
0 – 50% of ICHG (REG04[6:0])
1 – 20% of ICHG (REG04[6:0]) (default)
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8.4.9 REG08
Figure 34. REG08
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. REG08
Bit
42
Field
Type
Reset
Description
80mΩ
7
BAT_COMP[2]
R/W
by Softwareby
by Watchdog
6
BAT_COMP[1]
R/W
by Softwareby
by Watchdog
40mΩ
5
BAT_COMP[0]
R/W
by Softwareby
by Watchdog
20mΩ
4
VCLAMP[2]
R/W
by Softwareby
by Watchdog
128mV
64mV
32mV
3
VCLAMP[1]
R/W
by Softwareby
by Watchdog
2
VCLAMP[0]
R/W
by Softwareby
by Watchdog
1
TREG[1]
R/W
by Softwareby
by Watchdog
0
TREG[0]
R/W
by Softwareby
by Watchdog
IR Compensation Resistor Setting
Range: 0 – 140mΩ
Default: 0Ω (000) (i.e. Disable IRComp)
IR Compensation Voltage Clamp
above VREG (REG06[7:2])
Offset: 0mV
Range: 0-224mV
Default: 0mV (000)
Thermal Regulation Threshold
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (default)
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8.4.10 REG09
Figure 35. REG09
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. REG09
Bit
7
Field
FORCE_ICO
Type
Reset
Description
R/W
by Softwareby
by Watchdog
Force Start Input Current Optimizer (ICO)
0 – Do not force ICO (default)
1 – Force ICO
Note:
This bit is can only be set only and always returns to 0 after ICO starts
Safety Timer Setting during DPM or Thermal Regulation
0 – Safety timer not slowed by 2X during input DPM or thermal
regulation
1 – Safety timer slowed by 2X during input DPM or thermal regulation
(default)
6
TMR2X_EN
R/W
by Softwareby
by Watchdog
5
BATFET_DIS
R/W
by Softwareby
Force BATFET off to enable ship mode
0 – Allow BATFET turn on (default)
1 – Force BATFET off
4
JEITA_VSET (45C-60C)
R/W
by Software
by Watchdog
JEITA High Temperature Voltage Setting
0 – Set Charge Voltage to VREG-200mV during JEITA hig temperature
(default)
1 – Set Charge Voltage to VREG during JEITA high temperature
3
BATFET_DLY
R/W
by Softwareby
BATFET turn off delay control
0 – BATFET turn off immediately when BATFET_DIS bit is set (default)
1 – BATFET turn off delay by tSM_DLY when BATFET_DIS bit is set
2
BATFET_RST_EN
R/W
by Softwareby
BATFET full system reset enable
0 – Disable BATFET full system reset
1 – Enable BATFET full system reset (default)
by Softwareby
by Watchdog
Current pulse control voltage up enable
0 – Disable (default)
1 – Enable
Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0
after current pulse control sequence is completed
by Softwareby
by Watchdog
Current pulse control voltage down enable
0 – Disable (default)
1 – Enable
Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0
after current pulse control sequence is completed
1
0
PUMPX_UP
PUMPX_DN
R/W
R/W
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8.4.11 REG0A
Figure 36. REG0A
7
0
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. REG0A
Bit
44
Field
Type
Reset
Description
512mV
7
BOOSTV[3]
R/W
by Softwareby
by Watchdog
6
BOOSTV[2]
R/W
by Softwareby
by Watchdog
256mV
5
BOOSTV[1]
R/W
by Softwareby
128mV
64mV
PFM mode allowed in boost mode
0 – Allow PFM in boost mode (default)
1 – Disable PFM in boost mode
4
BOOSTV[0]
R/W
by Softwareby
by Watchdog
3
PFM_OTG_DIS
R/W
by Software
2
BOOST_LIM[2]
R/W
by Software
by Watchdog
1
BOOST_LIM[1]
R/W
by Software
by Watchdog
0
BOOST_LIM[0]
R/W
by Software
by Watchdog
000: 0.5A
001: 0.75A
010: 1.2A
011: 1.4A
100: 1.65A
101: 1.875A
110: 2.15A
111: 2.45A
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Boost Mode Voltage Regulation
Offset: 4.55V
Range: 4.55V – 5.51V
Default:4.998V(0111)
Boost Mode Current Limit
Default: 1.4A (011)
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8.4.12 REG0B
Figure 37. REG0B
7
x
R
6
x
R
5
x
R
4
x
R
3
x
R
2
x
R
1
x
R
0
x
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. REG0B
Bit
Field
Type
Reset
Description
7
VBUS_STAT[2]
R
N/A
6
VBUS_STAT[1]
R
N/A
5
VBUS_STAT[0]
R
N/A
VBUS Status register
000: No Input 001: USB Host SDP
010: USB CDP (1.5A)
011: USB DCP (3.25A)
100: Adjustable High Voltage DCP (MaxCharge) (1.5A)
101: Unknown Adapter (500mA)
110: Non-Standard Adapter (1A/2A/2.1A/2.4A)
111: OTG Note: Software current limit is reported in IINLIM register
4
CHRG_STAT[1]
R
N/A
3
CHRG_STAT[0]
R
N/A
2
PG_STAT
R
N/A
1
Reserved
0
VSYS_STAT
Charging Status
00 – Not Charging
01 – Pre-charge ( < VBATLOWV)
10 – Fast Charging
11 – Charge Termination Done
Power Good Status
0 – Not Power Good
1 – Power Good
Reserved: Always reads 0
R
N/A
VSYS Regulation Status
0 – Not in VSYSMIN regulation (BAT > VSYSMIN)
1 – In VSYSMIN regulation (BAT < VSYSMIN)
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8.4.13 REG0C
Figure 38. REG0C
7
x
R
6
x
R
5
x
R
4
x
R
3
x
R
2
x
R
1
x
R
0
x
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. REG0C
Bit
46
Field
Type
Reset
Description
7
WATCHDOG_FAULT
R
N/A
Watchdog Fault Status
Status 0 – Normal
1- Watchdog timer expiration
6
BOOST_FAULT
R
N/A
Boost Mode Fault Status
0 – Normal
1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low in
boost mode
5
CHRG_FAULT[1]
R
N/A
4
CHRG_FAULT[0]
R
N/A
3
BAT_FAULT
R
N/A
2
NTC_FAULT[2]
R
N/A
1
NTC_FAULT[1]
R
N/A
0
NTC_FAULT[0]
R
N/A
Charge Fault Status
00 – Normal
01 – Input fault (VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V)
)
10 - Thermal shutdown
11 – Charge Safety Timer Expiration
Battery Fault Status
0 – Normal
1 – BATOVP (VBAT > VBATOVP)
NTC Fault Status
Buck Mode:
000 – Normal
010 – TS Warm
011 – TS Cool
101 – TS Cold
110 – TS Hot
Boost Mode:
000 – Normal
101 – TS Cold
110 – TS Hot
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8.4.14 REG0D
Figure 39. REG0D
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. REG0D
Bit
Field
Type
Reset
Description
7
FORCE_VINDPM
R/W
by Softwareby
VINDPM Threshold Setting Method
0 – Run Relative VINDPM Threshold (default)
1 – Run Absolute VINDPM Threshold
Note: Register is reset to default value when input source is plugged-in
6
VINDPM[6]
R/W
by Softwareby
6400mV
5
VINDPM[5]
R/W
by Softwareby
3200mV
4
VINDPM[4]
R/W
by Softwareby
1600mV
3
VINDPM[3]
R/W
by Softwareby
800mV
2
VINDPM[2]
R/W
by Softwareby
400mV
1
VINDPM[1]
R/W
by Softwareby
200mV
0
VINDPM[0]
R/W
by Softwareby
100mV
Absolute VINDPM Threshold
Offset: 2.6V
Range: 3.9V (0001101) – 15.3V (1111111)
Default: 4.4V (0010010)
Note:
Value < 0001101 is clamped to 3.9V (0001101)
Register is read only when FORCE_VINDPM=0 and can
be written by internal control based on relative VINDPM
threshold setting
Register can be read/write when FORCE_VINDPM = 1
Note: Register is reset to default value when input source
is plugged-in
8.4.15 REG0E
Figure 40. REG0E
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. REG0E
Bit
Field
Type
Reset
Description
7
THERM_STAT
R
N/A
Thermal Regulation Status
0 – Normal
1 – In Thermal Regulation
6
BATV[6]
R
N/A
1280mV
5
BATV[5]
R
N/A
640mV
4
BATV[4]
R
N/A
320mV
3
BATV[3]
R
N/A
160mV
2
BATV[2]
R
N/A
80mV
1
BATV[1]
R
N/A
40mV
0
BATV[0]
R
N/A
20mV
ADC conversion of Battery Voltage (VBAT)
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
Default: 2.304V (0000000)
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8.4.16 REG0F
Figure 41. REG0F
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. REG0F
Bit
Field
Type
Reset
Description
7
Reserved
R
N/A
Reserved: Always reads 0
6
SYSV[6]
R
N/A
1280mV
5
SYSV[5]
R
N/A
640mV
4
SYSV[4]
R
N/A
320mV
3
SYSV[3]
R
N/A
160mV
2
SYSV[2]
R
N/A
80mV
1
SYSV[1]
R
N/A
40mV
0
SYSV[0]
R
N/A
20mV
ADDC conversion of System Voltage (VSYS)
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
Default: 2.304V (0000000)
8.4.17 REG10
Figure 42. REG10
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. REG10
Bit
48
Field
Type
Reset
Description
7
Reserved
R
N/A
Reserved: Always reads 0
6
TSPCT[6]
R
N/A
29.76%
5
TSPCT[5]
R
N/A
14.88%
4
TSPCT[4]
R
N/A
7.44%
3
TSPCT[3]
R
N/A
3.72%
2
TSPCT[2]
R
N/A
1.86%
1
TSPCT[1]
R
N/A
0.93%
0
TSPCT[0]
R
N/A
0.465%
ADC conversion of TS Voltage (TS) as percentage of REGN
Offset: 21%
Range 21% (0000000) – 80% (1111111)
Default: 21% (0000000)
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8.4.18 REG11
Figure 43. REG11
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. REG11
Bit
Field
Type
Reset
Description
7
VBUS_GD
R
N/A
VBUS Good Status
0 – Not VBUS attached
1 – VBUS Attached
6
VBUSV[6]
R
N/A
6400mV
5
VBUSV[5]
R
N/A
3200mV
4
VBUSV[4]
R
N/A
1600mV
3
VBUSV[3]
R
N/A
800mV
2
VBUSV[2]
R
N/A
400mV
1
VBUSV[1]
R
N/A
200mV
0
VBUSV[0]
R
N/A
100mV
ADC conversion of VBUS voltage (VBUS)
Offset: 2.6V
Range 2.6V (0000000) – 15.3V (1111111)
Default: 2.6V (0000000)
8.4.19 REG12
Figure 44. REG12
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. REG12
Bit
Field
Type
Reset
Description
7
Unused
R
N/A
Always reads 0
6
ICHGR[6]
R
N/A
3200mA
5
ICHGR[5]
R
N/A
1600mA
4
ICHGR[4]
R
N/A
800mA
3
ICHGR[3]
R
N/A
400mA
2
ICHGR[2]
R
N/A
200mA
1
ICHGR[1]
R
N/A
100mA
0
ICHGR[0]
R
N/A
50mA
ADC conversion of Charge Current (IBAT) when VBAT >
VBATSHORT
Offset: 0mA
Range 0mA (0000000) – 6350mA (1111111)
Default: 0mA (0000000)
Note:
This register returns 0000000 for VBAT < VBATSHORT
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8.4.20 REG13
Figure 45. REG13
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. REG13
Bit
Field
Type
Reset
Description
7
VDPM_STAT
R
N/A
VINDPM Status
0 – Not in VINDPM
1 – VINDPM
6
IDPM_STAT
R
N/A
IINDPM Status
0 – Not in IINDPM
1 – IINDPM
5
IDPM_LIM[5]
R
N/A
1600mA
4
IDPM_LIM[4]
R
N/A
800mA
3
IDPM_LIM[3]
R
N/A
400mA
2
IDPM_LIM[2]
R
N/A
200mA
1
IDPM_LIM[1]
R
N/A
100mA
0
IDPM_LIM[0]
R
N/A
50mA
Input Current Limit in effect while Input Current Optimizer
(ICO) is enabled
Offset: 100mA (default)
Range 100mA (0000000) – 3.25mA (1111111)
8.4.21 REG14
Figure 46. REG14
7
0
R/W
6
0
R/W
5
0
R
4
1
R
3
1
R
2
1
R
1
1
R
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. REG14
Bit
50
Field
Type
Reset
Description
7
REG_RST
R/W
N/A
Register Reset
0 – Keep current register setting (default)
1 – Reset to default register value and reset safety timer
Note:
Reset to 0 after register reset is completed
6
ICO_OPTIMIZED
R
N/A
Input Current Optimizer (ICO) Status
0 – Optimization is in progress
1 – Maximum Input Current Detected
5
PN[2]
R
N/A
4
PN[1]
R
N/A
3
PN[0]
R
N/A
2
TS_PROFILE
R
N/A
1
DEV_REV[1]
R
N/A
0
DEV_REV[0]
R
N/A
Device Configuration
011: bq25890H
Temperature Profile
1- JEITA
Device Revision: 11
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: BQ25890H
BQ25890H
www.ti.com
SLUSCC5A – SEPTEMBER 2016 – REVISED MAY 2018
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also
integrates a bootstrap diode for the high-side gate drive.
9.2 Typical Application
Input
3.9Vt14V at 3A
OTG
5V at 2.4A
1 F
VBUS
PMID
C1
1 H
SYS 3.5Vt4.5V
SW
47nF
USB
47nF
DSEL
D+
Optional
D260Q
10 F
4.7 F
1 F
PGND
ILIM
10 F
BTST
REGN
SYS
SYS
Ichg = 5A
BAT
10 F
QON
VREF
2.2
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