Not Recommended For New Designs
bq27000, bq27200
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SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
SINGLE CELL Li-Ion AND Li-Pol BATTERY GAS GAUGE IC FOR PORTABLE
APPLICATIONS (bqJUNIOR)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
2
HDQ (bq27000) or I C (bq27200)
Communication
Reports Accurate Time-to-Empty With
Measured Load and Historical Maximum and
Standby Loads
Reports Temperature, Voltage, and Current
High Accuracy Charge and Discharge Current
Integration with Automatic Offset Calibration
Requires No User Calibration
Programmable Input/Output Port
Internal User EEPROM Configuration Memory
Automatic Capacity Reduction With Age
Stable Oscillator Without External
Components
Dynamic End-of-Discharge Detection Delay to
Allow Use in a High-Dynamic Load
Environment
Automatic Sleep Mode When Communication
Lines are Low
Available in a Small 3 mm x 4 mm QFN
Package
Five Low-Power Operating Modes
– Active: < 90 µA
– Sleep: < 2.5 µA
– Ship: < 2 µA (bq27000 only)
– Hibernate: < 1.5 µA
– Data Retention: < 20 nA
•
•
•
•
•
•
PDA
Smart Phones
MP3 Players
Digital Cameras
Internet Appliances
Handheld Devices
DESCRIPTION
The bqJUNIOR™ series are highly accurate
stand-alone single-cell Li-Ion and Li-Pol battery
capacity monitoring and reporting devices targeted at
space-limited, portable applications. The IC monitors
a voltage drop across a small current sense resistor
connected in series with the battery to determine
charge and discharge activity of the battery.
Compensations
for
battery
temperature,
self-discharge, and discharge rate are applied to the
capacity
measurments
to
provide
available
time-to-empty information across a wide range of
operating conditions. Battery capacity is automatically
recalibrated, or learned, in the course of a discharge
cycle from full to empty. Internal registers include
current, capacity, time-to-empty, state-of-charge, cell
temperature and voltage, status, and more.
The bqJUNIOR can operate directly from single-cell
Li-Ion and Li-Pol batteries and communicates to the
system over a HDQ one-wire or I2C serial interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
bqJUNIOR is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated
bq27000, bq27200
Not Recommended For New Designs
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SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
TYPICAL APPLICATION
PACK+
PGM TP
R3
1 kΩ
1
C4
0.1 µF
+
R4
10 kΩ
Li-Ion
or
Li-Pol
bq27000DRK
2
VCC
3
VSS
GPIO 9
R1
1 kΩ
SRP 8
C3
0.1 µF
C1
0.1 µF
4
R7
100 Ω
PGM 10
RBI
D/C
RS
0.02 Ω
SRN 7
R2
1 kΩ
R8
100 Ω
HDQ
5
HDQ
D2
5.6 V
BAT 6
C3
0.1 µF
C2
0.1 µF
11
ESD Protection
Li-Ion Protector
PACK−
UDG−04096
ORDERING INFORMATION
TA
COMMUNICATION INTERFACE
PACKAGED DEVICES (1)
MARKINGS
HDQ
bq27000DRKR
27000
I2C
bq27200DRKR
27200
-20°C to 70°C
(1)
The DRK package is available taped and reeled only. Quantities are 2,000 devices per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
bq27000
bq27200
VCC
VIN
Supply voltage
Input voltage
(with respect to VSS)
-0.3 to 7
SRP, SRN, RBI, BAT (all with respect to VSS)
-0.3 to
VCC+0.3
HDQ, SCL, SDA, GPIO (all with respect to
VSS)
-0.3 to 7
PGM (with respect to VSS) during EEPROM
programming
-0.3 to 22
ISINK
Output sink current
TA
Operating free-air temperature range
-20 to 70
Tstg
Storage temperature range
-65 to 150
TJ
Operating junction temperature range
-40 to 125
Lead temperature (soldering, 10 sec)
300
2
GPIO, SCL, SDA, HDQ
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5
UNITS
V
mA
°C
Not Recommended For New Designs
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SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
VCC
Supply voltage
2.6
4.5
V
TA
Operating free-air temperature
–20
70
°C
–100
100
mV
Input voltage, SRP and SRN with respect to VSS
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range and supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
ICC(VCC)
Active current
52
90
ICC(SLP)
Sleep current
1.0
2.5
ICC(SHP)
Ship current (bq27000 only)
0.9
2.0
ICC(POR)
Hibernate current
0 < VCC < 1.5 V
0.6
1.5
RBI current
RBI pin only, VCC <
VCC(POR)
4.2 V
1.7
Low-level output voltage (GPIO)
IOL = 1 mA
0.4
Low-level output voltage (HDQ, SCL, SDA)
IOL = 2 mA
0.4
VOLTAGE AND TEMPERATURE MEASUREMENT
Measurement range
VCC = V(BAT)
2.6
Reported voltage resolution
4.5
2.7
Reported accuacy
-25
Voltage update time
25
2.56
Reported temperature resolution
-3
Temperature update time
3
2.56
VSRP-VSRN differential input
mV
s
0.25
Reported temperature accuracy
V
°K
s
–100
100
-2.2%
1.5%
mV
TIME, CURRENT AND CAPACITY (3.0 V ≤ VCC≤ 4.2 V, 0°C ≤ TA≤ 50°C)
fOSC
Internal oscillator frequency
Current gain variability
-0.5%
0.5%
Coulometric gain variability
-1.7%
0.5%
Coulomb counter input offset (1)
-15
EEPROM PROGRAMMING ( VCC≥ 3.0 V, -20°C ≤ TA≤
(1)
(2)
0
15
µV
35°C) (2)
Programming voltage rise time
0.5
1.5
ms
Programming voltage high time
10
100
ms
Programming voltage fall time
0.5
1.5
ms
20
22
V
15
mA
Programming voltage
Applied to PGM pin
EEPROM programming current
VPROGRAM = 21 V
Excludes contributions to the offset due to PCB layout or other factors external to the bq27000/bq27200.
Maximum number of programming cycles on the EEPROM is 10 and data retention time is 10 years at TA = 85°C.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range and supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STANDARD HDQ SERIAL COMMUNICATION TIMING (bq27000 only)
t(B)
Break timing
t(BR)
Break recovery
190
40
t(CYCH)
Host bit window
190
t(HW1)
Host sends 1
0.5
50
t(HW0)
Host sends 0
86
145
t(RSPS)
bqJUNIOR to host response
190
320
t(CYCD)
bqJUNIOR bit window
190
250
t(DW1)
bqJUNIOR sends 1
32
50
t(DW0)
bqJUNIOR sends 0
80
145
µs
STANDARD I2C SERIAL COMMUNICATION TIMING (bq27200 only)
tr
SCL/SDA rise time
tf
SCL/SDA fall time
tw(H)
SCL pulse width (high)
tw(L)
SCL pulse width (low)
4.7
tsu(STA)
Setup for repeated start
4.7
td(STA)
Start to first falling edge of SCL
tsu(DAT)
Data setup time
250
th(DAT)
Data hold time
300
tsu(STOP)
Setup time for stop
t(BUF)
Bus free time between stop and start
f(SCL)
Clock frequency
t(BUSERR)
Bus error timeout
4
1
µs
300
ns
4
µs
4
ns
4
µs
4.7
17.3
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100
kHz
21.2
s
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SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
TIMING DIAGRAMS
t(BR)
t(B)
(a) Break and Break Recovery
t(HW1)
t(DW1)
t(DW0)
t(HW0)
t(CYCH)
t(CYCD)
(b) Host Transmitted Bit
Break
(c) bqJUNIOR Transmitted Bit
1-Bit
R/W
7−Bit Address
8−Bit Data
t(RSPS)
UDG−03039
(d) bqJUNIOR to Host Response
Figure 1. HDQ Bit Timing Diagram
tsu(STA)
tw(H)
tf
tw(L)
tr
t(BUF)
SCL
SDA
td(STA)
tr
tf
tsu(STOP)
tsu(DAT)
th(DAT)
REPEATED
START
STOP
START
UDG−04122
2
Figure 2. I C Timing Diagram
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TIMING DIAGRAMS (continued)
BQ27000
DRK PACKAGE
(BOTTOM VIEW)
BQ27200
DRK PACKAGE
(BOTTOM VIEW)
RBI
VCC
VSS
D/C
HDQ
RBI
VCC
VSS
SCL
SDA
1
2
3
4
5
1
2
3
4
5
bq27000DRK
bq27200DRK
11
10
9
11
8
PGM GPIO SRP
7
6
10
SRN
BAT
9
PGM GPIO SRP
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
bq27000
bq27200
BAT
6
6
I
Battery voltage sense input
D/C
4
-
-
Do not connect. Must be left floating or tied to VSS
GPIO
9
9
I/O
General purpose input/output
HDQ
5
-
I/O
Single wire HDQ serial interface
PGM
10
10
I
EEPROM programming voltage input
RBI
1
1
I
Register back-up input
SCL
-
4
I
Serial clock input (I2C)
SDA
-
5
I/O
Serial data input (I2C)
SRN
7
7
I
Current sense input (negative)
SRP
8
8
I
Current sense input (positive)
VCC
2
2
I
VCC supply input
VSS
3
3
-
Ground input
VSS
11
11
-
Ground shield
6
8
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7
6
SRN
BAT
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SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006
FUNCTIONAL BLOCK DIAGRAMS
bq27000
VCC
Bandgap,
Reference
and Bias
2
Temperature
Compensated
Precision Oscillator
Clock
Generator
EEPROM
5
HDQ
9
GPIO
System I/O
and Control
SCPU
SRP
8
SRN
7
10 RGM
Autocalibration
and
Autocompensating
Coulomb Counter
RAM
Temperature
Sensor
BAT
1
RBI
3
VSS
ADC
6
UDG−03040
bq27200
VCC
2
Bandgap,
Reference
and Bias
Temperature
Compensated
Precision Oscillator
Clock
Generator
EEPROM
System I/O
and Control
4
SCL
5
SDA
9
GPIO
SCPU
SRP
8
SRN
7
10 RGM
Autocalibration and
Autocompensating
Coulomb Counter
Temperature
Sensor
BAT
RAM
1
RBI
3
VSS
ADC
6
UDG−04123
FUNCTIONAL DESCRIPTION
The bqJUNIOR determines battery capacity by monitoring the amount of charge input to or removed from a
Li-Ion or Li-Pol battery. The bqJUNIOR measures discharge and charge currents, monitors the battery for low
voltage thresholds, and compensates for self-discharge, aging, temperature, and discharge rate. Current is
measured across a small value series resistor between the negative terminal of the battery and the pack ground
(see RS in Figure 3). Available capacity is reported with a resolution of 3.57 µVh. Time-To-Empty reporting in
minutes at standby, peak, actual, and at-rate currents allows the requirements for host-based calculations to be
greatly reduced or eliminated; reading a single register pair provides useful and meaningful information to the
end user of the application.
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FUNCTIONAL DESCRIPTION (continued)
Figure 3 shows a typical application circuit. Differential sense of the voltage across the current sense resistor,
RS, improves device performance, leading to an improvement in reported time-to-empty accuracy. An internal, 3
µA pull-down on the HDQ or SDA and SCL lines ensures that the device detects a logic 0 on the communication
lines and allows the device to automatically enter the low-power sleep mode when the system power is switched
off or the pack is removed. A 100 kΩ pullup to VCC can be added to the communication lines if this feature needs
to be disabled. The bqJUNIOR can operate directly from a single Li-Ion or Li-Pol cell.
PACK+
PGM TP
R3
1 kΩ
1
C4
0.1 µF
ESD Protection
R5
100 Ω
R6
100 Ω
PGM 10
RBI
+
R4
10 kΩ
Li-Ion
or
Li-Pol
bq27200DRK
2
GPIO 9
VCC
SCL
R1
1 kΩ
SRP 8
C3
0.1 µF
D1
5.6 V
3
C1
0.1 µF
4
R7
100 Ω
VSS
SCL
SRN 7
R2
1 kΩ
R8
100 Ω
SDA
5
D2
5.6 V
ESD Protection
RS
0.02 Ω
SDA
BAT 6
C3
0.1 µF
C2
0.1 µF
11
Li-Ion Protector
PACK−
UDG−03041
Figure 3. Typical Application Circuit (bq27200)
Measurements
As shown in the functional block diagram, the bqJUNIOR uses a dedicated fully differential Delta-Sigma Coulomb
Counter (DSCC) for charge and discharge current and coulometric measurements and an analog-to-digital
converter (ADC) for battery voltage and temperature measurements. Both DSCC and ADC are automatically
compensated for offset. No user calibration or compensation is required. An EEPROM offset value can be
programmed to compensate for contributions to the DSCC offset due to the PCB layout.
Charge and Discharge Coulometric and Current Measurements
The bqJUNIOR uses a DSCC to perform a continuous integration of the voltage waveform across a small value
sense resistor in the negative lead of the battery, as shown in Figure 3. The integration of the voltage across the
sense resistor is the charge added or removed from the battery. Because the DSCC does a direct integration of
the waveform, the shape of the current waveform through the sense resistor does not have any effect on the
coulometric measurement accuracy. The low-pass filter that feeds the sense resistor voltage to the bqJUNIOR
SRP and SRN inputs filters out system noise and does not affect the coulometric measurement accuracy,
because the low-pass filter does not change the integrated value of the waveform. The bqJUNIOR also uses the
DSCC to measure current. The reported current is determined by the average voltage across the sense resistor
over a 5.12 second interval.
8
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FUNCTIONAL DESCRIPTION (continued)
Offset Calibration
The offset voltage of the DSCC measurement must be very low to be able to measure small signal levels
accurately. The bqJUNIOR provides an auto-calibration feature to cancel the internal voltage offset error across
SRP and SRN for maximum charge measurement accuracy. NO CALIBRATION IS REQUIRED. External
voltage offset error caused by the PCB layout cannot be automatically calibrated out by the gauge, but the
external offset can be determined using a built-in user offset measurement command and can be programmed
into the EEPROM for inclusion in the offset compensation performed by the gauge. See the Layout
Considerations section for details on minimizing PCB induced offset across the SRP and SRN pins.
The bqJUNIOR auto-calibration of the DSCC offset is performed from time-to-time as operating conditions
change, to keep the measurement error small. A Calibration-In-Progress (CALIP) flag is set in FLAGS to indicate
when the operation occurs. Capacity, voltage, and temperature is updated during the 5.12 second offset
calibration time, but other parameters are not updated until the calibration has completed. When there is a full
reset, the gauge makes an initial quick offset calibration and delays the 5.12 second full offset calibration for at
least 40 seconds. This is done to prevent the full 5.12 second calibration operation from interfering with module
test functions that need to be performed immediately after power application during manufacturing test. The
quick offset calibration after a full reset is a 1.28 second offset measurment used as a delay, followed by a 1.28
second offset measurement that is used as the initial offset value. The 1.28 second delay allows VCC to settle
before the initial offset measurement. If manufacturing test does not need the additional VCC settling time or can
use a slightly worse initial offset measurement, the tester may write bit 0 of CTRL (address 0x00) to 1 during the
first 1.28 seconds after the reset and the first offset sample will be used, cutting the initial quick offset calibration
time in half.
Digital Magnitude Filter
The Digital Magnitude Filter (DMF) threshold can be set in EEPROM to indicate a threshold below which any
charge or discharge accumulation is ignored. This allows setting a threshold above the maximum DSCC offset
expected from the IC and PCB combination, so that when no charge or discharge current is present, the
measured capacity change by the bqJUNIOR is zero. Note that even a small offset can add up to a large error
over a long period. In addition to setting the threshold above the largest offset expected, the DMF should be set
below the minimum signal level to be measured. The sense resistor value should be large enough to allow the
minimum current level to provide a signal level substantially higher than the maximum offset voltage. Conversely,
the sense resistor must be small enough to meet the system requirement for insertion loss as well as keep the
maximum voltage across the sense resistor below the 100 mV maximum that the DSCC can accurately measure.
The DMF threshold is programmed in EEPROM in increments of 4.9 µV. Programming a zero in the DMF value
will disable the DMF function and all non-zero DSCC measurements are counted.
Voltage
The bqJUNIOR monitors the battery voltage through the BAT pin and reports an offset corrected value through
the internal registers. The bqJUNIOR also monitors the voltage for the end-of-discharge (EDV) thresholds. The
EDV threshold levels are used to determine when the battery has been discharged to 6.25% or empty and
synchronizes the reported capacity to these levels when the programmed EDV thresholds are detected.
Temperature
The bqJUNIOR uses an integrated temperature sensor to monitor the pack temperature and is reported through
the internal registers. The temperature measurement is used to adjust compensated available capacity and
self-discharge capacity loss.
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FUNCTIONAL DESCRIPTION (continued)
RBI Input
The RBI input pin is used with an external capacitor to provide backup potential to the internal registers when
VCC drops below V(POR). VCC is output on RBI when VCC is above V(POR), charging the capacitor. An optional 1
MΩ resistor can be added from the RBI pin to VCC. This allows the IC to maintain RAM register data for an
indefinite period when the battery voltage is below V(POR) and above 1.3 V. The bqJUNIOR checks for RAM
corruption by storing a redundant copy of the high byte of NAC and a checkbyte computed from LMD, CYCL,
CYCT, and other critical data. After a reset, the bqJUNIOR compares the redundant NAC and checkbyte values.
If the checks are correct, NAC, LMD, CYCL, and CYCT are retained; and the CI bit in FLAGS is left unchanged.
If these checks are not correct, NAC, CYCL, and CYCT are cleared; LMD is initialized from EEPROM and the CI
bit in FLAGS is set to 1. All other RAM is initialized on all resets.
GPIO
The GPIO pin can be used as an input or an output. The initial state can be established by programming bit 7 in
the PKCFG EEPROM location. The input/output state can be changed at any time by changing the value in bit 7
of MODE.
Layout Considerations
The auto-calibrating DSCC approach effectively cancels the internal offset voltage within the bqJUNIOR, but any
external offset caused by PCB layout must be programmed in the EEPROM to be cancelled. The magnitude and
variability of the external offset makes it critical to pay special attention to the PCB layout. To obtain optimal
performance, the decoupling capacitor from VCC to VSS and the filter capacitors from SRP and SRN to VSS
should be placed as closely as possible to the bqJUNIOR, with short trace runs to both signal and VSS pins. All
low-current VSS connections should be kept separate from the high-current discharge path from the battery and
should tie into the high-current trace at a point directly next to the sense resistor. This should be a trace
connection to the edge or inside of the sense resistor connection, so that no part of the VSS interconnections
carry any load current and no portion of the high-current PCB trace is included in the effective sense resistor (i.e.
Kelvin connection).
Gas Gauge Operation
Figure 4 illustrates an operational overview of the gas gauge function.
The bqJUNIOR measures the capacity of the battery during actual use conditions and updates the Last
Measured Discharge (LMD) register with the latest measured value. The bqJUNIOR retains the learned LMD
value unless a full reset occurs. By measuring the capacity that the battery delivers as it is discharged from full to
the EDV1 threshold without any disqualifying events, the bqJUNIOR learns the capacity of the battery. The
bqJUNIOR does not need to learn a new capacity on each full discharge, and only a discharge during normal
use conditions should be used to learn a new capacity. In the event that some abnormal situation occurs that
could cause a significant reduction in learned capacity, the LMD value is restricted to a maximum LMD
learn-down during any single learning discharge of LMD/8. The Capacity Inaccurate (CI) bit in FLAGS is cleared
after a learning cycle. This bit remains cleared unless a full reset occurs or the cycle count since the last learning
cycle (CYCL) reaches a count of 32.
The full condition is defined as Nominal Available Capacity (NAC) = LMD. The Valid Discharge Flag (VDQ) in the
FLAGS register is set when this condition occurs and remains set until the learning discharge cycle completes or
an event occurs that disqualifies the learning cycle.
The learning discharge cycle completes when the battery is discharged to the condition where VOLT ≤ EDV1
threshold. The EDV1 threshold should be set at a voltage that ensures at least 6.25% of battery capacity below
that threshold. The EDVF threshold should be set at a voltage that the system sees as the zero-capacity battery
voltage. The bqJUNIOR EDV detection is designed to prevent premature detection of the EDV thresholds due to
dynamic load variations. EDV detection has a dynamically adjusted delay of up to 21.5 s with RSOC ≥ 6% and
down to 3 s when RSOC = 0%.
The bqJUNIOR does not learn the capacity between EDV1 and EDVF thresholds, but assumes that the capacity
is 6.25% of LMD; so, care should be taken to set EDV1 based on the characteristics of the battery. The
measured LMD value is determined by measuring the capacity delivered from the battery from NAC = LMD until
VOLT = EDV1, plus LMD/16 to account for the 6.25% capacity remaining below the EDV1 threshold.
10
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FUNCTIONAL DESCRIPTION (continued)
A learning cycle can be disqualified by any of the following conditions:
1. Cold temperature: Temperature ≤ TCOMP[3:0] (°C) when the EDV1 threshold voltage is reached.
2. Light load: A capacity learning cycle is disqualified if average current is less than or equal to 2 times the
initial standby load when the EDV1 threshold voltage is reached.
3. Fast voltage drop: VOLT ≤ (EDV1 – 256 mV) before EDV1 is set.
4. Excessive charging: Cumulative Charge > 255 NAC counts (910 µVh) during a learning discharge cycle
(alternating discharge/charge/discharge before EDV1 is set).
5. Reset: VDQ is cleared on all resets.
6. Excessive self-discharge: NAC reduction from self-discharge estimate (0.195%) performed 64 times.
7. Self-discharge at termination of learning cycle. If self-discharge estimate causes NAC ≤ LMD/16, VDQ is
cleared.
NAC is adjusted by charge and discharge coulometric measurements except when battery full or empty
conditions are detected. NAC = LMD is forced when IMIN = 1 (full detection) unless Temperature ≤ TCOMP[3:0]
(°C). During a discharge with VDQ = 1, NAC is not allowed to drop below LMD/16 until EDV1 = 1. If EDV1 = 1
occurs when NAC > LMD/16, NAC = LMD/16 will be forced. NAC = 0 is forced if EDVF = 1.
INPUTS
Charge
Current
Discharge
Current
Self−Discharge
Timer
Temperature
Compensation
+
COMPUTATIONS
_
_
_
Nominal Available
Charge (NAC)
Last Measured
Discharge (LMD)
Qualified
Transfer
Rate and
Temperature
Compensation
+
+
Learning Count
Register (LCR)
Temperature, Voltage,
Average Current,
Other Data
OUTPUTS
Compensated
Available Charge
I2C or HDQ Interface
UDG−03042
Figure 4. Operational Overview
Register Interface
The bqJUNIOR stores all calculated information in RAM, which is backed up by the voltage on the RBI input.
EEPROM registers store permanent user data. The memory map for bq27000/bq27200 is shown in Table 1.
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FUNCTIONAL DESCRIPTION (continued)
Table 1. bq27000/bq27200 Memory Map
ADDRESS
NAME
FUNCTION
UNITS
0x7F
TCOMP
Temperature Compensation Constants, OR, ID#1
0x7E
DCOMP
Discharge Rate Compensation Constants, OR, ID#2
ACCESS
EEPROM Registers
0x7D
IMLC
0x7C
PKCFG
Pack Configuration Values
0x7B
TAPER
Aging Estimate Enable, Charge Termination Taper Current
0x7A
DMFSD
Digital Magnitude Filter and Self-Discharge Rate Constants
0x79
ISLC
0x78
SEDV1
Scaled EDV1 Threshold
0x77
SEDVF
Scaled EDVF Threshold
0x76
ILMD
0x6F - 0x75
-
0x6E
EE_EN
0x2D - 0x6D
-
Initial Max Load Current, OR, ID#3
Initial Standby Load Current
Initial Last Measured Discharge High Byte
R/W
R/W
457
µV (1)
R/W
R/W
228 µV (1)
R/W
R/W
7.14 µV (1)
R/W
R/W
R/W
914
µVh (1)
RESERVED
R/W
R
EEPROM Program Enable
R/W
RESERVED
R
RAM Registers
(1)
(2)
12
0x2C
CSOC
Compensated State-of-Charge
%
R
0x2B - 0x2A
CYCT
0x29 - 0x28
CYCL
Cycle Count Total High - Low Byte
Cycles
R
Cycle Count Since Learning Cycle High - Low Byte
Cycles
0x27 - 0x26
TTECP
Time-to-Empty At Constant Power High - Low Byte
R
Minutes
0x25 - 0x24
AP
R
29.2 µV2 (2)
R
µV2h (2)
R
Average Power High - Low Byte
0x23 - 0x22
SAE
0x21 - 0x20
MLTTE
0x1F - 0x1E
MLI
0x1D - 0x1C
STTE
0x1B - 0x1A
SI
0x19 - 0x18
TTF
Time-to-Full High - Low Byte
0x17 - 0x16
TTE
Time-to-Empty High - Low Byte
0x15 - 0x14
AI
0x13 - 0x12
LMD
0x11 - 0x10
CACT
0x0F - 0x0E
CACD
0x0D - 0x0C
NAC
0x0B
RSOC
Available Energy High - Low Byte
Max Load Time-to-Empty High - Low Byte
Max Load Current High - Low Byte
Standby Time-to-Empty High - Low Byte
Standby Current High - Low Byte
29.2
Minutes
R
3.57 µV (1)
R
Minutes
R
3.57 µV (1)
R
Minutes
R
Minutes
R
Average Current High - Low Byte
3.57 µV (1)
R
Last Measured Discharge High - Low Byte
3.57 µVh (1)
R
Temperature Compensated CACD High - Low Byte
3.57 µVh (1)
R
Discharge Compensated NAC High - Low Byte
3.57
µVh (1)
R
Nominal Available Capacity High - Low Byte
3.57 µVh (1)
R
%
R
Relative State-of-Charge
0x0A
FLAGS
0x09 - 0x08
VOLT
Reported Voltage High - Low Byte
Status Flags
R
0x07 - 0x06
TEMP
Reported Temperature High - Low Byte
0x05 - 0x04
ARTTE
0x03 - 0x02
AR
0x01
MODE
Device Mode Register
R/W
0x00
CTRL
Device Control Register
R/W
At-Rate Time-to-Empty High - Low Byte
At-Rate High - Low Byte
Divide by Rs in milliohms to convert µV to mA or µVh to mAh.
Divide by Rs in milliohms to convert µV2 to mW or µV2h to mWh.
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R
0.25 °K
R
Minutes
R
3.57 µV (1)
R/W
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APPLICATION INFORMATION
Control and MODE Registers (CTRL/MODE) — Address 0x00/0x01
The device control register is used by the host system to request special operations by the bqJUNIOR. The
highest priority command set in the MODE register is performed when the host writes data 0xA9 or 0x56 as
indicated to the control register. The CTRL register is cleared when the command is accepted. The host must set
the appropriate command bit in MODE before sending the command key to CTRL.
Mode Register (MODE) — Address 0x01
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COMMAND KEY = 0xA9
GPIEN
GPSTAT
WRTNAC
DONE
PRST
POR
FRST
SHIP (1)
COMMAND KEY = 0x56
GPIEN
GPSTAT
CEO
CIO
N/A
POR
N/A
N/A
(1)
bq27000 only
GPIEN
GPIEN sets the state of the GPIO pin. A 1 configures the GPIO pin as input, while a 0 configures
the GPIO pin as an open-drain output. This bit is initialized to the value of bit 7 of the PKCFG
register in the EEPROM. The user should keep this bit set or cleared as desired when other bits in
this register are written.
GPSTAT
GPSTAT sets the state of the open drain output of the GPIO pin (GPIEN = 0). A 1 turns off the
open drain output, while a 0 turns the output on. This bit is set to 1 on POR. When the GPIO pin is
an input (GPIEN=1), this bit returns the logic state of the GPIO pin. The user should keep this bit
set or cleared as desired when other bits in this register are written.
WRTNAC
WRTNAC is used to transfer data from the AR registers to NAC. Other registers are updated as
appropriate. This command is useful during the pack manufacture and test to initialize the gauge to
match the estimated battery capacity.
DONE
DONE is used to write NAC equal to LMD. Useful if the host uses a charge termination method that
does not allow the monitor to detect the taper current. The host system could use this command
when the charging is complete to force update of internal registers to a full battery condition.
PRST
Partial reset. This command requests a reset of all RAM registers except NAC, LMD, and the CI bit
in FLAGS. This command is intended for manufacturing use.
POR
The POR status bit is set to 1 by the bqJUNIOR following a Power on Reset. This is a flag to the
host that VCC was less than V(POR) and caused a reset. The bit is cleared to 0 by the bqJUNIOR
when a full charge condition is reached or it may be cleared by the host. The bit is also cleared to 0
after exiting from EEPROM programming or ship. The host may set this bit, but it has no effect on
the bqJUNIOR operation. The user should keep this bit set or cleared as desired when other bits in
this register are set.
FRST
Full reset. This command bit requests a full reset. A full reset reinitializes all RAM registers,
including the NAC, LMD, and FLAGS registers. This command is intended for manufacturing use.
SHIP
This command bit requests that the device (bq27000 only) should be put in ship mode. See the
Power Mode section for a description of the ship mode. This command is intended for
manufacturing use.
CEO
This command bit requests that the external offset value is measured. Care should be taken to
insure that no charge or discharge current flows during the time this measurement is made. The
external offset value is the total offset of the DSCC plus any external PCB affects. The result can
be read in 0x5f-5e. The result is a signed number with an LSB value of 1.225 µV. The command
takes approximately 5.5 seconds to make the measurement. This command is intended for
manufacturing use.
CIO
This command bit requests that the internal offset value is measured. The internal offset value is
the offset of the DSCC with an internal short applied from SRP to SRN. The result can be read in
0x5f-5e. The result is a signed number with an LSB value of 1.225 µV. The command takes
approximately 5.5 seconds to make the measurement. This command is intended for manufacturing
use.
WRTNAC, DONE, PRST, FRST, and SHIP (bq27000 only) commands are prioritized in bit order. This means
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that WRTNAC (bit 5) has higher priority than DONE (bit 4); PRST (bit 3) has higher priority than FRST (bit 1),
and so on. Only the highest priority mode set is enabled each time the CTRL register is written with data 0xA9,
and the firmware clears all other mode bits and the CTRL register when that action is complete. The host system
must make two writes for every mode to be enabled: one write to the MODE register to set the appropriate bit
and a second write to the CTRL register to signal that the command in the mode register should be executed.
The CIO value may be subtracted from the CEO value to determine the external board offset. This value can be
programmed into the PKCFG[4-2] in the EEPROM for automatic compensation of this external offset value.
At-Rate Registers (ARL/ARH) — Address 0x02/0x03
The host can write the current in units of 3.57 µV per bit to this register for predictive calculation time-to-empty.
The part uses this value to predict the time-to-empty at any desired current; it does not affect the time-to-empty
calculation based on the actual current. The value in AR is always assumed to be a discharge current.
This register is also used during pack manufacturing to input a nominal available charge value to set NAC to the
approximate initial pack capacity value.
At Rate Time-to-Empty Registers (ARTTEL/ARTTEH) — Address 0x04/0x05
This is predicted time-to-empty in minutes at user-entered discharge rate. The discharge current used in the
calculation is entered by the host system in the AR registers. The at-rate capacity (ARCAP) value used can be
larger or smaller than CACT. It is computed using the same formulas as CACT, except the discharge
compensation is computed using AR, instead of AI, for the discharge rate. The equation used to compute at-rate
time-to-empty is:
ARTTE = 60 * ARCAP / AR
The host system has read-only access to this register pair.
Reported Temperature Registers (TEMPL/TEMPH) — Address 0x06/0x07
The TEMPH and the TEMPL registers contain the reported die temperature. The temperature is expressed in
units of 0.25 °K and is updated every 2.56 seconds. The equation to calculate reported pack temperature is:
Temperature = 0.25 * (256 * TEMPH + TEMPL)
The host system has read-only access to this register pair.
Reported Battery Voltage registers (VOLTL/VOLTH) — Address 0x08/0x09
The VOLTH and the VOLTL low-byte registers contain the reported battery voltage measured on the BAT pin.
Voltage is expressed in mV with an LSB resolution of 1 mV. Reported voltage cannot exceed 5000 mV. The host
system has read-only access to this register pair. Voltage is updated every 2.56 seconds.
Status Flag Register (FLAGS) — Address 0x0A
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME
CHGS
NOACT
IMIN
CI
CALIP
VDQ
EDV1
EDVF
POR STATUS
0
0
0
1
0
0
0
0
CHGS
Charge State flag. A 1 in the CHGS indicates a charge current (VSRP > VSRN). A 0 indicates a lack
of charge activity. This bit should be read when the host system reads the Average Current register
pair to determine the sign of the average current magnitude. This bit is cleared to 0 on all resets.
NOACT
No Activity flag. A 1 indicates that the voltage across RS is less than the digital magnitude filter. See
the Digital Magnitude Filter section for more information. This bit is cleared to 0 on all resets.
IMIN
Li-ion taper current detection flag. A 1 indicates that the charge current has tapered to less than the
value set in EEPROM and that the battery voltage is greater than or equal to the value selected by
the QV0 and QV1 bits in the PKCFG register (see EEPROM Data Register description for more
details). Taper current detection is disqualified if AI < 8 (28.6 µV across sense resistor). The taper
detection conditions must be maintained for 4 successive average current measurements (20-25 s)
to qualify as a valid taper current detection. This bit is cleared to 0 on all resets.
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CI
Capacity Inaccurate flag. A 1 indicates that the firmware has not been through a valid learning cycle
and is basing all calculations on initial design values programmed into EEPROM or that there have
been at least 32 cycle-count increments since the last learning cycle. This bit is cleared only on a
LMD update following a learning cycle. This bit is set to 1 on a full reset. The previous value is
retained if no RAM corruption is detected after a reset.
CALIP
Calibration-In-Progress flag. This flag is set whenever an automatic or commanded offset
calibration measurement is being made. This bit is set to 0 on all resets.
VDQ
Valid Discharge flag. A 1 indicates that the bqJUNIOR has met all necessary requirements for the
firmware to learn the battery capacity. This bit clears to 0 on a LMD update or condition that
disqualifies a learning cycle. This bit is cleared to 0 on all resets.
EDV1
First End-of-Discharge-Voltage flag. A 1 indicates that voltage on the BAT pin is less than or equal
to the EDV1 voltage programmed in EEPROM and the battery has less than or equal to 6.25% of
LMD capacity remaining. LMD updates immediately if the VDQ bit is set when this bit transitions
from 0 to 1. This bit is cleared to 0 on all resets.
EDVF
Final End-of-Discharge-Voltage flag. A 1 indicates that the battery has discharged to the empty
capacity threshold. This bit is cleared to 0 on all resets.
The host system has read-only access to this register.
Relative State-of-Charge (RSOC) — Address 0x0B
RSOC reports the nominal available capacity as a percentage of the last measured discharge value (LMD). The
equation is:
RSOC (%) = 100 * NAC/LMD
The host system has read-only access to this register.
Nominal Available Capacity Registers (NACL/NACH) — Address 0x0C/0x0D
This register pair increments during charge (VSRP > VSRN) if Voltage > EDVF threshold and decrements during
discharge (VSRP < VSRN). The NAC registers are cleared by a reset if RAM corruption is detected. The register
value is retained after a reset if RAM corruption is not detected. The host system has read-only access to this
register pair. NAC is reported in units of 3.57 µVh per count.
Discharge Rate Compensated Available Capacity Registers (CACDL/CACDH) — Address
0x0E/0x0F
This register pair reports available capacity in the battery, compensated for discharge rate. This register pair
follows NAC during charge and is reduced from NAC during discharge by an amount computed from AI and the
discharge rate compensation value programmed into EEPROM. CACD is not allowed to increase while
discharging, so that if the discharge rate decreases, the available capacity does not increase. CACD equals NAC
if the CHGS bit is 1. If CHGS is 0, CACD is the smaller of the previous and new computed values. The host
system has read-only access to this register pair. CACD is reported in units of 3.57 µVh per count.
Temperature Compensated CACD Registers (CACTL/CACTH) — Address 0x10/0x11
This register pair reports available capacity in the battery, compensated for both discharge rate and temperature.
This register pair follows CACD during both charge and discharge unless the temperature has fallen below the
threshold programmed into EEPROM. Once the temperature falls below the programmed threshold, the CACT
value is reduced from CACD by an amount computed from ILMD and the temperature compensation constants
programmed into EEPROM. This is the base capacity value used to calculate time-to-empty and compensated
state-of-charge. The host system has read-only access to this register pair. CACT is reported in units of 3.57 µVh
per count.
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Last Measured Discharge Registers (LMDL/LMDH) — Address 0x12/0x13
Last measured discharge is the measured discharge capacity of the battery from full to empty. LMD is updated
on a valid learning cycle, which occurs when the battery reaches the EDV1 level while the VDQ bit is set. It is
used with NAC to calculate Relative State-Of-Charge (RSOC). The host system has read-only access to this
register pair. LMD is reported in units of 3.57 µVh per count.
Average Current Registers (AIL/AIH) — Address 0x14/0x15
This register pair reports the magnitude of the average current through the sense resistor. The value is reported
with a resolution of 3.57 µV per count. Use the following equation to convert the value to mA, where R S is the
sense resistor value in milliohms:
Average Current = (256*AIH + AIL) * 3.57/ RS
The current reported is an average over the last 5.12 seconds. The host system has read-only access to this
register pair.
Time-to-Empty Registers (TTEL/TTEH) — Address 0x16/0x17
This register pair reports calculated time-to-empty at the measured discharge rate. This value is based on the
temperature and discharge rate compensated available charge and the average current. The equation to
calculate TTE is:
TTE = 60 * CACT/AI
TTE is reported in minutes. The host system has read-only access to this register pair.
Time-to-Full Registers (TTFL/TTFH) — Address 0x18/0x19
This register pair reports calculated time-to-full at the measured charge rate. The time computed at the average
current charge rate is extended by 50% to estimate the effect of the current taper. TTF is reported in minutes.
The equation for TTF is:
TTF = 60 * 1.50 * (LMD-NAC)/AI
The host system has read-only access to this register pair.
Standby Current Registers (SIL/SIH) — Address 0x1A/0x1B
This register pair reports measured standby current through the sense resistor. The standby current is an
adaptive measurement. Initially, the register pair reports the standby current programmed in EEPROM and after
spending some time in standby, the register pair reports the measured standby current. The register value is
updated every 5.12 seconds when the measured current is above the DMF threshold and is less than or equal to
2x the initial programmed standby current value. Each new SI value is computed as follows:
SINEW = (15/16)*SIOLD + (1/16)*AI
This filter function allows the reported standby current to shift towards the actual measured current with a time
constant of approximately 67 seconds. The value is reported with a resolution of 3.57 µV per bit. Use the
following equation to convert the value to mA, where RS is the sense resistor value in milliohms:
Standby Load Current = (256*SIH + SIL) * (3.57/ RS)
The host system has read-only access to this register pair.
Standby Time-to-Empty Registers (STTEL/STTEH) — Address 0x1C/0x1D
This register pair reports calculated time-to-empty at the measured standby current value. This value is based on
the nominal available charge and the standby current. STTE is reported in minutes. STTE is calculated by:
STTE = 60 * NAC/SI
The host system has read-only access to this register pair.
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Max Load Current Registers (MLIL/MLIH) — Address 0x1E/0x1F
This register pair reports the measured maximum load current through sense resistor. The max load current is an
adaptive measurement of the maximum load conditions. If the measured current is ever greater than the initial
Max Load Current programmed in EEPROM, the register pair updates to the new current. MLI is reduced to the
average of the previous value and the initial value in EEPROM whenever the battery is charged to full after a
previous discharge to an RSOC less than 50%. This keeps it from being stuck at an unusually high value. The
value is reported in units of 3.57 µV per count. Use the following equation to convert the value to mA, where R S
is the sense resistor value in milliohms:
Max Load Current = (256*MLIH + MLIL) * (3.57/ RS)
The host system has read-only access to this register pair.
Max Load Time to Empty Registers (MLTTEL/MLTTEH) — Address 0x20/0x21
This register pair reports calculated time-to-empty in minutes at the maximum measured discharge rate. The Max
Load Capacity (MLCAP) value is based on the temperature and discharge rate compensated available capacity
computed using MLI, instead of AI, for the discharge rate. MLTTE is calculated by:
MLTTE = 60 * MLCAP/MLI
The host system has read-only access to this register pair.
Available Energy Registers (SAEL/SAEH) — Address 0x22/0x23
SAE is the calculated energy available from the battery. The available energy is computed by multiplying the
compensated available capacity with the average of reported voltage and EDVF threshold voltage while
discharging. SAE is not allowed to increase while discharging, so that if the discharge rate decreases, the
available energy does not increase. This is accomplished by reporting the smaller of the previous and new
computed values. During charging, the available energy uses a computed value for average voltage to avoid an
inflated energy report due to the increased voltage. The value is reported in units of 29.2 µV2h per count. Use the
following equation to convert the value to mWh, where RS is the sense resistor value in milliohms.
SAE(mWh) = (256*SAEH + SAEL) * 29.2 / Rs(mΩ)
While charging SAE is calculated as:
SAE = 8 * CACT * (3088 +512*NAC/LMD)/65536,
and while discharging SAE is calculated as:
SAE = 4 * CACT * (Reported Voltage + EDVF)/65536
The host system has read-only access to this register pair.
Average Power Registers (APL/APH) — Address 0x24/0x25
Average power is the calculated power delivered during a discharge. It is the product of average current and
reported voltage, reported in units of 29.2 µV2 per bit. Use the following formula to convert the value to mW,
where RS is the sense resistor value in milliohms.
AP(mW) = (256 * APH + APL) * 29.2 / Rs(mΩ)
AP = 8 * AI * Reported Voltage/65536, while discharging
AP = 0, while charging
The host system has read-only access to this register pair.
Time-to-Empty at Constant Power Registers (TTECPL/TTECPH) — Address 0x26/0x27
TTECP is the time-to-empty in minutes with a constant power load. Because SAE is already scaled for the
average discharge voltage, the result is simply the ratio of SAE to AP:
TTECP = 60 * SAE/AP
The host system has read-only access to this register pair.
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Cycle Count Since Learning Cycle Registers (CYCLL/CYCLH) — Address 0x28/0x29
CYCL is the cycle count since the last learning cycle. Each count indicates an increment of CYCT since there
was a learning cycle. This register is cleared every time there is a learning cycle. When this count reaches 32, it
forces the CI flag in FLAGS to a 1. The host system has read-only access to this register pair.
Cycle Count Total Registers (CYCTL/CYCTH) — Address 0x2A/0x2B
CYCT is the cycle count since a full reset. A full reset clears this register. Each count indicates a cumulative
discharge equal to the Design Capacity (256 * ILMD). The host system has read-only access to this register pair.
Compensated State-of-Charge (CSOC) — Address 0x2C
CSOC reports the compensated available capacity as a percentage of the last measured discharge value (LMD).
The equation is:
CSOC (%) = 100 * CACT/LMD
The host system has read-only access to this register.
Reserved Registers
Addresses 0x2D — 0x6D and Address 0x6F — 0x75 are reserved and cannot be written by host.
EEPROM Enable Register (EE_EN) — Address 0x6E
This register is used to enable host writes to EEPROM data locations (addresses 0x76 — 0x7F). The host must
write data 0xDD to this register to enable EEPROM programming. See the Programming the EEPROM section
for further information on programming the EEPROM bytes. Care should be taken to insure that no value except
0xDD is written to this location.
EEPROM Data Registers (EE_DATA) — Address 0x76 — 0x7F
The EEPROM data registers contain information vital to the performance of the device. These registers are to be
programmed during pack manufacturing to allow flexibility in the design values of the battery to be monitored.
The EEPROM data registers are listed in Table 2. Detailed descriptions of what should be programmed follow.
See the Programming the EEPROM section for detailed information on writing the values to EEPROM.
Table 2. bq27000/bq27200 EEPROM Memory Map
Address
Name
Function
0x7F
TCOMP
Temperature compensation constants, OR, ID#1
0x7E
DCOMP
Discharge rate compensation constants, OR, ID#2
0x7D
IMLC
0x7C
PKCFG
Initial max load current, OR, ID#3
Pack configuration values
0x7B
TAPER
Aging estimate enable [7], charge termination taper current [6:0]
0x7A
DMFSD
Digital magnitude filter and self-discharge rate constants
0x79
ISLC
0x78
SEDV1
0x77
SEDVF
0x76
ILMD
Initial standby load current
Scaled EDV1 threshold
Scaled EDVF threshold
Initial last measured discharge high byte
Initial Last Measured Discharge High Byte (ILMD) — Address 0x76
This register contains the scaled design capacity of the battery to be monitored. The equation to calculate the
initial LMD is:
ILMD = Design Capacity(mAh) * RS(mΩ) / (256*3.57)
where RS is the value of the sense resistor used in the system. This value is used to initialize the high byte of
LMD. The initial low byte value of LMD is 0.
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Scaled EDVF Threshold (SEDVF) — Address 0x77
This register contains the scaled value of the threshold for zero battery capacity. To calculate the value to
program, use the following equation:
SEDVF = Design EDVF(mV)/8 – 256
Scaled EDV1 Threshold (SEDV1) — Address 0x78
This register contains the scaled value of the voltage when the battery has 6.25% remaining capacity. When the
battery reaches this threshold during a valid discharge, the device learns the full battery capacity, including the
remaining 6.25%. See the bqJUNIOR Capacity Learning section for more information on the learning cycles of
the device. To calculate the value to program, use the following equation:
SEDV1 = Design EDV1(mV)/8 – 256
Initial Standby Load Current (ISLC) — Address 0x79
This register contains the scaled, end-equipment-design standby current. On a reset or POR, this value is
transferred to the SI register and is used to calculate Standby Time-to-Empty. The gauge learns a new standby
load if the discharge activity is above the DMF threshold and less than or equal to 2 times the initial standby
load.
A capacity learning cycle is disqualified if average current is less than or equal to 2 times the initial standby load
when the EDV1 threshold voltage is reached. The equation for programming this value is:
ISLC = Design Standby Current (mA) * RS(mΩ) / 7.14
where RS is the value of the sense resistor used in the system.
Digital Magnitude Filter and Self-Discharge Values (DMFSD) — Address 0x7A
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DMF[3]
DMF[2]
DMF[1]
DMF[0]
SD[3]
SD[2]
SD[1]
SD[0]
DMF[3:0]
Sets the digital magnitude filter threshold. See the bqJUNIOR Digital Magnitude Filter section for
more information on the function of the DMF. The value to be programmed is:
DMF[3:0] = Design Threshold/4.9
SD[3:0]
Sets the self-discharge rate %/day value at 25°C. The value to be programmed is:
SD[3:0] = 1.61/Design SD
NAC is reduced with an estimated self-discharge correction to adjust for the expected self-discharge of the
battery. This estimation is performed only when the battery is not being charged. The rate programmed in
EEPROM for DMFSD determines the self-discharge when 20°C ≤ TEMP < 30°C. The self-discharge estimation is
doubled for each 10°C decade hotter than the 20-30°C decade, up to a maximum of 16 times the programmed
rate for TEMP ≥ 60°C and is halved for each 10°C decade colder than the 20-30°C decade, down to a minimum
of 1/4th the programmed rate for TEMP < 0°C. The self-discharge estimation is performed by reducing NAC by
NAC/512 at a time interval that achieves the desired estimation. If DMFSD is programmed with 8 decimal, the
self-discharge rate is 0.195% per day in the 20-30°C decade. This is accomplished by reducing NAC by
NAC/512 (100/512 = 0.195%) a single time every 23.3 hours (0.195 * 24/23.3 = 0.2). If temperature rises by
10°C, the 0.195% NAC reduction is made every 11.65 hours for a 0.4% per day reduction. If TAPER[7] = 1,
capacity aging is enabled, and there is an LMD reduction of 0.1% (Design Capacity/1024) every time there are 8
NAC self-discharge estimate reductions without charging the battery to full.
Taper Current (TAPER) — Address 0x7B
This register contains the enable bit for the capacity aging estimate and the charge taper current value. The
taper current value, in addition to battery voltage, is used to determine when the battery has reached a full
charge state. The equation for programming the taper current is:
TAPER[6-0] = Design Taper Current (mA) * RS(mΩ)/228 µV
where RS is the value of the sense resistor used in the system.
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TAPER[7] should be set to 1 to enable the automatic aging of the LMD full capacity value. If this feature is
enabled, LMD is reduced by Design Capacity/1024 every time CYCL increments by 2 and every time that a
cumulative NAC self-discharge estimate reduction of 1.56% has been made without charging the battery to full. If
TAPER[7] is set to 0, there is no LMD reduction with cycle count or self-discharge.
Pack Configuration (PKCFG) — Address 0x7C
NAME
GPIEN
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIEN
QV1
QV0
BOFF(2)
BOFF(1)
BOFF(0)
DCFIX
TCFIX
Allows the pack manufacturer to set the state of the GPIO pin on initial power up. If the bit is 0, the
GPIEN bit is cleared on reset and the GPIO pin acts as a high-impedance output. If the bit is 1, the
GPIEN bit is set on reset and the GPIO pin acts as an input. The state of the GPIO pin can then be
read through the GPSTAT bit in the MODE register.
QV1 & QV0 These bits set the minimum qualification voltage for charge termination. The termination voltage
thresholds are set as listed in Table 3.
Table 3. Charge Termination Voltage Settings
BOFF
QV1
QV0
Voltage (mV)
0
0
3968
0
1
4016
1
0
4064
1
1
4112
These bits are used to store a typical board offset value for the gauge. This value is added to the
internal offset measurement and the total applied as an offset correction for the charge and
discharge coulometric measurements made by the DSCC. This is a 2s-complement signed number
with a value of 2.45 µV per bit.
Table 4. Board Offset Voltage Settings
Board Offset
BOFF(2)
BOFF(1)
BOFF(0)
7.35 µV
0
1
1
4.9 µV
0
1
0
2.45 µV
0
0
1
0
0
0
0
-2.45 µV
1
1
1
-4.9 µV
1
1
0
-7.35 µV
1
0
1
-9.8 µV
1
0
0
DCFIX
Fixed discharge compensation. Normal discharge rate compensation (DCOMP register) is used if
this bit is set to 0. If this bit is set to 1, the device assumes a fixed value of 0x42 for DCOMP, giving
a discharge rate compensation gain of 6.25% with a compensation threshold of C/4. Setting the bit
to 1 frees the EEPROM location of 0x7E for use as a programmable identification byte.
TCFIX
Fixed temperature compensation. Normal temperature compensation (TCOMP register) is used if
this bit is set to 0. If this bit is set to 1, the device assumes a fixed value of 0x7C for TCOMP, giving
a temperature compensation gain of 0.68% of Design Capacity/°C with an offset of 12°C. Setting
this bit to 1 frees the EEPROM location of 0x7F for use as a programmable identification byte.
Initial Max Load Current (IMLC) — Address 0x7D
This register contains the scaled, end-equipment-design maximum current. On a full reset or POR, this value is
transferred to the MLI register and used to calculate max load time-to-empty. The device learns a new maximum
load if the current exceeds the initial maximum load. The equation for programming this value is:
IMLC = Design Max Current (mA) * RS(mΩ)/457 µV
where RS is the value of the sense resistor used in the system.
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The user can optionally use this byte in the EEPROM as an identification byte. If so used, the user should ignore
the values in MLI and MLTTE registers.
Discharge Rate Compensation Constants (DCOMP) — Address 0x7E
This register is used to set the compensation coefficients for discharge rate. These coefficients are applied to the
nominal available charge to more accurately predict capacity at high discharge rates.
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DCGN[5]
DCGN[4]
DCGN[3]
DCGN[2]
DCGN[1]
DCGN[0]
DCOFF[1]
DCOFF[0]
DCGN[5:0] Discharge rate compensation gain. Used to set the slope of the discharge rate capacity
compensation. The gain factor adjustment is in increments of 0.39% of discharge current in excess
of the DCOFF value. The equation for programming the value is:
DCGN[5:0] = 2.56 * Design discharge compensation gain %
DCOFF[1:0] These bits set the discharge threshold of compensating the nominal available charge for discharge
rate. The threshold is set as listed in Table 5.
Table 5. Discharge Rate Compensation Thresholds
DCOFF[1]
DCOFF[0]
DCOFF Threshold
0
0
0
0
1
C/2 (ILMD*256÷2)
1
0
C/4 (ILMD*256÷4)
1
1
C/8 (ILMD*256÷8)
Discharge compensation, DCMP, is computed from these coefficients as follows:
DCMP = DCGN(AI-DCOFF)/256
where DCMP ≥ 0. The CACD register then takes on the value:
CACD = NAC – (DCMP – LMDCMP), if DCMP > LMDCMP or
CACD = NAC, if DCMP ≤ LMDCOMP
where LMDCMP is the value of DCMP when the last LMD value was learned. This allows the compensation for
CACD to adapt as the LMD value is learned.
If PKCFG[1] = 1, the device assumes a fixed value of 0x42 for DCOMP, giving a discharge rate compensation
gain of 6.25% with a compensation threshold of C/4. This frees the EEPROM location of 0x7E for use as a
programmable identification byte.
Temperature Compensation Constants (TCOMP) — Address 0x7F
This register is used to set the compensation coefficients for temperature. These coefficients are applied to the
discharge rate compensated available charge to more accurately predict capacity available at cold temperature.
BIT 7
BIT 6
BIT 5
TCGN[3]
TCGN[2]
TCGN[1]
BIT 4
BIT 3
TCGN[0] NAME TOFF[3]
BIT 2
BIT 1
BIT 0
TOFF[2]
TOFF[1]
TOFF[0]
TCGN[3:0]
Temperature compensation gain. Used to set the slope of the compensation as a percentage of
Design Capacity (DC) decrease per °C. The equation for programming the value is:
TCGN[3:0] = 10.24 * Design Temp Compensation Gain % DC/°C
TOFF[3:0]
Temperature compensation offset. Used to set the offset of the compensation. The temperature
threshold is also used as the cold temperature disqualification for a learning cycle. The equation for
programming the value is:
TOFF[3:0] = Design Temp Compensation Offset (°K) – 273
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Temperature compensation, TCMP, is computed from these coefficients as follows:
TCMP = TCGN * ILMD(273 + TOFF - T)/4
where T is the temperature in °K and TCMP ≥ 0. CACT is then computed as follows:
CACT = CACD – TCMP
If PKCFG[0] = 1, the device assumes a fixed value of 0x7C for TCOMP, giving a temperature compensation gain
of 0.68% DC/°C with an offset of 12°C. This frees the EEPROM location of 0x7F for use as a programmable
identification byte.
Power Modes
The bqJUNIOR has five power modes: Active, Sleep, Ship, Hibernate, and Data Retention (RBI). Figure 5 shows
the flow that moves the device between the Active, Sleep, and Ship modes. Hibernate and Data Retention are
special modes not included in the flow. Detailed explanations of each mode follow the diagram in Figure 5.
Active Mode
COM low for 18
seconds?
No
Yes
No
Ship
enabled?
No
Yes
Yes
Ship Mode
COM
pulled high?
Yes
VSR
below DMF
threshold?
Sleep Mode
No
COM
pulled high?
No
Yes
No
43.6 minute
wake?
Yes
Device enters active
mode for 18 seconds
UDG−04101
Figure 5. Power Mode Flow Chart
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Active Mode
During normal operation, the device is in active mode, which corresponds to the highest power consumption.
Normal gas gauging is performed in this mode. If system requirements mandate that bqJUNIOR should not enter
Sleep or Ship modes, then an external pullup resistor from VCC to keep HDQ or CLK and DTA at a logic 1 is
required on the bqJUNIOR side of the system. The resistor value chosen should be small enough to force a logic
1 even with the internal pulldown current and any external ESD protection circuitry loading.
Sleep Mode
This low power mode is entered when the HDQ or CLK and/or DTA line is pulled low for at least 18 seconds and
the charge or discharge activity is below the DMF threshold. Normal gas gauging ceases, but battery
self-discharge, based on the temperature when the device entered sleep mode, is maintained internally. The
device wakes every 43.6 minutes to update the temperature measurement and goes back to sleep after about 18
seconds if the HDQ or CLK and/or DTA line is still low and the charge or discharge activity is still below the DMF
threshold. The bqJUNIOR has an internal 3 °A pulldown current on each communication line, eliminating the
need to add external pulldown resistors to force a logic 0 on open communication lines.
When the device wakes, it stays in active mode long enough to confirm that the charge or discharge activity is
still below the digital magnitude filter threshold. This is meant to minimize possible error if the battery pack is
removed from the end equipment for a short period of time and then reinserted, and there is not a transient on
the communication lines to pull the device into the active mode. This is an issue only if the system has some
current drain from the battery even though the communication lines are low. The gauge reenters sleep mode
when the charge or discharge activity falls below the digital magnitude filter threshold.
When all communication lines are pulled high, the device leaves the sleep mode. If the DMF threshold is set to
zero and a communication line is pulled low, the device does not enter sleep mode until the average current
value is less than 3.57 µV/Rsr.
If the battery pack can be removed and placed on an external charger, the charger should have a pull-up resistor
on the HDQ or SCL and SDA lines to wake the part from sleep. A 100 kΩ pullup resistor from communication
line(s) to VCC can be added in the battery pack to disable the sleep function.
Ship Mode (bq27000 only)
This low power mode is to be used when the pack manufacturer has completed assembly and test of the pack.
The ship mode is enabled by setting the SHIP bit in the MODE register and issuing the control command (data
0xA9 to register 0x00). Ship mode is entered only when the ship mode is enabled and the HDQ or CLK and/or
DTA line has been pulled low for at least 18 seconds. This allows the pack manufacturer to enable the ship
mode and pull the pack from the test equipment without any additional overhead. Transients on a communication
line after the ship mode has been enabled but before the device has entered ship mode, do not cause the device
to stay in active mode. Transients on a communication line, after the device has entered ship mode can wake the
part from ship mode, but if there is no charge or discharge activity above the DMF threshold, the part
automatically enters the Sleep mode as previously described.
All device functionality stops in ship mode and it does not start again until the communication lines are pulled
high or the battery voltage drops below and then rises above the V(POR) threshold. A full reset is forced when the
part leaves ship mode. If the current NAC value must be retained after waking, ship mode should not be used.
Hibernate Mode
The device enters hibernate mode when VCC drops below V(POR). VCC must be raised above V(POR) in order to
exit the hibernate mode. If RBI voltage does not drop below 1.3 V, RAM content is maintained and allows
retention of NAC, LMD, CYCL, CYCT, and the CI flag after VCC is raised above V(POR).
Programming the EEPROM
The bqJUNIOR has 10 bytes of EEPROM that are used for firmware control and application data (see the
bqJUNIOR Register Descriptions section for more information). Programming the EEPROM should take place
during pack manufacturing because a 21 V pulse is needed on the PROG pin. The programming mode must be
enabled prior to writing any values to the EEPROM locations. The programming mode is enabled by writing to
the EE_EN register (address 0x6E) with data 0xDD. Once the programming mode is enabled, the desired data
can be written to the appropriate address. Figure 6 shows the method for programming all locations.
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Host enables E2PROM
programming mode. Write data
0xDD to address 0x6E
Host writes data in addresses
0x76 − 0x7F
Host reads data
address 0x76
21−V pulse applied to
PROG pin for 50 ms
Host increments
address and reads
Programmed
0x7F?
No
Yes
Write data 0x00 to
address 0x6E
UDG−04099
Figure 6. EEPROM Programming Flow
It is not required that addresses 0x76 — 0x7F be programmed at the same time or in any particular order. The
programming method illustrated in Figure 6 can be used to program any of the bytes as long as the sequence of
Enable, Write, Read, Apply Programming Pulse, and Disable is followed.
Communicating With the bq27000 (HDQ interface)
The bq27000 includes a single-wire HDQ serial data interface. Host processors, configured for either polled or
interrupt processing, can use the interface to access various bq27000 registers. The HDQ pin is an open-drain
device, which requires an external pullup resistor. The interface uses a command-based protocol, where the host
processor sends a command byte to the bq27000. The command directs the bq27000 either to store the next
eight bits of data received to a register specified by the command byte or to output the eight bits of data from a
register specified by the command byte.
The communication protocol is asynchronous return-to-one and is referenced to VSS. Command and data bytes
consist of a stream of eight bits that have a maximum transmission rate of 5 Kbits/s. The least-significant bit of a
command or data byte is transmitted first. Data input from the bqJUNIOR can be sampled using the pulse-width
capture timers available on some microcontrollers. A UART can also be configured to communicate with the
bq27000.
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If a communication timeout occurs (for example, if the host waits longer than T(RSPS) for the bq27000 to respond)
or if this is the first access command, then a BREAK should be sent by the host. The host may then resend the
command. The bq27000 detects a BREAK when the HDQ pin is driven to a logic-low state for a time T(B) or
greater. The HDQ pin then returns to its normal ready-high logic state for a time T(BR).The bq27000 is then ready
for a command from the host processor.
The return-to-one data-bit frame consists of three distinct sections:
1. The first section starts the transmission by either the host or the bq27000 taking the HDQ pin to a logic-low
state for a period equal to T(HW1) or T(DW1).
2. The next section is the actual data transmission, where the data should be valid for T(HW0)- T(HW1) or T(DW0)T(DW1).
3. The final section stops the transmission by returning the HDQ pin to a logic-high state and holding it high
until the time from bit start to bit end is equal to T(CYCH) or T(CYCD).
The HDQ line can remain high for an indefinite period of time between each bit of address or between each bit of
data on a write cycle. After the last bit of address is sent on a read cycle, the bq27000 starts outputting the data
after T(RSPS) with timing as specified. The serial communication timing specification and illustration sections give
the timings for data and break communication. Communication with the bq27000 always occurs with the
least-significant bit being transmitted first.
Plugging in the battery pack can be seen as the start of a communication due to contact bounce. It is
recommended that each communication or string of communications be preceded by a break to reset the HDQ
engine.
Command byte
The Command byte of the bqJUNIOR consists of eight contiguous valid command bits. The command byte
contains two fields: W/R Command and address. The Command byte values are shown as follows:
7
6
5
4
3
2
1
0
W/R
AD6
AD5
AD4
AD3
AD2
AD1
AD0
W/R
Indicates whether the command bytes is a read or write command. A 1 indicates a write command
and that the following eight bits should be written to the register specified by the address field of the
Command byte, whereas a 0 indicates that the command is a read. On a read command, the
bqJUNIOR outputs the requested register contents specified by the address field portion of the
Command byte.
AD6-AD0
The seven bits labeled AD6—AD0 containing the address portion of the register to be accessed.
Reading 16-bit Registers
Because 16-bit values are read only 8 bits at a time with the HDQ interface, it is possible that the device can
update the register value between the time the host reads the first and second bytes. To prevent any system
issues, any 16-bit values read by the host should be read with the following procedure.
1. Read high byte (H0).
2. Read low byte (L0).
3. Read high byte (H1).
4. If H1=H0, then valid result is H0, L0.
5. Otherwise, read low byte (L1) and valid result is H1, L1.
This procedure assumes that the 3 or 4 reads are made more quickly than the update rate of the value. The
maximum update rate of any value in the bq27000/bq27200 is 1.28 seconds.
The bq27200 circumvents this issue if a 16-bit value is read using the I2C incremental read procedure. Both low
and high bytes are captured simultaneously when the low byte is read.
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Communicating with the bq27200 (I2C interface)
The bq27200 supports the standard I2C read, incremental read, quick read, and one byte write functions. The
7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively. (S = Start, Sr = Repeated Start, A =
Acknowledge, N = No Acknowledge, and P = Stop)
Host generated
S
ADDR[6:0]
0
A
CMD[7:0]
A
DATA[7:0]
A
P
S
ADDR[6:0]
1
(a)
S
bq27200 generated
ADDR[6:0]
0
A
CMD[7:0]
Sr
A
ADDR[6:0]
1
A
A
DATA[7:0]
(b)
DATA[7:0]
N
(c)
S
ADDR[6:0]
0
A
CMD[7:0]
A
Sr
ADDR[6:0]
1
A
DATA[7:0]
A
...
N
P
N
P
P
DATA[7:0]
(d)
Figure 7. Supported I2C formats :
(a) 1-byte write; (b) quick read; (c) 1-byte read; (d) incremental read
The incremental read protocol is recommended for reading all 16-bit values, as this ensures that the 16-bit value
is not updated during the time interval between reading the two bytes of data (see previous section on reading
16-bit values). The quick read returns data at the address indicated by the internal address pointer. The address
pointer is incremented after each data byte is read or written. Reading an even address causes the
communication engine to simultaneously capture the data byte from the requested even address and the data
byte from the next odd address, and the address pointer is incremented twice. The data byte captured from the
next odd address is output if the communication continues, without a stop, after the host acknowledges the even
address byte.
Due to the memory map setup of the device, several boundary conditions must be enforced by the
communication engine.
Attempt to write a read-only address (NACK after data sent by master):
S
ADDR[6:0]
0
A
CMD[7:0]
A
DATA[7:0]
N
P
Attempt to read an address above 0x7F (NACK command):
S
ADDR[6:0]
0
A
CMD[7:0]
N
P
Attempt at incremental writes (NACK all extra data bytes sent):
S
ADDR[6:0]
0 A
CMD[7:0]
A
DATA[7:0]
A
DATA[7:0]
N
...
N P
Incremental read at the maximum allowed read address:
S
ADDR[6:0]
0 A
CMD[7:0]
A Sr
ADDR[6:0]
1 A
DATA[7:0]
Address
0x7F
A
Data from
addr 0x7F
DATA[7:0]
N P
Data from
addr 0x00
The I2C engine releases both SDA and SCL if the I2C bus is held low for T(BUSERR). If the bq27200 was holding
the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines
low, the I2C engine enters the low-power sleep mode if the measured charge and discharge activity level are less
than the DMF threshold.
26
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ27000DRKR
NRND
VSON
DRK
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-20 to 70
27000
BQ27200DRKR
NRND
VSON
DRK
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-20 to 70
27200
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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