BQ29312PWR

PW bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 THREE AND FOUR CELL LITHIUM-ION OR LITHIUM-POLYMER BATTERY PROTECTION AFE FEATURES APPLICATIONS • • • • • • • • • • • • • • 2-, 3-, or 4-Cell Series Protection Control Can Directly Interface With the bq2084 Gas Gauges Provides Individual Cell Voltages and Battery Voltage to Battery Management Host Integrated Cell Balancing Drive I2C Compatible User Interface Allows Access to Battery Information Programmable Threshold and Delay for Over Load and Short Circuit During Charge and Discharge System Alert Interrupt Output Host Control Can Initiate Sleep Power Mode and Ship Mode Integrated 3.3-V, 25-mA LDO Supply Voltage Range From 4.5 V to 25 V Low Supply Current of 60-µA Typical Notebook PCs Medical and Test Equipment Portable Instrumentation DESCRIPTION The bq29312 is a 2-, 3-, or 4-cell lithium-ion battery pack protection analog front end (AFE) IC that incorporates a 3.3-V, 25-mA low-dropout regulator (LDO). The bq29312 also integrates an I2C compatible interface to extract battery parameters such as cell voltages and control output status. Other parameters such as current protection thresholds and delays can be programmed into the bq29312 to increase the flexibility of the battery management system. The bq29312 provides safety protection for overcharge, overload, short-circuit, overvoltage, and undervoltage conditions in conjunction with the battery management host. In overload and short-circuit conditions, the bq29312 turns the FET drive off autonomously dependant on the internal configuration setting. SYSTEM PARTITIONING DIAGRAM Discharge / Charge / Pre-Charge FETs Fuse Pack + bq29312 PF Input PCH FET Drive Power Management LDO, TOUT and Power mode control Temperature Measurement 1 ->0 clears the fault latches OUTPUT CTL b1 (DSG): This bit controls the external discharge FET. 0 = discharge FET is off and is controlled by the system host (default). 1 = discharge FET is on and the bq29312 is in normal operating mode. OUTPUT CTL b2 (CHG): This bit controls the external charge FET. PMS=GND 0 = charge FET is off and is controlled by the system host (default). 1 = charge FET is on and the bq29312 is in normal operating mode. PMS=PACK 0 = charge FET is off and is controlled by the system host. 1 = charge FET is on and the bq29312 is in normal operating mode (default). OUTPUT CTL b3 (XZVCHG): This bit controls the external ZVCHG FET. 0 = ZVCHG FET is on and is controlled by the system host (default). 1 = ZVCHG FET is off and the bq29312 is in normal operating mode. OUTPUT CTL b4 (OD): This bit enables or disables the OD output. 0 = OD is high impedance (default). 1 = OD output is active (GND). STATE CTL: State Control Register STATE CTL REGISTER (0x02) 7 6 5 4 3 2 1 0 0 0 0 0 0 WDDIS SHIP SLEEP The STATE CTL register controls the state of the bq29312. STATE CTL b0 (SLEEP): This bit is used to enter the sleep power mode. 0 = bq29312 exits sleep mode (default). 1 = bq29312 enters the sleep mode. STATE CTL b1 (SHIP): This bit is used to enter the ship power mode when pack supply voltage is not applied. 0 = bq29312 in normal mode (default). 1 = bq29312 enters ship mode when pack voltage is removed. STATE CTL b2 (WDDIS): This bit is used to enable or disable the watchdog timer function. 0 = enable clock monitoring (default). 1 = disable clock monitoring. NOTE: Use caution when setting the WDDIS. For example, when the 32-kHz input fails, the overload and short-circuit delay timers no longer function because they use the same WDI input. If the WDI input clock stops, these current protections do not function. WDF should be enabled at any time for maximum safety. If the watchdog function is disabled, the CHG and DSG FETs should be turned off. 18 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 FUNCTION CTL: Function Control Register FUNCTION CTL REGISTER (0x03) 7 6 5 4 3 2 1 0 0 0 TOUT XSCD SSCC XOL PACKOUT VMEN The FUNCTION CTL register enables and disables functons of the bq29312. FUNCTION CTL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function. 0 = disable voltage monitoring (default). CELL output is pulled down to GND level. 1 = enable voltage monitoring. FUNCTION CTL b1 (PACKOUT): This bit is used to translate the PACK input to the CELL pin when VMEN=1 The pack voltage is divided by 25 and is presented on CELL regardless of the CELL_SEL register settings. 0 = disable PACK OUT (default). 1 = enable PACK OUT. FUNCTION CTL b2 (XOL): This bit enables or disables the over current sense function. 0 = enable over load sense (default). 1 = disable over load sense. FUNCTION CTL b3 (XSCC): This bit enables or disables the short current sense function of charging. 0 = enable short-circuit current sense in charge direction (default). 1 = disable short-circuit current sense in charge direction. FUNCTION CTL b4 (XSCD): This bit enables or disables the short current sense function of discharge. 0 = enable short-circuit current sense in discharge direction (default). 1 = disable short-circuit current sense in discharge direction. FUNCTION CTL b5 (TOUT): This bit controls the power to the thermistor. 0 = thermistor power is off (default). 1 = thermistor power is on. 19 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 CELL SEL: Cell Select Register CELL_SEL REGISTER (0x04) 7 6 5 4 3 2 1 0 CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0 This register determines cell selection for voltage measurement and translation, cell balancing and the operational mode of the cell voltage monitoring. CELL_SEL b0–b1 (CELL0–CELL1): These two bits select the series cell for voltage measurement translation. CELL1 CELL0 0 0 VC4–VC5, Bottom series element (Default) SELECTED CELL 0 1 VC4–VC3, Second lowest series element 1 0 VC3–VC2, Second highest series element 1 1 VC1–VC2, Top series element CELL_SEL b2–b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block. CAL1 CAL0 0 0 Cell translation for selected cell (default) SELECTED MODE 0 1 Offset measurement for selected cell 1 0 Monitor the VREF value for gain calibration 1 1 Monitor the VREF directly value for gain calibration, bypassing the translation circuit CELL_SEL b4–b7 (CB0–CB3): These 4 bits select the series cell for cell balance bypass path. CELL SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path 0 = disable bottom series cell balance charge bypass path (default). 1 = enable bottom series cell balance charge bypass path. CELL SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path. 0 = disable series cell balance charge bypass path (default). 1 = enable series cell balance charge bypass path. CELL SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path. 0 = disable series cell balance charge bypass path (default). 1 = enable series cell balance charge bypass path. CELL SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path. 0 = disable series cell balance charge bypass path (default). 1 = enable series cell balance charge bypass path. 20 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 OLV: Overload Voltage Threshold Register OLV REGISTER (0x05) 7 6 5 4 3 2 1 0 0 0 0 OLV4 OLV3 OLV2 OLV1 OLV0 OLV (b4–b0): These five bits select the value of the over load threshold with a default of 00000. OLV (b4–b0) configuration bits with corresponding voltage threshold 00000 0.050 V 01000 0.090 V 10000 0.130 V 11000 0.170 V 00001 0.055 V 01001 0.095 V 10001 0.135 V 11001 0.175 V 00010 0.060 V 01010 0.100 V 10010 0.140 V 11010 0.180 V 00011 0.065 V 01011 0.105 V 10011 0.145 V 11011 0.185 V 00100 0.070 V 01100 0.110 V 10100 0.150 V 11100 0.190 V 00101 0.075 V 01101 0.115 V 10101 0.155 V 11101 0.195 V 00110 0.080 V 01110 0.120 V 10110 0.160 V 11110 0.200 V 00111 0.085 V 01111 0.125 V 10111 0.165 V 11111 0.205 V OLT: Overload Blanking Delay Time Register OLT REGISTER (0x06) 7 6 5 4 3 2 1 0 0 0 0 0 OLT3 OLT2 OLT1 OLT0 OLT(b3–b0): These four bits select the value of the delay time for overload with a default of 0000. OLT(b3–b0) configuration bits with corresponding delay time 0000 1 ms 0100 9 ms 1000 17 ms 1100 25 ms 0001 3 ms 0101 11 ms 1001 19 ms 1101 27 ms 0010 5 ms 0110 13 ms 1010 21 ms 1110 29 ms 0011 7 ms 0111 15 ms 1011 23 ms 1111 31 ms SCC: Short Circuit in Charge Configuration Register SCC REGISTER (0x07) 7 6 5 4 3 2 1 0 SCCT3 SCCT2 SCCT1 SCCT0 SCCV3 SCCV2 SCCV1 SCCV0 This register selects the short-circuit threshold voltage and delay for charge. SCC(b3–b0) : These bits select the value of the short-circuit voltage threshold with 0000 as the default. SCC(b3–b0) with corresponding SC threshold voltage 0000 0.100 V 0100 0.200 V 1000 0.300 V 1100 0.400 V 0001 0.125 V 0101 0.225 V 1001 0.325 V 1101 0.425 V 0010 0.150 V 0110 0.250 V 1010 0.350 V 1110 0.450 V 0011 0.175 V 0111 0.275 V 1011 0.375 V 1111 0.475 V 21 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 SCC(b7–b4): These bits select the value of the short-circuit delay time. Exceeding the short-circuit voltage threshold for longer than this period will turn off the corresponding CHG, DSG, and ZVCHG output. 0000 is the default. SCC(b7–b4) with corresponding SC delay time 0000 0 µs 0100 244 µs 1000 488 µs 1100 732 µs 0001 61 µs 0101 305 µs 1001 549 µs 1101 793 µs 0010 122 µs 0110 366 µs 1010 610 µs 1110 854 µs 0011 183 µs 0111 427 µs 1011 671 µs 1111 915 µs SCD: Short Circuit in Discharge Configuration Register SCD REGISTER (0x08) 7 6 5 4 3 2 1 0 SCDT3 SCDT2 SCDT1 SCDT0 SCDV3 SCDV2 SCDV1 SCDV0 This register selects the short-circuit threshold voltage and delay for discharge. SCD(b3–b0) with corresponding SC threshold voltage with 0000 as the default. SCD(b3–b0): These bits select the value of the short-circuit voltage threshold 0000 0.10 V 0100 0.20 V 1000 0.30 V 1100 0.40 V 0001 0.125 V 0101 0.225 V 1001 0.325 V 1101 0.425 V 0010 0.150 V 0110 0.250 V 1010 0.350 V 1110 0.450 V 0011 0.175 V 0111 0.275 V 1011 0.375 V 1111 0.475 V SCD(b7–b4): These bits select the value of the short-circuit delay time. Exceeding the short-circuit voltage threshold for longer than this period will turn off the corresponding CHG, DSG, and ZVCHG output as has 0000 as the default. SCD(b7-b4) with corresponding SC delay time 22 0000 0 µs 0100 244 µs 1000 488 µs 1100 732 µs 0001 61 µs 0101 305 µs 1001 549 µs 1101 793 µs 0010 122 µs 0110 366 µs 1010 610 µs 1110 854 µs 0011 183 µs 0111 427 µs 1011 671 µs 1111 915 µs bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION Precharge and 0-V Charging—Theory of Operation In order to charge, the charge FET (CHG-FET) must be turned on to create a current path. When the V(BAT) is 0 V and CHG-FET = ON, the V(PACK) is as low as the battery voltage. In this case, the supply voltage for the device is too low to operate. There are 3 possible configurations for this function and the bq29312 can be easily configured according to the application needs. The 3 modes are 0-V Charge FET Mode, Common FET Mode and Precharge FET Mode. 1. 0-V Charge FET Mode – Dedicates a precharge current path using an additional FET (ZVCHG-FET) to sustain the PACK+ voltage level. The host charger is expected to provide a precharge function. 2. Common FET Mode – Does not use a dedicated precharge FET. The charge FET (CHG-FET) is assured to be set to ON state as default. The charger is expected to provide a precharge function. 3. Precharge FET Mode – Dedicates a precharge current path using an additional open drain (OD) pin drive FET (PCHG-FET) FET to sustain the PACK+ voltage level. The charger does not provide any precharge function. 0-V Charge FET Mode In this mode, a dedicated precharge current path using an additional FET (ZVCHG-FET) is required to sustain a suitable PACK+ voltage level. The charger is expected to provide the precharge function in this mode where the precharge current level is suitable to charge cells below a set level, typically below 3 V per cell. When the lowest cell voltage rises above this level, then a fast charging current is applied by the charger. The circuit diagram for this method is shown in Figure 7, showing how the additional FET is added in parallel with the charge FET (CHG-FET). R(ZVCHG) Charger ZVCHG-FET CC DC Input IZVCHG DSG-FET CHG-FET DSG BAT CHG bq29312 Pack+ IFASTCHG PACK ZVCHG Battery REG OD CV PMS 4.7 µF NC I(ZVCHG) = 0 V Percharge Current I(FASTCHG) = Fast Current Figure 7. 0-V Charge FET Mode Circuit 23 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) In order to pass 0 V or precharge current an appropriate gate-source voltage V(GS), for ZVCHG-FET must be applied. Here, V(PACK) can be expressed in terms of V(GS) as follows: V(PACK) = V(ZVCHG) + V(GS)(ZVCHG-FET gate - source voltage) ID Point B Point A Precharge Current VGS VDS Figure 8. Drain Current vs Drain-Source Voltage Characteristics In the bq29312, the initial state is for CHG-FET = OFF and ZVCHG-FET = ON with the V(ZVCHG) clamped at 3.5 V initially. Then the charger applies a constant current and raises V(PACK) high enough to pass the precharge current, point A. For example, if the V(GS) is 2 V at this point, V(PACK) is 3.5 V + 2 V = 5.5 V. Also, the ZVCHG-FET is used in its MOS saturation region at this point so that V(DS) is expressed as follows: V(PACK) = V(BAT) + VF + VDS(ZVCHG-FET) where V(F) = 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V. This derives the following equation: VDS = 4.8 V - V(BAT) As the battery is charged V(BAT) increases and the V(DS) voltage decreases reaching its linear region. For example: If the linear region is 0.2 V, this state continues until V(BAT) = 4.6 V, (4.8 V - 0.2 V). As V(BAT) increases further, V(PACK) and the V(GS) voltage increase. But the VDS remains at 0.2 V because the ZVCHG-FET is driven in its MOS linear region, point B. V(PACK) = VF + 0.2 V + V(BAT) where VF = 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V The R(ZVCHG) purpose is to split heat dissipation across the ZVCHG-FET and the resistor. ZVCHG pin behavior is shown in Figure 9 where V(ZVCHG) is set to 0 V at the beginning. 24 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) 20 18 16 V(PACK) 14 Voltage - V V(ZVCHG)= V(PACK) - 8 V V(BAT) 12 10 8 6 4 V(ZVCHG)= V(PACK) / 2 2 3.5 V 0 0 4 8 12 t - Time - mS 16 20 Figure 9. Voltage Transition at ZVCHG, PACK and BAT As V(PACK) exceeds 7 V, V(ZVCHG) = V(PACK)/2. However, V(ZVCHG) is maintained to limit the voltage between PACK and ZVCHG at a maximum of 8 V(typ). This limitation is intended to avoid excessive voltage between the gate and the source of ZVCHG-FET. The signal timing is shown in Figure 10. When precharge begins (V(BAT) = 0 V) V(PACK) is clamped to 3.5 V and holds the supply voltage for bq29312 operation. After V(BAT) reaches sufficient voltage high enough for bq29312 operation, the CHG-FET and the DSG-FET are turned ON and ZVCHG-FET is turned OFF. Although the current path is changed, the same precharging current is still applied. When V(BAT) reaches the fast charging voltage (typical 3 V per cell), the charger switches into fast charging mode. 25 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) V(PACK) 3.5 V+VGS(ZVCHGFET) 0V 3.3 V 0V REG ZVCHG FET = OFF ON V = VPACK*(1/2) ZVCHG 3.5 V (typ.) 0V OFF CHG FET = ON GHD ”L” (1 V) OFF CHG FET = ON DSG ”L” (1 V) Battery Voltage 0V Charge Current Fast Charge Current 0 V and Precharge Current 0A 0 V Charge Mode Precharge Mode Fast Charge Mode Figure 10. Signal Timing of Pins During 0 V Charging and Precharging (0 V Charge FET) Common FET This mode does not require a dedicated precharge FET (ZVCHG-FET). The charge FET (CHG-FET) is ON at initialization of the bq29312 when PMS = V(PACK) allowing for 0 V or precharge current to flow. The application circuit is shown in Figure 11. The charger is expected to provide the precharge function in this mode, where the charger provides a precharge current level suitable to charge cells below a set level, typically below 3.0 V per cell. When the lowest cell voltage rises above this level then a fast charging current is applied. When the charger is connected the voltage at PMS rises. Once it is above 0.7 V, the CHG output is driven to GND which turns ON the CHG-FET. The charging current flows through the CHG-FET and a back diode of DSG-FET. The pack voltage is represented by the following equation. V(PACK) = V(BAT) + VF + VDS(CHG-FET) Where VF = 0.7 V is the forward voltage of a DSG-FET back diode and is typically 0.7 V. While V(PACK) is maintained above 0.7 V the precharging current is maintained. While V(PACK) and V(BAT) are under the bq29312 supply voltage then the bq29312 regulator is inactive and the host controller is not functional. Thus, any protection features of this chipset do not function during this period. This state continues until V(PACK) goes higher than the bq29312 minimum supply voltage. When V(BAT) rises and V(PACK) reaches bq29312 minimum supply voltage, the REG output is active providing a 3.3 V (typ) supply to the host. When this level is reached the CHG pin changes its state from GND to the level controlled with CHG bit in bq29312 registers. In this state, the CHG output level is driven by a clamp circuit so that its voltage level changes from 0 V to 1 V. Also, the host controller is active and can turn ON the DSG-FET. 26 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) The disadvantages is that during 0 V charging, bq29312 is inactive. The device does not protect the battery and does not update battery information (now is 0 V charging) to the PC. There are two advantage of this configuration: 1. The voltage between BAT and PACK is lower. Higher precharge current is allowed due to less heat loss is the FET and no external resistor required. 2. The charge FET is turned on during precharging. The precharge current can be fully controlled by the charger. Charger CC DC Input I(ZVCHG) DSG-FET CHG-FET DSG BAT CHG PACK bq29312 Battery REG OD 4.7 µF NC ZVCHG Pack+ I(FASTCHG) CV PMS I(ZVCHG) = 0 V Percharge Current I(FASTCHG) = Fast Current Figure 11. Common FET Mode Circuit Diagram The signal timing during the common FET mode is shown in Figure 12. The CHG-FET is turned on when the charger is connected. As V(BAT) rises and V(PACK) reaches the bq29312 minimum supply voltage, the REG output becomes active and the host controller starts to work. When V(PACK) becomes high enough, the host controller turns ON the DSG-FET. The charger enters the fast charging mode when V(BAT) reaches the fast charge level. 27 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) 0.7 V 0V V(PACK) Host = Inactive Host = Active REG 3.3 V 0V PMS CHG Set to ”L” as PMS = PACK 0V Set to ”L” by Host ”L” (1 V) 0V DSG Host Sets DSG-FET to ON ”L” (1 V) Battery Voltage 0V Charge Current Fast Charge Current 0 V and Precharge Current 0A 0 V Precharge Mode Fast Charge Mode Figure 12. Signal Timing of Pins During 0 V Charging and Precharging (Common FET) Precharge FET This mode has a dedicated precharge current path using an additional open drain driven FET (PCHG-FET) and sustains the V(PACK) level. In this mode, where the PMS input is connected to GND, the bq29312 and host combine to provide the precharge function by limiting the fast charge current which is provided by the system side charger. Figure 13 shows the bq29312 application circuit in this mode. 28 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) R(PCHG) Charger PCHG-FET CC DC Input I(FASTCHG) DSG-FET CHG-FET DSG CHG PACK OD BAT CV bq29312 Battery Pack+ ZVCHG PMS REG SCLK SDATA 4.7 µF I(FASTCHG) = Fast Current Host Figure 13. Precharge FET Mode Circuit Diagram The PCHG-FET is driven by the OD output and the resister R(PCHG) in the precharge path limits the precharge current. When OD = GND then the PCHG-FET is ON. The precharge current is represented by the following equation: I(PCHG) = ID = ( V(PACK) - V(BAT) - VDS )/R(PCHG) • A load curve of the PCHG-FET is shown in Figure 14. When the drain-source voltage (VDS) is high enough, the PCHG-FET operates in the linear region and has low resistance. By approximating VDS as 0 V, the precharge current, I(PCHG) is expressed as below. • I(PCHG) = ( V(PACK) - V(BAT) )/R(PCHG) ID ID = (V(PACK) - V(BAT) - VDS)/R(PCHG) VSD Figure 14. PCHG-FET ID—VDS Characteristic During the precharge phase, CHG-FET is turned OFF and PCHG-FET is turned ON. When all the cell voltages measured by the host reach the fast charge threshold, the host controller turns ON CHG-FET and turns OFF PCHG-FET. The signal timing is shown in Figure 15. When the charger is connected, CHG-FET, DSG-FET and PCHG-FET are already in the OFF state. When the charger in connected it applies V(PACK). The bq29312 REG output then becomes active and supplies power to the host controller. As the host controller starts up, it turns on the OD pin and the precharge current is enabled. 29 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) In this configuration, attention must be paid to high power consumption in the PCHG-FET and the series resistor R(PCHG). The highest power is consumed when VBAT = 0 V, where it is the highest differential between the PACK and BAT pins. For example, the power consumption in 4 series cells with 17.4 V fast charge voltage and R(PCHG) = 188 Ω is expressed below. • IPCHG = (17.4 V – 0.0 V)/188 Ω = 92.6 mA • 17.4 V × 92.6 mA = 1.61 W An optional solution is to combine a thermistor with a resistor to create R(PCHG), therefore, as temperature increases, the current reduces. Once the lowest cell voltage reaches the fast charge level (typ 3.0 V per cell), the host controller turns ON CHG-FET and DSG-FET, and turns OFF PCHG-FET. It is also appropriate to turn on DSG-FET during precharge in order to supply precharge current efficiently, as shown in Figure 15. Charge CV V(PACK) 0V Host : Active REG 3.3 V 0V OD OFF PCHG FET = ON OFF 0V CHG CHG FET = OFF ”L” (1 V) DSG FET = ON DSG OFF ”L” (1 V) Battery Voltage Charge Current 0V Fast Charge Current Charge 0 V and Precharge Current 0A Charge Mode 0 V and Precharge Mode Fast Charge Mode Figure 15. Signal Timing of Pins During 0 V Charging and Precharging (Precharge FET) 30 bq29312 www.ti.com SLUS546E – MARCH 2003 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) Summary The three types of 0-V charge options available with the bq29312 are summarized in Table 4. Table 4. Charge Options CHARGE MODE TYPE HOST CHARGE CAPABILITIES KEY APPLICATION CIRCUIT NOTES PMS = GND 1) 0-V Charge FET Fast charge and precharge ZVCHG: Drives 0-V charge FET (ZVCHG-FET) OD: Not used PMS = PACK 2) Common FET Fast charge and precharge ZVCHG: Not used OD: Not used PMS = GND 3) Precharge FET Fast charge but no precharge function ZVCHG: Not used OD: Drives the precharge FET (PCHG-FET) There a number of tradeoffs between the various 0-V charge modes which are discussed below. • 0-V Charge FET (1) vs Common FET (2) When the charger has both of precharge and charging functions, there are two types of circuit configuration available. 1. 0-V Charge FET – The bq29312 is active even during precharge. Therefore, the host can update the battery status to the system and protect the battery pack by detecting abnormal conditions. – A high voltage is applied on the 0-V charge FET at 0-V cell voltage. In order to avoid excessive heat generation the 0-V charge current must be limited. 2. Common FET – During 0-V charge the bq29312 and the host are not active. Therefore, they cannot protect the cells and cannot update the battery status to the system. – The bq29312 can tolerate high 0-V charge current as heat generation is not excessive. – A dedicated FET for the 0-V charge is not required. • 0-V Charge FET (1) vs Precharge FET (3) The current paths of the 0-V charge FET (1) and Precharge FET (3) modes are the same. If the 0-V charge FET (1) mode is used with chargers without precharge function, the bq29312 consumes extra current of up to 1 mA in order to turn ON the ZVCHG output. 1. If the charger has a precharge function - ZVCHG-FET is turned ON only during 0-V charging. In this case, 1 mA increase is not a concern because the charger is connected during the 0-V charging period. 2. If the charger does not have precharge function - The ZVCHG-FET must be turned ON during 0-V charging and also precharging. When the battery reaches an over discharged state, it must turn OFF DSG-FET and CHG-FET and turn ON ZVCHG-FET. The reason for this is the battery must keep the 0-V charge path while waiting for a charger to be connected to limit the current. – Consuming 1 mA, while waiting for a charger to be connected in over discharge state, is significant if compared to current consumption of other modes. • Precharge FET (3) If the precharge FET (3) mode is used with a charger with precharge function, care must be taken as limiting the 0-V charge current with resistance may cause some issues. The charger may start fast charge immediately, or detect an abnormal condition. When the charger is connected, the charger may raise the output voltage to force the precharge current. In order to assure a supply voltage for the bq29312 during 0-V charging, the resistance of a series resister (RPCHG) must be high enough. This may result in a very high VPACK, and some chargers may detect it as an abnormal condition. 31 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ29312PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 29312PW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of