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bq32000
SLUS900E – DECEMBER 2008 – REVISED AUGUST 2015
bq32000 Real-Time Clock (RTC)
1 Features
3 Description
•
•
•
The bq32000 device is a compatible replacement for
industry standard real-time clocks.
1
•
•
•
Automatic Switchover to Backup Supply
I2C Interface Supports Serial Clock up to 400 kHz
Uses 32.768-kHz Crystal With –63-ppm to
+126-ppm Adjustment
Integrated Oscillator-Fail Detection
8-Pin SOIC Package
–40°C to 85°C Ambient Operating Temperature
2 Applications
•
General Consumer Electronics
The bq32000 features an automatic backup supply
with integrated trickle charger. The backup supply
can be implemented using a capacitor or nonrechargeable battery. The bq32000 has a
programmable calibration adjustment from –63 ppm
to +126 ppm. The bq32000 registers include an OF
(oscillator fail) flag indicating the status of the RTC
oscillator, as well as a STOP bit that allows the host
processor to disable the oscillator. The time registers
are normally updated once per second, and all the
registers are updated at the same time to prevent a
timekeeping glitch. The bq32000 includes automatic
leap-year compensation.
Device Information(1)
PART NUMBER
bq32000
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm x 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
3.0 to 3.6 V
Controller
bq32000
SCL
SDA
____
IRQ
Real-Time
Clock
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq32000
SLUS900E – DECEMBER 2008 – REVISED AUGUST 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Timing Requirements..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes........................................ 10
7.5 Programming........................................................... 10
7.6 Register Maps ......................................................... 12
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 19
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2011) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Added Storage Temperature to Absolute Maximum Ratings ................................................................................................. 4
•
Changed VCC = 0 to VCC needs a pulse................................................................................................................................ 5
2
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
OSCI
1
8
VCC
OSCO
2
7
IRQ
VBACK
3
6
SCL
GND
4
5
SDA
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
POWER AND GROUND
GND
4
-
Ground
VBACK
3
-
Backup device power
VCC
8
-
Main device power
I2C serial interface clock
SERIAL INTERFACE
SCL
6
I
SDA
5
I/O
I2C serial data
7
O
Configurable interrupt output. Open-drain output.
OSCI
1
-
Oscillator input
OSCO
2
-
Oscillator output
INTERRUPT
IRQ
OSCILLATOR
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Input voltage, VIN
MIN
MAX
UNIT
VCC to GND
–0.3
4
V
All other pins to GND
–0.3
VCC + 0.3
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–60
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC
Supply voltage, VCC to GND
TA
Operating free-air temperature
fo
Crystal resonant frequency
RS
Crystal series resistance
CL
Crystal load capacitance
NOM
MAX UNIT
3
3.6
V
–40
85
°C
32.768
10.8
12
kHz
70
kΩ
13.2
pF
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
bq32000
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
114.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.1
°C/W
RθJB
Junction-to-board thermal resistance
55.5
°C/W
ψJT
Junction-to-top characterization parameter
11.9
°C/W
ψJT
Junction-to-board characterization parameter
55
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
ICC
VCC supply current
VBACK
Backup supply voltage
IBACK
Backup supply current
μA
100
Operating
1.4
VCC
Switchover
2.0
VCC
VCC needs a pulse
(1)
, VBACK = 3 V, Oscillator on, TA = 25°C
1.2
V
1.5
μA
0.3 VCC
V
1
μA
LOGIC LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
IIN
Input current
0.7 VCC
0 V ≤ VIN ≤ VCC
V
-1
LOGIC LEVEL OUTPUTS
VOL
Output low voltage
IL
Leakage current
IOL = 3 mA
0.4
V
1
μA
-1
REAL-TIME CLOCK CHARACTERISTICS
Pre-calibration accuracy
(1)
(2)
±35 (2)
VCC = 3.3 V, VBACK = 3 V, Oscillator on, TA = 25°C
ppm
The currents measured after issuing a pulse on VCC. The pulse amplitude 0-VCC; pulse width min 1 ms.
Typical accuracy is measured using reference board design and KDS DMX-26S surface-mount 32.768-kHz crystal. Variation in board
design and crystal section results in different typical accuracy.
6.6 I2C Timing Requirements
STANDARD MODE
MIN
MAX
100
FAST MODE
MIN
MAX
0
400
UNIT
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
μs
tscl
I2C clock low time
4.7
1.3
μs
2
tsp
I C spike time
tsds
I2C serial data setup time
tsdh
I2C serial data hold time
ticr
I2C input rise time
0
50
0
250
100
0
0
1000
2
ns
ns
ns
20 + 0.1Cb
(1)
300
300
ns
300
μs
ticf
I C input fall time
300
20 + 0.1Cb
(1)
tocf
I2C output fall time
300
20 + 0.1Cb
(1)
tbuf
I2C bus free time
2
50
kHz
ns
4.7
1.3
μs
tsts
I C Start setup time
4.7
0.6
μs
tsth
I2C Start hold time
4
0.6
μs
tsps
I2C Stop setup time
4
0.6
μs
tvd(data)
Valid data time (SCL low to SDA valid)
1
1
μs
tvd(ack)
Valid data time of ACK
(ACK signal from SCL low to SDA low)
1
1
μs
(1)
Cb = total capacitance of one bus line in pF
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ticf
SDA
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ticr
tsdh
tvd
0.7 VCC
0.3 VCC
Start Condition
ticf
ticr
tsds
tsch
SCL
0.7 VCC
1
0.3 VCC
2
3
4
tscl
tsth
1/fscl
Stop Condition
tvd
SDA
0.7 VCC
tbuf
D7/A
0.3 VCC
Start Condition
tsds
SCL
0.7 VCC
8
0.3 VCC
9
tsps
Figure 1. I2C Timing Diagram
6.7 Typical Characteristics
VCC = 2 V
Iback (uA)
45
20
100
Icc (uA)
107.5
90
15
80
106
70
40
10
50
35
40
30
30
ICC (uA)
60
Iback (uA)
ICC (uA)
VCC = 3.3 V
104.5
5
103
Iback (uA)
50
0
20
101.5
10
25
-10
20
0.5
1.0
1.5
2.0
Vbackup (V)
2.5
2.4
-10
2.9
3.4
Vbackup (V)
C001
Figure 2. Current Consumption vs Backup Supply Voltage
6
Iback (uA)
100
3.0
-5
Icc (uA)
0
3.9
C002
Figure 3. Current Consumption vs Backup Supply Voltage
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7 Detailed Description
7.1 Overview
The bq32000 is a real-time clock that features an automatic backup supply with an integrated trickle charger.
7.2 Functional Block Diagram
VCC
Place supply-decoupling
capacitor near supply pin
1 µF
VCC
VCC
Trickle
Charge
Automatic
Backup
Switch
VBACK
Use only
super-capacitor
or battery,
not both
4.7 kW
VCORE
0.22 F
Interrupt
Generator
OSCI
OSCO
32-kHz
Oscillator
I2C Register
Interface With
Undervoltage
Lockout
4.7 kW
4.7 kW
IRQ
SCL
SDA
Registers
GND
NOTE: All pullup resistors should be connected to VCC such that no pullup is applied during backup supply operation.
7.3 Feature Description
7.3.1
IRQ Function
The IRQ pin of the bq32000 functions as a general-purpose output or a frequency test output. The function of
IRQ is configurable in the device register space by setting the FT, FTF, and OUT bits. On initial power cycles,
the OUT bit is set to one, and the FTF and FT bits are set to zero. On subsequent power-ups, with backup
supply present, the OUT bit remains unchanged, and the FTF and FT bits are set to zero. When operating on
backup supply, the IRQ pin function is unused. IRQ pullup resistor should be tied to VCC to prevent IRQ operation
when operating on backup supply. The effect of the calibration logic is not normally observable when IRQ is
configured to output 1 Hz. The calibration logic functions by periodically adjusting the width of the 1-Hz clock.
The calibration effect is observable only every eight or sixteen minutes, depending on the sign of the calibration.
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Feature Description (continued)
Figure 4. IRQ Pin Functional Diagram
Table 1. IRQ Function
8
FT
OUT
FTF
1
X
1
1 Hz
1
X
0
512 Hz
0
1
X
1
0
0
X
0
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IRQ STATE
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7.3.2 VBACK Switchover
The bq32000 has an internal switchover circuit that causes the device to switch from main power supply to
backup power supply when the voltage of the main supply pin VCC drops below a minimum threshold. The VBACK
switchover circuit uses an internal reference voltage VREF derived from the on-chip bandgap reference; VREF is
approximately 2.8 V. The device switches to the VBACK supply when VCC is less than the lesser of VBACK or VREF.
Similarly, the device switches to the VCC supply when VCC is greater than either VBACK or VREF.
Some registers are reset to default values when the RTC switches from main power supply to backup power
supply. Please see the register definitions to determine what register bits are effected by a backup switchover
(effected bits have their reset value (1/0) shown for 'Cycle', bits that are unchanged by backup are marked 'UC').
The time keeping registers can take up to 1 second to update after the RTC switches from backup power supply
to main power supply.
V BACK > VREF
V BACK > VREF
3.3V
VB AC K
VR E F
VCC
Voltage
Voltage
VC C
–5 V/ms (max)
3.3V
VB AC K
VR E F
T ime
On VC C
Time
On V BAC K
On V BAC K
V REF > V BACK
V REF > V BACK
3.3V
3.3V
VR E F
VR E F
Voltage
VB AC K
VCC
Voltage
VB AC K
VCC
–5 V/ms (max)
T ime
On VC C
On V C C
Time
On V BAC K
On V BAC K
On V C C
Figure 5. Switchover Diagram
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7.3.3 Trickle Charge
The bq32000 includes a trickle charge circuit to maintain the charge of the backup supply when a super
capacitor is used. The trickle charge circuit is implemented as a series of three switches that are independently
controlled by setting the TCHE[3:0], TCH2, and TCFE bits in the register space.
TCHE[3:0] must be written as 0x5h and TCH2 as 1 to close the trickle charge switches and enable charging of
the backup supply from VCC. Additionally, TCFE can be set to 1 to bypass the internal diode and boost the
charge voltage of the backup supply. All trickle charge switches are opened when the device is initially powered
on and each time the device switches from the main supply to the backup supply. The trickle charge circuit is
intended for use with super capacitors; however, it can be used with a rechargeable battery under certain
conditions. Care must be taken not to overcharge a rechargeable battery when enabling trickle charge. Follow all
charging guidelines specific to the rechargeable battery or super capacitor when enabling trickle charge.
20 kW
VBACK
180 W
940 W
Figure 6. Trickle Charge Switch Functional Diagram
7.4 Device Functional Modes
When the device switches from the main power supply to backup supply, the Time keeping register Registers [09] cannot be accessed via the I2C. The access to these registers are only when VCC > Vref.
The Time keeping registers can take up to 1 second to update after the device switches from backup power
supply to main power supply.
7.5 Programming
7.5.1 I2C Serial Interface
The I2C interface allows control and monitoring of the RTC by a microcontroller. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000).
The bus consists of a data line (SDA) and a clock line (SCL) with off-chip pullup resistors. When the bus is idle,
both SDA and SCL lines are pulled high.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer.
A slave device receives and/or transmits data on the bus under control of the master device. This device
operates only as a slave device.
I2C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while
SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first,
including the data direction bit (R/W). After receiving a valid address byte, this device responds with an
acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. This device
responds to the I2C slave address 11010000b for write commands and slave address 11010001b for read
commands.
This device does not respond to the general call address.
10
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Programming (continued)
A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W
bit is high, the data from this device are the values read from the register previously selected by a write to the
subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if
complete bytes are received and acknowledged.
A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the
master to terminate the transfer. A master device must wait at least 60 μs after the RTC exits backup mode to
generate a START condition.
Slave
Address
(DN)
0
Sub
Address
R
(DN+1)
0 0 0
Slave
Address
ACK
0 0 0W
ACK
START
0
1
S
DataN
DataN+1
NACK
STOP
1 1
(AN)
ACK
1
ACK
START
1 1
S
Figure 7. I2C Read Mode
Figure 8. I2C Write Mode
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7.6 Register Maps
Table 2. Normal Registers
REGISTER
ADDRESS
(HEX)
REGISTER NAME
0
0x00
SECONDS
Clock seconds and STOP bit
1
0x01
MINUTES
Clock minutes
2
0x02
CENT_HOURS
3
0x03
DAY
Clock day
4
0x04
DATE
Clock date
5
0x05
MONTH
Clock month
6
0x06
YEARS
Clock years
7
0x07
CAL_CFG1
8
0x08
TCH2
Trickle charge enable
9
0x09
CFG2
Configuration 2
DESCRIPTION
Clock hours, century, and CENT_EN bit
Calibration and configuration
Table 3. Special Function Registers
REGISTER
ADDRESS
(HEX)
REGISTER NAME
32
0x20
SF KEY 1
Special function key 1
33
0x21
SF KEY 2
Special function key 2
34
0x22
SFR
DESCRIPTION
Special function register
7.6.1 I2C Read After Backup Mode
The time keeping registers can take up to 1 second to update after the RTC switches from backup power supply
to main power supply. An I2C read of the RTC that starts before the update has completed will return the time
when the RTC enters backup mode. To ensure that the correct time is read after backup mode, the host should
wait longer than 1 second after the main supply is greater than 2.8 V and VBACK.
7.6.2 Normal Register Descriptions
7.6.2.1 SECONDS Register (address = 0x00) [reset = 0XXXXXXb]
Description – Clock seconds and STOP bit
Figure 9. SECONDS Register
7
STOP
r/w
0
UC
STOP
10_SECOND
1_SECOND
12
6
X
UC
5
10_SECOND
r/w
X
UC
4
3
2
1
0
X
UC
X
UC
1_SECOND
r/w
X
UC
X
UC
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Oscillator stop. The STOP bit is used to force the oscillator to stop oscillating. STOP is set to 0 on initial application of
power, on all subsequent power cycles STOP remains unchanged. On initial power application STOP can be written to 1
and then written to 0 to force start the oscillator.
0
Normal
1
Stop
BCD of tens of seconds. The 10_SECOND bits are the BCD representation of the number of tens of seconds on the
clock. Valid values are 0 to 5. If invalid data is written to 10_SECOND, the clock will update with invalid data in
10_SECOND until the counter rolls over; thereafter, the data in 10_SECOND is valid. Time keeping registers can take up
to 1 second to update after the RTC switches from backup power supply to main power supply.
BCD of seconds. The 1_SECOND bits are the BCD representation of the number of seconds on the clock. Valid values
are 0 to 9. If invalid data is written to 1_SECOND, the clock will update with invalid data in 1_SECOND until the counter
rolls over; thereafter, the data in 1_SECOND is valid. Time keeping registers can take up to 1 second to update after the
RTC switches from backup power supply to main power supply.
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7.6.2.2 MINUTES Register (address = 0x01) [reset = 1XXXXXXb]
Description – Clock minutes
Figure 10. MINUTES Register
7
OF
r/w
1
0
OF
10_MINUTE
1_MINUTE
6
X
UC
5
10_MINUTE
r/w
X
UC
4
3
2
1
0
X
UC
X
UC
1_MINUTE
r/w
X
UC
X
UC
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Oscillator fail flag. The OF bit is a latched flag indicating when the 32.768-kHz oscillator has dropped at least four
consecutive pulses. The OF flag is always set on initial power-up, and it can be cleared through the serial interface.
When OF is 0, no oscillator failure has been detected. When OF is 1, the oscillator fail detect circuit has detected at least
four consecutive dropped pulses.
0
No failure detected
1
Failure detected
BCD of tens of minutes. The 10_MINUTE bits are the BCD representation of the number of tens of minutes on the clock.
Valid values are 0 to 5. If invalid data is written to 10_MINUTE, the clock will update with invalid data in 10_MINUTE until
the counter rolls over; thereafter, the data in 10_MINUTE is valid. Time keeping registers can take up to 1 second to
update after the RTC switches from backup power supply to main power supply.
BCD of minutes. The 1_MINUTE bits are the BCD representation of the number of minutes on the clock. Valid values are
0 to 9. If invalid data is written to 1_MINUTE, the clock will update with invalid data in 1_MINUTE until the counter rolls
over; thereafter, the data in 1_MINUTE is valid. Time keeping registers can take up to 1 second to update after the RTC
switches from backup power supply to main power supply.
7.6.2.3 CENT_HOURS Register (address = 0x02) [reset = XXXXXXXXb]
Description – Clock hours, century, and CENT_EN bit
Figure 11. CENT_HOURS Register
7
CENT_EN
r/w
X
UC
CENT_EN
CENT
10_HOUR
1_HOUR
6
CENT
r/w
X
UC
5
4
3
2
10_HOUR
r/w
X
UC
1
0
X
UC
X
UC
1_HOUR
r/w
X
UC
X
UC
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Century enable. The CENT_EN bit enables the century timekeeping feature. If CENT_EN is set to 1, then the clock
tracks the century using the CENT bit. If CENT_EN is set to 0, the clock ignores the CENT bit.
0
Century disabled
1
Century enabled
Century. The CENT bit tracks the century when century timekeeping is enabled. The clock toggles the CENT bit when
the year count rolls from 99 to 00. Because the clock compliments the CENT bit, the user can define the meaning of
CENT (1 for current century and 0 for next century, or 0 for current century and 1 for next century).
BCD of tens of hours (24-hour format). The 10_HOUR bits are the BCD representation of the number of tens of hours on
the clock, in 24-hour format. Valid values are 0 to 2. If invalid data is written to 10_HOUR, the clock will update with
invalid data in 10_HOUR until the counter rolls over; thereafter, the data in 10_HOUR is valid. Time keeping registers can
take up to 1 second to update after the RTC switches from backup power supply to main power supply.
BCD of hours (24-hour format). The 1_HOUR bits are the BCD representation of the number of hours on the clock, in 24hour format. Valid values are 0 to 9. If invalid data is written to 1_HOUR, the clock will update with invalid data in
1_HOUR until the counter rolls over; thereafter, the data in 1_HOUR is valid. Time keeping registers can take up to 1
second to update after the RTC switches from backup power supply to main power supply.
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7.6.2.4 DAY Register (address = 0x03) [reset = 00000XXXb]
Description – Clock day
Figure 12. DAY Register
7
6
0
0
0
0
RSVD
DAY
5
RSVD
r/w
0
0
4
3
2
0
0
0
0
X
UC
1
DAY
r/w
X
UC
0
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Reserved. The RSVD bits should always be written as 0.
BCD of the day of the week. The DAY bits are the BCD representation of the day of the week. Valid values are 1 to 7
and represent the days from Sunday to Saturday. DAY updates if set to 0 until the counter rolls over; thereafter, the data
in DAY is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power
supply to main power supply.
1
Sunday
2
Monday
3
Tuesday
4
Wednesday
5
Thursday
6
Friday
7
Saturday
7.6.2.5 DATE Register (address = 0x04) [reset = 00XXXXXXb]
Description – Clock date
Figure 13. DATE Register
7
6
5
RSVD
r/w
0
0
0
0
RSVD
10_DATE
1_DATE
(1)
14
4
3
2
10_DATE
r/w
X
UC
1
0
X
UC
X
UC
1_DATE
r/w
X
UC
X
UC
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Reserved. The RSVD bits should always be written as 0.
BCD of tens of date. The 10_DATE bits are the BCD representation of the tens of date on the clock. Valid values are 0 to
3 (1). If invalid data is written to 10_DATE, the clock will update with invalid data in 10_DATE until the counter rolls over;
thereafter, the data in 10_DATE is valid. Time keeping registers can take up to 1 second to update after the RTC
switches from backup power supply to main power supply.
BCD of date. The 1_DATE bits are the BCD representation of the date on the clock. Valid values are 0 to 9 (1). If invalid
data is written to 1_DATE, the clock will update with invalid data in 1_DATE until the counter rolls over; thereafter, the
data in 1_DATE is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup
power supply to main power supply.
10_DATE and 1_DATE must form a valid date, 01 to 31, dependent on month and year.
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7.6.2.6 MONTH Register (address = 0x05) [reset = 000XXXXXb]
Description – Clock month
Figure 14. MONTH Register
7
0
0
RSVD
10_MONTH
1_MONTH
(1)
6
RSVD
r/w
0
0
5
0
0
4
10_MONTH
r/w
X
UC
3
2
1
0
X
UC
X
UC
1_MONTH
r/w
X
UC
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Reserved. The RSVD bits should always be written as 0.
BCD of tens of month. The 10_MONTH bits are the BCD representation of the tens of month on the clock. Valid values
are 0 to 1 (1). If invalid data is written to 10_MONTH, the clock will update with invalid data in 10_MONTH until the
counter rolls over; thereafter, the data in 10_MONTH is valid.
BCD of month. The 1_MONTH bits are the BCD representation of the month on the clock. Valid values are 0 to 9 (1). If
invalid data is written to 1_MONTH, the clock will update with invalid data in 1_MONTH until the counter rolls over;
thereafter, the data in 1_MONTH is valid.
10_MONTH and 1_MONTH must form a valid date, 01 to 12.
7.6.2.7 YEARS Register (address = 0x06) [reset = XXXXXXXXb]
Description – Clock year
Figure 15. YEARS Register
7
6
5
4
3
2
10_YEAR
r/w
X
UC
10_YEAR
1_YEAR
X
UC
1
0
X
UC
X
UC
1_YEAR
r/w
X
UC
X
UC
X
UC
X
UC
BIT(S)
Name
Read/Write
Initial
Cycle
BCD of tens of years. The 10_YEAR bits are the BCD representation of the tens of years on the clock. Valid values are 0
to 9. If invalid data is written to 10_YEAR, the clock will update with invalid data in 10_YEAR until the counter rolls over;
thereafter, the data in 10_YEAR is valid. Time keeping registers can take up to 1 second to update after the RTC
switches from backup power supply to main power supply.
BCD of year. The 1_YEAR bits are the BCD representation of the years on the clock. Valid values are 0 to 9. If invalid
data is written to 1_YEAR, the clock will update with invalid data in 1_YEAR until the counter rolls over; thereafter, the
data in 1_YEAR is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup
power supply to main power supply.
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7.6.2.8 CAL_CFG1 Register (address = 0x07) [reset = 10000000b]
Description – Calibration and control
Figure 16. CAL_CFG1 Register
7
OUT
r/w
1
UC
6
FT
r/w
0
UC
OUT
5
S
r/w
0
UC
4
3
0
UC
0
UC
2
CAL
r/w
0
UC
1
0
0
UC
0
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Logic output, when FT = 0. When FT is zero, the logic output of IRQ pin reflects the value of OUT.
0
IRQ is logic 0
1
IRQ is logic 1
Frequency test. The FT bit is used to enable the frequency test signal on the IRQ pin. When FT is 1, a square wave is
produced on the IRQ pin. The FTF bit in the SFR register determines the frequency of the test signal.
0
Disable
1
Enable
Calibration sign. The S bit determines the polarity of the calibration applied to the oscillator. If S is 0, then the calibration
slows the RTC. If S is 1, then the calibration speeds the RTC.
0
Slowing (+)
1
Speeding (–)
Calibration. The CAL bits along with S determine the calibration amount as shown in Table 4.
FT
S
CAL
Table 4. Calibration
CAL (DEC)
S=0
S=1
0
+0 ppm
–0 ppm
1
+2 ppm
–4 ppm
N
+N / 491520 (per minute)
–N / 245760 (per minute)
30
+61 ppm
–122 ppm
31
+63 ppm
–126 ppm
7.6.2.9 TCH2 Register (address = 0x08) [reset = 10010000b]
Description – Trickle charge TCH2 control
Figure 17. TCH2 Register
7
6
RSVD
r/w
1
UC
RSVD
TCH2
16
0
0
5
TCH2
r/w
0
0
4
3
1
1
0
UC
2
RSVD
r/w
0
UC
1
0
0
UC
0
UC
BIT(S)
Name
Read/Write
Initial
Cycle
Reserved. The RSVD bits should always be written as 0.
Trickle charge switch two. The TCH2 bit determines if the internal trickle charge switch is closed or open. All the trickle
charge switches must be closed in order for trickle charging to occur. If TCH2 is 0, then the TCH2 switch is open. If
TCH2 is 1, then the TCH2 switch is closed.
0
Open
1
Closed
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7.6.2.10 CFG2 Register (address = 0x09) [reset = 10101010b]
Description – Configuration 2
Figure 18. CFG2 Register
7
RSVD
r/w
1
1
RSVD
TCFE
6
TCFE
r/w
0
0
5
4
3
2
RSVD
r/w
1
UC
1
0
1
1
0
0
TCHE
r/w
0
UC
1
1
0
0
BIT(S)
Name
Read/Write
Initial
Cycle
Reserved. The RSVD bits should always be written as 0.
Trickle charge FET bypass. The TCFE bit is used to enable the trickle charge FET. When TCFE is 0, the FET is off.
When TCFE is 1, the FET is on.
0
Open
1
Closed
Trickle charge enable. The TCHE bits determine if the trickle charger is active. If TCHE is 0x5, then the trickle charger is
active, otherwise, the trickle charger is inactive.
TCHE
7.6.3 Special Function Registers
7.6.3.1 SF KEY 1 Register (address = 0x20) [reset = 00000000b]
Description – Special function key 1
Figure 19. SF KEY 1 Register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
SF KEY B1
r/w
0
0
SF KEY B1
0
0
0
0
0
0
BIT(S)
Name
Read/Write
Initial
Cycle
Special function access key byte 1. Reads as 0x00, and key is 0x5E.
The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to
SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the
SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2.
7.6.3.2 SF KEY 2 Register (address = 0x21) [reset = 00000000b]
Description – Special function key 2
Figure 20. SF KEY 2 Register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
SF KEY 2
r/w
0
0
SF KEY 2
0
0
0
0
0
0
BIT(S)
Name
Read/Write
Initial
Cycle
Special function access key byte 2. Reads as 0x00, and key is 0xC7.
The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to
SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the
SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2.
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7.6.3.3 SFR Register (address = 0x22) [reset = 00000000b]
Description – Special function register 1
Figure 21. SFR Register
RSVD
FTF
18
7
6
5
0
0
0
0
0
0
4
RSVD
r/w
0
0
3
2
1
0
0
0
0
0
0
0
FTF
r/w
0
0
BIT(S)
Name
Read/Write
Initial
Cycle
Reserved. The RSVD bits should always be written as 0.
Force calibration to 1 Hz. FTF allows the frequency of the calibration output to be changed from 512 Hz to 1 Hz. By
default, FTF is cleared, and the RTC outputs a 512-Hz calibration signal. Setting FTF forces the calibration signal to 1
Hz, and the calibration tracks the internal ppm adjustment. Note: The default 512-Hz calibration signal does not include
the effect of the ppm adjustment.
0
Normal 512-Hz calibration
1
1-Hz calibration
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The typical application for the bq32000 is to provide precise time and date to a system. The backup power
supply provides additional reliability by automatically switching over from the main supply when it drops under the
voltage threshold.
8.2 Typical Application
The following design is a common application of the bq32000.
V CC
bq32000
V CC
OSCI
32.768 kHz
1 µF
4.7 kΩ
OSCO
V BACK
4.7 kΩ
4.7 kΩ
IRQ
SCL
GND
SDA
Figure 22. Typical Application Schematic
8.2.1 Design Requirements
The design requirement parameters are listed in the following table.
Table 5. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Supply Voltage
VCC
3.3 V
Backup Supply
VBACK
BR1225
Crystal Oscillator
XT
32.768 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Reading From a Register
The report details the read-back of the SECONDS register. Figure 23 depicts the first condition that will be used
as a benchmark to compare the values taken from the SECONDS register in the bq32000, to the oscilloscope’s
internal PC time. In this example two modes of operation are demonstrated.
Condition 1. The main power supply, VCC, is greater than the backup power supply, VBACK, and the internal
reference voltage, VREF. In this mode, the device's internal registers are fully operational with READ and WRITE
access. Analyzing Figure 23, the known register values are compared to the system clock; in this case, the PC
clock which is shown at the bottom of the screen capture.
The bq32000 during this condition is reading back [101][0010]= [5][2], which corresponds to 52 seconds at
PC time of 2:22:43 PM.
Condition 2. VCC is now lowered to 2 V (VBACK > VCC). In this mode, the I2C communications are halted.
However, the internal time keeping registers maintain full functional operation and accuracy which will be
available to be reliably read by the controller 1 second after the RTC switches from VBACK to VCC supply.
Condition 3. During this final test condition, the RTC is restored to operate from the main power supply and I2C
communications are now fully functional.
Figure 24 demonstrates a read-back value from the SECONDS register of [100][0101]= [4][5], or 45 seconds
at PC time of 2:23:36 PM. This proves that the bq32000 managed to accurately maintain the time keeping
registers functional while the VCC dropped below VBACK.
8.2.2.2 Leap Year Compensation
The BQ32000 classifies a leap year as any year that is evenly divisible by 4. Using this rule allows for reliable
leap year compensation until 2100. Years that fall outside this rule will need to be compensated for by the
external controller.
8.2.2.3 Utilizing the Backup Supply
In order for the bq32000 to achieve a low backup supply current as specified in the Electrical Characteristics, the
VCC pin must be initialized after every total power loss situation. Initialization Is achieved by powering on VCC with
a voltage between 3 to 3.6 V for at least 1 ms immediately after the backup supply is connected. If the VCC is not
powered on while connecting the backup supply, then the expected leakage current from VBACK will be much
greater than specified.
20
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8.2.3 Application Curves
Figure 23. Master and Slave I2C Communication for the SECONDS Register
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Figure 24. Master and Slave I2C Communication for the SECONDS Register After Recovering From the
Backup Supply
22
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9 Power Supply Recommendations
The bq32000 is designed to operate from an input voltage supply, VCC, range between 3.0 and 3.6 V. The user
must place a minimum of 1-µF ceramic bypass capacitor rated for at least the maximum voltage as close as
possible to VCC and GND pin.
10 Layout
10.1 Layout Guidelines
The VCC pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a minimum
recommended value of 1-µF. This capacitor should be placed as close to the VCC and GND pins as possible with
thick trace or ground plane connection to the device GND pin.
Locate the 32.768-kHz crystal oscillator as close as possible to the OSCI and OSCO pins. This will minimize
stray capacitance.
10.2 Layout Example
1 µF
____
IRQ
VBACK
SCL
GND
SDA
4.7 kΩ
OSCO
4.7 kΩ
VCC
4.7 kΩ
OSCI
0.22F
Figure 25. Recommended PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
BQ32000D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
32000
BQ32000DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
32000
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ32000DR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ32000DR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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