BQ40Z50-R2
BQ40Z50-R2
SLUSCS4C – JUNE 2017 – REVISED
APRIL 2021
SLUSCS4C – JUNE 2017 – REVISED APRIL 2021
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BQ40Z50-R2 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager
1 Features
3 Description
•
The BQ40Z50-R2 device, incorporating patented
Impedance Track™ technology, is a fully integrated,
single-chip, pack-based solution that provides a rich
array of features for gas gauging, protection, and
authentication for 1-series, 2-series, 3-series, and 4series cell Li-ion and Li-polymer battery packs.
•
•
•
•
•
PART NUMBER
BQ40Z50-R2
PACKAGE
BODY SIZE (NOM)
VQFN (32)
4.00 mm × 4.00 mm
VC4
PACK
VCC
DSG
CHG
BAT
PCHG
PACK +
PTC
•
•
•
Device Information
FUSE
•
Using its integrated high-performance analog
peripherals, the BQ40Z50-R2 device measures and
maintains an accurate record of available capacity,
voltage, current, temperature, and other critical
parameters in Li-ion or Li-polymer batteries, and
reports this information to the system host controller
over an SMBus v1.1 compatible interface.
LEDCNTLA
LEDCNTLB
LEDCNTLC
VC3
OUT
VDD
GND
VC3
nd
•
•
•
•
2 level
protector
•
Fully integrated 1-series, 2-series, 3-series, and
4-series Li-ion or Li-polymer cell battery pack
manager and protection
Next-generation patented Impedance Track™
technology accurately measures available charge
in Li-ion and Li-polymer batteries
High-side N-CH protection FET drive
Integrated cell balancing while charging or at rest
Suitable for batteries between 100 mAh and 29 Ah
Full array of programmable protection features
– Voltage
– Current
– Temperature
– Charge timeout
– CHG/DSG FETs
– AFE
Sophisticated charge algorithms
– JEITA
– Enhanced charging
– Adaptive charging
– Cell balancing
Supports TURBO Mode 2.0
Supports battery trip point (BTP)
Diagnostic lifetime data monitor and black box
recorder
LED display
Supports two-wire SMBus v1.1 interface
SHA-1 authentication
IATA support
Compact package: 32-lead QFN (RSM)
VC2
Cell 3
Cell 2
VC2
DISP
VC1
SMBD
SMBC
PBI
VSS SRP SRN TS1 TS2 TS3 TS4 BTP PRES
VC1
Cell 1
Tablets
Drones
UPS/battery backup systems
Medical equipment
Handheld vacuum cleaners and vacuum robots
SMBC
PRES
BTP
2 Applications
•
•
•
•
•
SMBD
PACK–
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................3
6.1 Pin Equivalent Diagrams.............................................5
7 Specifications.................................................................. 8
7.1 Absolute Maximum Ratings........................................ 8
7.2 ESD Ratings............................................................... 8
7.3 Recommended Operating Conditions.........................8
7.4 Thermal Information....................................................9
7.5 Supply Current............................................................ 9
7.6 Power Supply Control................................................. 9
7.7 AFE Power-On Reset............................................... 10
7.8 AFE Watchdog Reset and Wake Timer.................... 10
7.9 Current Wake Comparator........................................ 10
7.10 VC1, VC2, VC3, VC4, BAT, PACK.......................... 11
7.11 SMBD, SMBC..........................................................11
7.12 PRES, BTP_INT, DISP ...........................................11
7.13 LEDCNTLA, LEDCNTLB, LEDCNTLC................... 12
7.14 Coulomb Counter....................................................12
7.15 CC Digital Filter.......................................................12
7.16 ADC........................................................................ 12
7.17 ADC Digital Filter.................................................... 13
7.18 CHG, DSG FET Drive............................................. 13
7.19 PCHG FET Drive.................................................... 14
7.20 FUSE Drive............................................................. 14
7.21 Internal Temperature Sensor.................................. 14
7.22 TS1, TS2, TS3, TS4................................................15
7.23 PTC, PTCEN...........................................................15
7.24 Internal 1.8-V LDO.................................................. 15
7.25 High-Frequency Oscillator...................................... 15
7.26 Low-Frequency Oscillator....................................... 16
7.27 Voltage Reference 1............................................... 16
7.28 Voltage Reference 2............................................... 16
7.29 Instruction Flash......................................................16
7.30 Data Flash...............................................................17
7.31 OLD, SCC, SCD1, SCD2 Current Protection
Thresholds...................................................................17
7.32 Timing Requirements: OLD, SCC, SCD1,
SCD2 Current Protection Timing................................. 18
7.33 Timing Requirements: SMBus................................ 18
7.34 Timing Requirements: SMBus XL........................... 19
7.35 Typical Characteristics............................................ 20
8 Detailed Description......................................................24
8.1 Overview................................................................... 24
8.2 Functional Block Diagram......................................... 24
8.3 Feature Description...................................................25
8.4 Device Functional Modes..........................................28
9 Application and Implementation.................................. 29
9.1 Application Information............................................. 29
9.2 Typical Applications.................................................. 30
10 Power Supply Recommendations..............................41
11 Layout........................................................................... 42
11.1 Layout Guidelines................................................... 42
11.2 Layout Example...................................................... 44
12 Device and Documentation Support..........................46
12.1 Third-Party Products Disclaimer............................. 46
12.2 Documentation Support.......................................... 46
12.3 Support Resources................................................. 46
12.4 Trademarks............................................................. 46
12.5 Electrostatic Discharge Caution..............................46
12.6 Glossary..................................................................46
13 Mechanical, Packaging, and Orderable
Information.................................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2018) to Revision C (April 2021)
Page
• Changed all occurrences of OCD to OLD throughout the data sheet ................................................................1
Changes from Revision A (October 2017) to Revision B (July 2018)
Page
• Changed Pin Configuration and Functions ........................................................................................................ 5
• Changed System Present ................................................................................................................................34
2
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5 Description (continued)
The BQ40Z50-R2 device supports TURBO Mode 2.0 by providing the available max power and max current to
the host system. The device also supports Battery Trip Point to send a BTP interrupt signal to the host system at
the preset state of charge thresholds.
The BQ40Z50-R2 provides software-based 1st- and 2nd-level safety protection against overvoltage,
undervoltage, overcurrent, short-circuit current, overload, and overtemperature conditions, as well as other packand cell-related faults.
SHA-1 authentication, with secure memory for authentication keys, enables identification of genuine battery
packs.
The compact 32-lead QFN package minimizes solution cost and size for smart batteries while providing
maximum functionality and safety for battery gauging applications.
BAT
CHG
PCHG
NC
DSG
PACK
VCC
FUSE
32
31
30
29
28
27
26
25
6 Pin Configuration and Functions
PBI
1
24
PTCEN
VC4
2
23
PTC
VC3
3
22
LEDCNTLC
VC2
4
21
LEDCNTLB
VC1
5
20
LEDCNTLA
SRN
6
19
SMBC
NC
7
18
SMBD
SRP
8
17
DISP
Thermal
9
10
11
12
13
14
15
16
VSS
TS1
TS2
TS3
TS4
NC
BTP_INT
PRES or SHUTDN
Pad
Not to scale
Table 6-1. Pin Functions
PIN NUMBER
1
2
3
4
5
PIN NAME
PBI
VC4
VC3
VC2
VC1
TYPE
P(1)
DESCRIPTION
Power supply backup input pin. Connect to the 2.2-µF capacitor to VSS.
IA
Sense voltage input pin for the most positive cell, and balance current input
for the most positive cell. Should be connected to the positive terminal of the
fourth cell from the bottom of the stack with a 100-Ω series resistor and a
0.1-μF capacitor to VC3. If not used, connect to VC3.
IA
Sense voltage input pin for the third-most positive cell, balance current input
for the third-most positive cell, and return balance current for the most
positive cell. Should be connected to the positive terminal of the third cell from
the bottom of the stack with a 100-Ω series resistor and a 0.1-μF capacitor to
VC2. If not used, connect to VC2.
IA
Sense voltage input pin for the second-most positive cell, balance current
input for the second-most positive cell, and return balance current for the
third-most positive cell. Should be connected to the positive terminal of the
second cell from the bottom of the stack with a 100-Ω series resistor and a
0.1-μF capacitor to VC1. If not used, connect to VC1.
IA
Sense voltage input pin for the least positive cell, balance current input for
the least positive cell, and return balance current for the second-most positive
cell. Should be connected to the positive terminal of the first cell from the
bottom of the stack with a 100-Ω series resistor and a 0.1-μF capacitor to
VSS.
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Table 6-1. Pin Functions (continued)
PIN NUMBER
6
SRN
7
NC
4
TYPE
I
—
DESCRIPTION
Analog input pin connected to the internal coulomb counter peripheral for
integrating a small voltage between SRP and SRN where SRP is the top of
the sense resistor.
Not internally connected. It is okay to leave floating or to tie to VSS.
8
SRP
I
Analog input pin connected to the internal coulomb counter peripheral for
integrating a small voltage between SRP and SRN where SRP is the top of
the sense resistor.
9
VSS
P
Device ground
10
TS1
IA
Temperature sensor 1 thermistor input pin. Connect to thermistor-1. If not
used, connect directly to VSS and configure data flash accordingly.
11
TS2
IA
Temperature sensor 2 thermistor input pin. Connect to thermistor-2. If not
used, connect directly to VSS and configure data flash accordingly.
12
TS3
IA
Temperature sensor 3 thermistor input pin. Connect to thermistor-3. If not
used, connect directly to VSS and configure data flash accordingly.
13
TS4
IA
Temperature sensor 4 thermistor input pin. Connect to thermistor-4. If not
used, connect directly to VSS and configure data flash accordingly.
14
NC
—
Not internally connected. It is okay to leave floating or to tie to VSS.
15
BTP_INT
O
Battery Trip Point (BTP) interrupt output. If not used, connect directly to VSS.
I
Host system present input for removable battery pack or emergency system
shutdown input for embedded pack. A pullup is not required for this pin. If not
used, connect directly to VSS.
16
(1)
PIN NAME
PRES or SHUTDN
17
DISP
—
18
SMBD
I/OD
SMBus data pin
Display control for LEDs. If not used, connect directly to VSS.
19
SMBC
I/OD
SMBus clock pin
20
LEDCNTLA
—
LED display segment that drives the external LEDs depending on the
firmware configuration. If LEDs are not used, these pins can be left floating or
connected to VSS through a 20-kΩ resistor.
21
LEDCNTLB
—
LED display segment that drives the external LEDs depending on the
firmware configuration. If LEDs are not used, these pins can be left floating or
connected to VSS through a 20-kΩ resistor.
22
LEDCNTLC
—
LED display segment that drives the external LEDs depending on the
firmware configuration. If LEDs are not used, these pins can be left floating or
connected to VSS through a 20-kΩ resistor.
23
PTC
IA
Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to
VSS.
24
PTCEN
IA
Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect
both PTC and PTCEN to VSS.
25
FUSE
O
Fuse drive output pin. If not used, connect directly to VSS.
26
VCC
P
Secondary power supply input
27
PACK
IA
Pack sense input pin
28
DSG
O
NMOS Discharge FET drive output pin. If not used, it can be left floating or
connected to VSS through a 20-kΩ resistor.
29
NC
—
Not internally connected. It is okay to leave floating or to tie to VSS.
30
PCHG
O
PMOS Precharge FET drive output pin. If not used, it can be left floating or
connected to VSS through a 20-kΩ resistor.
31
CHG
O
NMOS Charge FET drive output pin. If not used, it can be left floating or
connected to VSS through a 20-kΩ resistor.
32
BAT
P
Primary power supply input pin
P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
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6.1 Pin Equivalent Diagrams
VC4
BAT
VCC
CDEN4
PACK
VC3
+
–
3.1 V
BATDET
ENVCC
CDEN3
PACK
Detector
VC2
PACKDET
PBI
Reference
System
Shutdown
Latch
1.8 V
Domain
VC1
BAT
Control
Power Supply Control
ADC
CDEN2
SHOUT
ENBAT
ADC Mux
SHUTDOWN
CDEN1
Cell Balancing
VCC
CHGEN
BAT
2 kΩ
CHG
Pump
CHG
8 kΩ
2 kΩ
PCHG
CHGOFF
PCHGEN
Pre-Charge Drive
PACK
BAT
DSGEN
BAT
DSG
Pump
ZVCD
2 kΩ
DSG
CHGEN
BAT
DSGOFF
CHG
Pump
VCC
ZVCHGEN
CHG, DSG Drive
Zero-Volt Charge
Figure 6-1. Pin Equivalent Diagram 1
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1.8 V
ADTHx
BAT
FUSEWKPUP
18 kΩ
2 kΩ
ADC Mux
TS1,2,3,4
ADC
FUSEEN
150 nA
2 kΩ
FUSE
1.8 V
1.8 V
100 kΩ
FUSEDIG
RCWKPUP
RCPUP
FUSE Drive
1 kΩ
RCIN
RCOUT
SMBCIN
100 kΩ
SMBC
Thermistor Inputs
SMBCOUT
SMBCEN
1 MΩ
PBI
100 kΩ
SMBDIN
RHOEN
SMBDOUT
10 kΩ
PRES
SMBD
SMBDEN
1 MΩ
SMBus Interface
RHOUT
100 kΩ
RHIN
High-Voltage GPIO
BAT
RLOEN
LED1, 2, 3
22.5 mA
RLOUT
100 kΩ
RLIN
LED Drive
Figure 6-2. Pin Equivalent Diagram 2
6
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10 Ω
VC4
CHANx
Φ2
3.8 kΩ
1.9 MΩ
SRP
ADC Mux
Φ1
ADC
Φ2
3.8 kΩ
0.1 MΩ
SRN
Comparator
Array
Φ1
Φ2
10 Ω
100 Ω
PACK
Φ1
Φ2
CHANx
100 Ω
Coulomb
Counter
Φ1
1.9 MΩ
ADC Mux
ADC
0.1 MΩ
VC4 and PACK Dividers
OLD , SCC, SCD Comparators and Coulomb Counter
Figure 6-3. Pin Equivalent Diagram 3
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7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
Supply voltage range,
VCC
Input voltage range, VIN
Output voltage range,
VO
BAT, VCC, PBI
MIN
MAX
UNIT
–0.3
30
V
PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP
–0.3
30
V
TS1, TS2, TS3, TS4
–0.3
VREG + 0.3
V
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC
–0.3
VBAT + 0.3
V
SRP, SRN
–0.3
0.3
V
VC4
VC3 – 0.3
VC3 + 8.5, or
VSS + 30
V
VC3
VC2 – 0.3
VC2 + 8.5, or
VSS + 30
V
VC2
VC1 – 0.3
VC1 + 8.5, or
VSS + 30
V
VC1
VSS – 0.3
VSS + 8.5, or
VSS + 30
V
CHG, DSG
–0.3
32
PCHG, FUSE
–0.3
30
V
50
mA
Maximum VSS current, ISS
Storage temperature, TSTG
–65
Lead temperature (soldering, 10 s), TSOLDER
(1)
150
°C
300
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
8
VCC
Supply voltage
BAT, VCC, PBI
VSHUTDOWN–
Shutdown voltage
VPACK < VSHUTDOWN –
VSHUTDOWN+
Start-up voltage
VPACK > VSHUTDOWN– + VHYS
VHYS
Shutdown voltage
hysteresis
VSHUTDOWN+ – VSHUTDOWN–
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NOM
2.2
MAX
UNIT
26
V
1.8
2.0
2.2
V
2.05
2.25
2.45
V
250
mV
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7.3 Recommended Operating Conditions (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX
PACK, SMBC, SMBD, PRES, BTP_IN, DISP
VIN
Input voltage range
UNIT
26
TS1, TS2, TS3, TS4
VREG
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC
VBAT
SRP, SRN
–0.2
0.2
VC4
VVC3
VVC3 + 5
VC3
VVC2
VVC2 + 5
VC2
VVC1
VVC1 + 5
VC1
VVSS
VVSS + 5
VO
Output voltage
range
CPBI
External PBI
capacitor
2.2
TOPR
Operating
temperature
–40
CHG, DSG, PCHG, FUSE
26
V
V
µF
85
°C
7.4 Thermal Information
BQ40Z50-R2
THERMAL
METRIC(1)
RSM (QFN)
UNIT
32 PINS
RθJA, High K
Junction-to-ambient thermal resistance
47.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
40.3
°C/W
RθJB
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
14.4
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
3.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Supply Current
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 20 V (unless otherwise noted)
PARAMETER
INORMAL
NORMAL mode
ISLEEP
SLEEP mode
ISHUTDOWN
SHUTDOWN mode
TEST CONDITIONS
MIN
CHG on. DSG on, no Flash write
TYP
MAX
336
CHG off, DSG on, no SBS communication
75
CHG off, DSG off, no SBS communication
52
UNIT
µA
µA
1.6
µA
7.6 Power Supply Control
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSWITCHOVER–
BAT to VCC
V
< VSWITCHOVER–
switchover voltage BAT
VSWITCHOVER+
VCC to BAT
V
> VSWITCHOVER– + VHYS
switchover voltage BAT
MIN
TYP
MAX
UNIT
1.95
2.1
2.2
V
2.9
3.1
3.25
V
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7.6 Power Supply Control (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VHYS
Switchover
VSWITCHOVER+ – VSWITCHOVER–
voltage hysteresis
ILKG
Input Leakage
current
MIN
TYP
MAX
1000
UNIT
mV
BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V
1
PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V
1
BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK =
0 V, PBI = 25 V
1
µA
7.7 AFE Power-On Reset
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREGIT–
Negative-going
voltage input
VREG
VHYS
Power-on reset
hysteresis
VREGIT+ – VREGIT–
tRST
Power-on reset
time
MIN
TYP
MAX
UNIT
1.51
1.55
1.59
V
70
100
130
mV
200
300
400
µs
7.8 AFE Watchdog Reset and Wake Timer
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
AFE watchdog
timeout
tWDT
tWAKE
AFE wake timer
tFETOFF
FET off delay after
reset
TEST CONDITIONS
MIN
TYP
MAX
tWDT = 500
372
500
628
tWDT = 1000
744
1000
1256
tWDT = 2000
1488
2000
2512
tWDT = 4000
2976
4000
5024
tWAKE = 250
186
250
314
tWAKE = 500
372
500
628
tWAKE = 1000
744
1000
1256
tWAKE = 512
1488
2000
2512
409
512
614
tFETOFF = 512
UNIT
ms
ms
ms
7.9 Current Wake Comparator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.3
±0.625
VWAKE = ±1.25 mV
±0.6
±1.25
±1.8
VWAKE = ±2.5 mV
±1.2
±2.5
±3.6
VWAKE = ±5 mV
±2.4
±5.0
±7.2
VWAKE = ±0.625 mV
VWAKE
Wake voltage
threshold
VWAKE(DRIFT)
Temperature drift of
VWAKE accuracy
tWAKE
Time from
application of
current to wake
interrupt
10
MAX UNIT
±0.9
0.5%
°C
700
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7.9 Current Wake Comparator (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
tWAKE(SU)
TEST CONDITIONS
MIN
Wake comparator
startup time
TYP
MAX UNIT
500
1000
µs
7.10 VC1, VC2, VC3, VC4, BAT, PACK
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
K
Scaling factor
MIN
TYP
MAX
0.1980
0.2000
0.2020
BAT–VSS, PACK–VSS
0.049
0.050
0.051
VREF2
0.490
0.500
0.510
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
–0.2
5
BAT–VSS, PACK–VSS
–0.2
20
VIN
Input voltage range
ILKG
Input leakage current
VC1, VC2, VC3, VC4, cell balancing off, cell detach
detection off, ADC multiplexer off
RCB
Internal cell balance
resistance
RDS(ON) for internal FET switch at 2 V < VDS < 4 V
ICD
Internal cell detach
check current
VCx > VSS + 0.8 V
30
50
UNIT
—
V
1
µA
200
Ω
70
µA
7.11 SMBD, SMBC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input voltage high
SMBC, SMBD, VREG = 1.8 V
VIL
Input voltage low
SMBC, SMBD, VREG = 1.8 V
1.3
0.8
V
V
VOL
Output low voltage
SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA
0.4
V
CIN
Input capacitance
ILKG
Input leakage current
1
µA
RPD
Pulldown resistance
1.3
MΩ
5
0.7
1.0
pF
7.12 PRES, BTP_INT, DISP
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VIH
High-level input
VIL
Low-level input
VOH
Output voltage high
VOL
Output voltage low
CIN
Input capacitance
ILKG
Input leakage current
RO
Output reverse
resistance
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.3
V
0.55
VBAT > 5.5 V, IOH = –0 µA
3.5
VBAT > 5.5 V, IOH = –10 µA
1.8
V
IOL = 1.5 mA
0.4
V
1
µA
5
Between PRES or BTP_INT or DISP and PBI
8
V
pF
kΩ
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7.13 LEDCNTLA, LEDCNTLB, LEDCNTLC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VIH
High-level input
VIL
Low-level input
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.45
V
0.55
VOH
Output voltage high
VBAT > 3.0 V, IOH = –22.5 mA
VOL
Output voltage low
IOL = 1.5 mA
ISC
High level output
current protection
IOL
Low level output
current
VBAT > 3.0 V, VOH = 0.4 V
ILEDCNTLx
Current matching
between LEDCNTLx
VBAT = VLEDCNTLx + 2.5 V
CIN
Input capacitance
ILKG
Input leakage current
fLEDCNTLx
Frequency of LED
pattern
V
VBAT –
1.6
V
0.4
V
–30
–45
–6 0
mA
15.75
22.5
29.25
mA
±1%
20
pF
1
124
µA
Hz
7.14 Coulomb Counter
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input voltage range
Full scale range
Integral nonlinearity(1)
16-bit, best fit over input voltage range
Offset error
16-bit, Post-calibration
Offset error drift
15-bit + sign, Post-calibration
Gain error
15-bit + sign, over input voltage range
Gain error drift
15-bit + sign, over input voltage range
Effective input resistance
(1)
MIN
TYP
MAX
UNIT
–0.1
0.1
V
–VREF1/10
VREF1/10
V
±5.2
±22.3
±5
±10
µV
0.2
0.3
µV/°C
±0.2%
±0.8%
150
2.5
LSB
FSR
PPM/°C
MΩ
1 LSB = VREF1/(10 × 2N) = 1.215/(10 × 215) = 3.71 µV
7.15 CC Digital Filter
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Conversion time
Single conversion
Effective resolution
Single conversion
MIN
TYP
MAX UNIT
250
ms
15
Bits
7.16 ADC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Input voltage range
Full scale range
12
TEST CONDITIONS
MIN
TYP
MAX UNIT
Internal reference (VREF1)
–0.2
1
External reference (VREG)
–0.2
0.8 × VREG
VFS = VREF1 or VREG
–VFS
VFS
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7.16 ADC (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Integral nonlinearity(1)
Offset error(2)
TEST CONDITIONS
TYP
MAX UNIT
±6.6
16-bit, best fit, –0.2 V to –0.1 V
Offset error drift
16-bit, Post-calibration, VFS = VREF1
16-bit, –0.1 V to 0.8 × VFS
Gain error drift
16-bit, –0.1 V to 0.8 × VFS
LSB
±13.1
16-bit, Post-calibration, VFS = VREF1
Gain error
±67
±157
0.6
3
±0.2%
±0.8%
150
Effective input resistance
(1)
(2)
MIN
16-bit, best fit, –0.1 V to 0.8 × VREF1
µV
µV/°C
FSR
PPM/°C
8
MΩ
1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when tCONV = 31.25 ms)
For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC
multiplexer scaling factor (K)).
7.17 ADC Digital Filter
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Conversion time
Resolution
Effective resolution
TEST CONDITIONS
MIN
TYP
Single conversion
31.25
Single conversion
15.63
Single conversion
7.81
Single conversion
1.95
No missing codes
16
With sign, tCONV = 31.25 ms
14
15
MAX UNIT
ms
Bits
With sign, tCONV = 15.63 ms
13
14
With sign, tCONV = 7.81 ms
11
12
With sign, tCONV = 1.95 ms
9
10
Bits
7.18 CHG, DSG FET Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Output voltage
ratio
V(FETON)
V(FETOFF)
tR
TEST CONDITIONS
MIN
TYP
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10
MΩ between PACK and DSG
2.133
2.333
2.433
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10
MΩ between BAT and CHG
2.133
2.333
2.433
10.5
11.5
12
10.5
11.5
12
VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
PACK and DSG, VBAT = 18 V
Output voltage,
CHG and DSG on VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
BAT and CHG, VBAT = 18 V
VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and
Output voltage,
DSG
CHG and DSG off
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG
Rise time
MAX UNIT
—
V
–0.4
0.4
–0.4
0.4
VDSG from 0% to 35% VDSG (ON)(TYP), VBAT ≥ 2.2 V, CL =
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and CL, 10 MΩ between PACK and DSG
200
VCHG from 0% to 35% VCHG (ON)(TYP), VBAT ≥ 2.2 V, CL =
4.7 nF between CHG and BAT, 5.1 kΩ between CHG and
CL, 10 MΩ between BAT and CHG
200
V
500
µs
500
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7.18 CHG, DSG FET Drive (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
tF
TEST CONDITIONS
Fall time
MIN
TYP
VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between DSG and PACK, 5.1 kΩ between DSG and CL,
10 MΩ between PACK and DSG
40
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between CHG and BAT, 5.1 kΩ between CHG and CL, 10
MΩ between BAT and CHG
40
MAX UNIT
300
µs
200
7.19 PCHG FET Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(FETON)
Output voltage,
PCHG on
VPCHG(ON) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
V(FETOFF)
Output voltage,
PCHG off
VPCHG(OFF) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
tR
Rise time
VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥ 8 V, CL =
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
tF
Fall time
VPCHG from 90% to 10% VPCHG(ON)(TYP), VCC ≥ 8 V, CL =
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
MIN
TYP
6
7
MAX UNIT
8
V
0.4
V
40
200
µs
40
200
µs
–0.4
7.20 FUSE Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
Output voltage
high
VIH
High-level input
IAFEFUSE(PU)
Internal pullup
current
RAFEFUSE
Output impedance
CIN
Input capacitance
tDELAY
Fuse trip detection
delay
tRISE
Fuse output rise
time
MIN
TYP
VBAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA
6
7
VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA
VBAT – 0.1
1.5
VBAT ≥ 8 V, VAFEFUSE = VSS
2
MAX UNIT
8.65
VBAT
2.0
2.5
V
150
330
nA
2.6
3.2
kΩ
5
128
VBAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V
V
5
pF
256
µs
20
µs
7.21 Internal Temperature Sensor
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VTEMP
14
TEST CONDITIONS
Internal
VTEMPP
temperature
sensor voltage drift VTEMPP – VTEMPN, assured by design
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MIN
TYP
MAX UNIT
–1.9
–2.0
–2.1
0.177
0.178
0.179
mV/°C
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7.22 TS1, TS2, TS3, TS4
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TS1, TS2, TS3, TS4, VBIAS = VREF1
–0.2
0.8 × VREF1
TS1, TS2, TS3, TS4, VBIAS = VREG
–0.2
0.8 × VREG
VIN
Input voltage
range
RNTC(PU)
Internal pullup
resistance
TS1, TS2, TS3, TS4
14.4
18
21.6
kΩ
RNTC(DRIFT)
Resistance drift
over
TS1, TS2, TS3, TS4
temperature
–360
–280
–200
PPM/°C
V
7.23 PTC, PTCEN
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.2
2.5
3.95
MΩ
RPTC(TRIP)
PTC trip
resistance
VPTC(TRIP)
PTC trip voltage
VPTC(TRIP) = VPTCEN – VPTC
200
500
890
mV
IPTC
Internal PTC
current bias
TA = –40°C to 110°C
200
290
350
nA
tPTC(DELAY)
PTC delay time
TA = –40°C to 110°C
40
80
145
ms
7.24 Internal 1.8-V LDO
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.6
1.8
2.0
VREG
Regulator voltage
ΔVO(TEMP)
Regulator output
over temperature
ΔVREG/ΔTA, IREG = 10 mA
ΔVO(LINE)
Line regulation
ΔVREG/ΔVBAT, VBAT = 10 mA
–0 .6%
0.5%
ΔVO(LOAD)
Load regulation
ΔVREG/ΔIREG, IREG = 0 mA to 10 mA
–1.5%
1.5%
IREG
Regulator output
current limit
VREG = 0.9 × VREG(NOM), VIN > 2.2 V
20
ISC
Regulator shortcircuit current limit
VREG = 0 × VREG(NOM)
25
PSRRREG
Power supply
rejection ratio
ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz
VSLEW
Slew rate
enhancement
voltage threshold
VREG
UNIT
V
±0.25%
1.58
mA
40
55
mA
40
dB
1.65
V
7.25 High-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
fHFO
fHFO(ERR)
TEST CONDITIONS
MIN
TYP
TA = –20°C to 70°C, includes frequency drift
–2.5%
±0.25%
2.5%
TA = –40°C to 85°C, includes frequency drift
–3.5%
±0.25%
3.5%
Operating frequency
Frequency error
MAX UNIT
16.78
MHz
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7.25 High-Frequency Oscillator (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
tHFO(SU)
TEST CONDITIONS
Start-up time
MIN
TYP
TA = –20°C to 85°C, oscillator frequency within +/–
3% of nominal
oscillator frequency within +/–3% of nominal
MAX UNIT
4
ms
100
µs
7.26 Low-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFO
Operating frequency
fLFO(ERR)
Frequency error
fLFO(FAIL)
Failure detection
frequency
MIN
TYP
MAX UNIT
262.144
kHz
TA = –20°C to 70°C, includes frequency drift
–1.5%
±0.25%
1.5%
TA = –40°C to 85°C, includes frequency drift
–2.5
±0.25
2.5
30
80
100
kHz
7.27 Voltage Reference 1
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF1
Internal reference
voltage
VREF1(DRIFT)
Internal reference
voltage drift
TA = 25°C, after trim
MIN
TYP
1.21
1.215
TA = 0°C to 60°C, after trim
±50
TA = –40°C to 85°C, after trim
±80
MAX UNIT
1.22
V
PPM/°C
7.28 Voltage Reference 2
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF2
Internal reference
voltage
VREF2(DRIFT)
Internal reference
voltage drift
TA = 25°C, after trim
MIN
TYP
1.22
1.225
TA = 0°C to 60°C, after trim
±50
TA = –40°C to 85°C, after trim
±80
MAX UNIT
1.23
V
PPM/°C
7.29 Instruction Flash
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Data retention
Flash programming
write cycles
tPROGWORD
Word programming
time
MIN
TYP
MAX UNIT
10
Years
1000
Cycles
TA = –40°C to 85°C
40
µs
tMASSERASE
Mass-erase time
TA = –40°C to 85°C
40
ms
tPAGEERASE
Page-erase time
TA = –40°C to 85°C
40
ms
IFLASHREAD
Flash-read current
TA = –40°C to 85°C
2
mA
IFLASHWRITE
Flash-write current
TA = –40°C to 85°C
5
mA
16
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7.29 Instruction Flash (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
IFLASHERASE
TEST CONDITIONS
Flash-erase current
MIN
TYP
TA = –40°C to 85°C
MAX UNIT
15
mA
7.30 Data Flash
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Data retention
Flash programming
write cycles
MIN
TYP
MAX UNIT
10
Years
20000
Cycles
tPROGWORD
Word programming time TA = –40°C to 85°C
40
µs
tMASSERASE
Mass-erase time
TA = –40°C to 85°C
40
ms
tPAGEERASE
Page-erase time
TA = –40°C to 85°C
40
ms
IFLASHREAD
Flash-read current
TA = –40°C to 85°C
1
mA
IFLASHWRITE
Flash-write current
TA = –40°C to 85°C
5
mA
IFLASHERASE
Flash-erase current
TA = –40°C to 85°C
15
mA
7.31 OLD, SCC, SCD1, SCD2 Current Protection Thresholds
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
VOLD
ΔVOLD
VSCC
ΔVSCC
VSCD1
ΔVSCD1
VSCD2
TEST CONDITIONS
VOLD = VSRP – VSRN, AFE PROTECTION
OLD detection threshold CONTROL[RSNS] = 1
voltage range
VOLD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
MIN
–100
–8.3
–50
mV
–5.56
mV
–2.78
44.4
200
22.2
100
mV
VSCC = VSRP – VSRN, AFE PROTECTION
SCC detection threshold CONTROL[RSNS] = 1
voltage program step
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
SCD1 detection
threshold voltage range
SCD1 detection
threshold voltage
program step
SCD2 detection
threshold voltage range
MAX UNIT
–16.6
VOLD = VSRP – VSRN, AFE PROTECTION
OLD detection threshold CONTROL[RSNS] = 1
voltage program step
VOLD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCC = VSRP – VSRN, AFE PROTECTION
SCC detection threshold CONTROL[RSNS] = 1
voltage range
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
TYP
22.2
mV
11.1
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–44.4
–200
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–22.2
–100
mV
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–22.2
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–11.1
mV
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–44.4
–200
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–22.2
–100
mV
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7.31 OLD, SCC, SCD1, SCD2 Current Protection Thresholds (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
ΔVSCD2
TEST CONDITIONS
SCD2 detection
threshold voltage
program step
VOFFSET
OLD, SCC, and SCDx
offset error
VSCALE
OLD, SCC, and SCDx
scale error
MIN
TYP
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–22.2
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–11.1
Post-trim
No trim
Post-trim
MAX UNIT
mV
–2.5
2.5
–10%
10%
–5%
5%
mV
—
7.32 Timing Requirements: OLD, SCC, SCD1, SCD2 Current Protection Timing
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX UNIT
tOLD
OLD detection
delay time
ΔtOLD
OLD detection
delay time
program step
tSCC
SCC detection
delay time
ΔtSCC
SCC detection
delay time
program step
tSCD1
SCD1 detection
delay time
SCD1 detection
delay time
program step
AFE PROTECTION CONTROL[SCDDx2] = 0
61
ΔtSCD1
AFE PROTECTION CONTROL[SCDDx2] = 1
121
tSCD2
SCD2 detection
delay time
AFE PROTECTION CONTROL[SCDDx2] = 0
0
458
AFE PROTECTION CONTROL[SCDDx2] = 1
0
915
SCD2 detection
delay time
program step
AFE PROTECTION CONTROL[SCDDx2] = 0
30.5
ΔtSCD2
AFE PROTECTION CONTROL[SCDDx2] = 1
61
tDETECT
Current fault
detect time
VSRP – VSRN = VT – 3 mV for OLD, SCD1, and SC2,
VSRP – VSRN = VT + 3 mV for SCC
tACC
Current fault delay
Max delay setting
time accuracy
1
31
2
0
ms
915
61
µs
µs
AFE PROTECTION CONTROL[SCDDx2] = 0
0
915
AFE PROTECTION CONTROL[SCDDx2] = 1
0
1850
µs
µs
µs
µs
160
–10%
ms
µs
10%
7.33 Timing Requirements: SMBus
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
fSMB
SMBus operating
frequency
SLAVE mode, SMBC 50% duty cycle
fMAS
SMBus master clock
frequency
MASTER mode, no clock low slave extend
tBUF
Bus free time between start
and stop
18
10
51.2
4.7
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NOM
MAX
UNIT
100
kHz
kHz
µs
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7.33 Timing Requirements: SMBus (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
Hold time after (repeated)
start
4.0
µs
tSU(START)
Repeated start setup time
4.7
µs
tSU(STOP)
Stop setup time
4.0
µs
tHD(START)
tHD(DATA)
Data hold time
300
ns
tSU(DATA)
Data setup time
250
ns
tTIMEOUT
Error signal detect time
25
tLOW
Clock low period
4.7
35
ms
tHIGH
Clock high period
50
µs
tR
Clock rise time
10% to 90%
1000
ns
tF
Clock fall time
90% to 10%
300
ns
tLOW(SEXT)
Cumulative clock low slave
extend time
25
ms
tLOW(MEXT)
Cumulative clock low
master extend time
10
ms
µs
4.0
7.34 Timing Requirements: SMBus XL
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
fSMBXL
SMBus XL operating
frequency
tBUF
Bus free time between start
and stop
tHD(START)
tSU(START)
SLAVE mode
40
NOM
MAX UNIT
400
kHz
4.7
µs
Hold time after (repeated) start
4.0
µs
Repeated start setup time
4.7
µs
4.0
tSU(STOP)
Stop setup time
tTIMEOUT
Error signal detect time
tLOW
tHIGH
5
µs
20
ms
Clock low period
20
µs
Clock high period
20
µs
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TtR
tSU(STOP)p
TtF
TtF
tHD(START)
TtBUFT
SMBC
SMBC
SMBD
SMBD
P
TtR
TtHIGHT
TtLOWT
S
tHD(DATA)T
Start and Stop Condition
TtSU(DATA)
Wait and Hold Condition
tSU(START)T
TtTIMEOUT
SMBC
SMBC
SMBD
SMBD
S
Timeout Condition
Repeated Start Condition
Figure 7-1. SMBus Timing Diagram
7.35 Typical Characteristics
0.15
8.0
Max CC Offset Error
Min CC Offset Error
6.0
ADC Offset Error (µV)
CC Offset Error ( V)
0.10
0.05
0.00
±0.05
±0.10
4.0
2.0
0.0
±2.0
±4.0
±6.0
±0.15
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
±40
±20
C001
Figure 7-2. CC Offset Error vs. Temperature
20
Max ADC Offset Error
Min ADC Offset Error
±8.0
0
20
40
60
Temperature (°C)
80
100
120
C003
Figure 7-3. ADC Offset Error vs. Temperature
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264
Low-Frequency Oscillator (kHz)
Reference Voltage (V)
1.24
1.23
1.22
1.21
1.20
260
258
256
254
252
250
±40
0
±20
20
40
60
80
100
Temperature (ƒC)
±40
0
±20
20
40
60
80
Temperature (ƒC)
C006
Figure 7-4. Reference Voltage vs. Temperature
100
C007
Figure 7-5. Low-Frequency Oscillator vs.
Temperature
16.9
–24.6
OLD Protection Threshold (mV)
High-Frequency Oscillator (MHz)
262
16.8
16.7
16.6
–24.8
–25.0
–25.2
–25.4
–25.6
–25.8
±40
±20
0
20
40
60
80
100
120
Temperature (ƒC)
–40
–20
0
Figure 7-6. High-Frequency Oscillator vs.
Temperature
20
40
60
80
100
Temperature (°C)
C008
120
C009
Threshold setting is –25 mV.
Figure 7-7. Overcurrent Discharge Protection
Threshold vs. Temperature
±86.0
SCD 1 Protection Threshold (mV)
SCC Protection Threshold (mV)
87.4
87.2
87.0
86.8
86.6
86.4
86.2
±86.2
±86.4
±86.6
±86.8
±87.0
±87.2
±40
±20
0
20
40
60
80
100
120
Temperature (ƒC)
±40
Threshold setting is 88.85 mV.
±20
0
20
40
60
Temperature (ƒC)
C010
80
100
120
C011
Threshold setting is –88.85 mV.
Figure 7-8. Short Circuit Charge Protection
Threshold vs. Temperature
Figure 7-9. Short Circuit Discharge 1 Protection
Threshold vs. Temperature
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±172.9
Over-Current Delay Time (mS)
SCD 2 Protection Threshold (mV)
11.00
±173.0
±173.1
±173.2
±173.3
±173.4
±173.5
10.95
10.90
10.85
10.80
10.75
10.70
±173.6
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
Threshold setting is –177.7 mV.
0
20
40
60
80
100
Temperature (ƒC)
120
C013
Threshold setting is 11 ms.
Figure 7-10. Short Circuit Discharge 2 Protection
Threshold vs. Temperature
Figure 7-11. Overcurrent Delay Time vs.
Temperature
480
452
450
SC Discharge 1 Delay Time ( S)
SC Charge Current Delay Time ( S)
±20
C012
448
446
444
442
440
438
436
434
432
460
440
420
400
±40
±20
0
20
40
60
80
100
Temperature (ƒC)
120
±40
±20
0
Threshold setting is 465 µs.
20
40
60
80
100
Temperature (ƒC)
C014
120
C015
Threshold setting is 465 µs (including internal delay).
Figure 7-12. Short Circuit Charge Current Delay
Time vs. Temperature
Figure 7-13. Short Circuit Discharge 1 Delay Time
vs. Temperature
3.49825
2.4984
2.49835
3.4982
Cell Voltage (V)
Cell Voltage (V)
2.4983
2.49825
2.4982
2.49815
2.4981
3.49815
3.4981
3.49805
2.49805
3.498
2.498
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
±40
Figure 7-14. VCELL Measurement at 2.5-V vs.
Temperature
±20
0
20
40
60
Temperature (ƒC)
C016
80
100
120
C017
This is the VCELL average for single cell.
Figure 7-15. VCELL Measurement at 3.5-V vs.
Temperature
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4.24805
Measurement Current (mA)
99.25
Cell Voltage (V)
4.248
4.24795
4.2479
4.24785
4.2478
99.20
99.15
99.10
99.05
99.00
±40
±20
0
20
40
60
Temperature (ƒC)
80
100
120
±40
This is the VCELL average for single cell.
±20
0
20
40
60
80
100
Temperature (ƒC)
C018
120
C019
ISET = 100 mA
Figure 7-16. VCELL Measurement at 4.25-V vs.
Temperature
Figure 7-17. I measured vs. Temperature
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8 Detailed Description
8.1 Overview
The BQ40Z50-R2 device, incorporating patented Impedance Track™ technology, provides cell balancing while
charging or at rest. This fully integrated, single-chip, pack-based solution, including a diagnostic lifetime data
monitor and black box recorder, provides a rich array of features for gas gauging, protection, and authentication
for 1-series, 2-series, 3-series, and 4-series cell Li-ion and Li-polymer battery packs.
Cell Detach
Detection
Wake
Comparator
PCHG
DSG
CHG
PBI
VCC
BAT
VSS
Cell, Stack,
Pack
Voltage
PACK
VC2
VC1
VC4
Cell
Balancing
VC3
8.2 Functional Block Diagram
Power Mode
Control
High Side
N-CH FET
Drive
P-CH
FET Drive
Power On
Reset
Zero Volt
Charge
Control
PTC
Overtemp
Short Circuit
Comparator
PTCEN
PTC
FUSE
Control
FUSE
High
Voltage
I/O
PRES or SHUTDN
SRP
SRN
Over
Current
Comparator
Voltage
Reference2
NTC Bias
Random
Number
Generator
Watchdog
Timer
Internal
Temp
Sensor
LED Display
Drive I/O
TS1
TS2
TS3
ADC/CC
FRONTEND
ADC MUX
DISP
LEDCNTLC
LEDCNTLB
LEDCNTLA
TS4
Voltage
Reference1
BTP_INT
AFE Control
Low
Frequency
Oscillator
1.8V LDO
Regulator
AFE COM
Engine
SBS High
Voltage
Translation
I/O &
Interrupt
Controller
AFE COM
Engine
SBS COM
Engine
SMBD
SMBC
High
Frequency
Oscillator
Low Voltage
I/O
I/O
ADC/CC
Digital Filter
Data (8bit)
bqBMP
CPU
PMInstr
(8bit)
Timers &
PWM
DMAddr (16bit)
PMAddr
(16bit)
Program
Flash
EEPROM
Data Flash
EEPROM
Data
SRAM
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8.3 Feature Description
8.3.1 Primary (1st Level) Safety Features
The BQ40Z50-R2 supports a wide range of battery and system protection features that can easily be configured.
See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for detailed descriptions of each protection
function.
The primary safety features include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Cell Overvoltage Protection
Cell Undervoltage Protection
Cell Undervoltage Protection Compensated
Overcurrent in Charge Protection
Overcurrent in Discharge Protection
Overload in Discharge Protection
Short Circuit in Charge Protection
Short Circuit in Discharge Protection
Overtemperature in Charge Protection
Overtemperature in Discharge Protection
Undertemperature in Charge Protection
Undertemperature in Discharge Protection
Overtemperature FET protection
Precharge Timeout Protection
Host Watchdog Timeout Protection
Fast Charge Timeout Protection
Overcharge Protection
Overcharging Voltage Protection
Overcharging Current Protection
Over Precharge Current Protection
8.3.2 Secondary (2nd Level) Safety Features
The secondary safety features of the BQ40Z50-R2 can be used to indicate more serious faults via the FUSE
pin. This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for detailed descriptions of each
protection function.
The secondary safety features provide protection against:
• Safety Overvoltage Permanent Failure
• Safety Undervoltage Permanent Failure
• Safety Overtemperature Permanent Failure
• Safety FET Overtemperature Permanent Failure
• Qmax Imbalance Permanent Failure
• Impedance Imbalance Permanent Failure
• Capacity Degradation Permanent Failure
• Cell Balancing Permanent Failure
• Fuse Failure Permanent Failure
• PTC Permanent Failure
• Voltage Imbalance At Rest Permanent Failure
• Voltage Imbalance Active Permanent Failure
• Charge FET Permanent Failure
• Discharge FET Permanent Failure
• AFE Register Permanent Failure
• AFE Communication Permanent Failure
• Second Level Protector Permanent Failure
• Instruction Flash Checksum Permanent Failure
• Open Cell Connection Permanent Failure
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•
•
Data Flash Permanent Failure
Open Thermistor Permanent Failure
8.3.3 Charge Control Features
The BQ40Z50-R2 charge control features include:
•
•
•
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range
Handles more complex charging profiles. Allows for splitting the standard temperature range into two subranges and allows for varying the charging current according to the cell voltage
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
Reduces the charge difference of the battery cells in a fully charged state of the battery pack gradually using
a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing
to be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination.
Supports precharging/0-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicates charge status via charge and discharge alarms
8.3.4 Gas Gauging
The BQ40Z50-R2 uses the Impedance Track algorithm to measure and calculate the available capacity in
battery cells. The BQ40Z50-R2 accumulates a measure of charge and discharge currents and compensates the
charge current measurement for the temperature and state-of-charge of the battery. The BQ40Z50-R2 estimates
self-discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device
also has TURBO Mode 2.0 support, which enables the BQ40Z50-R2 to provide the necessary data for the
MCU to determine what level of peak power consumption can be applied without causing a system reset or
transient battery voltage level spike to trigger termination flags. See the BQ40Z50-R2 Technical Reference
Manual (SLUUBK0) for further details.
8.3.5 Configuration
8.3.5.1 Oscillator Function
The BQ40Z50-R2 fully integrates the system oscillators and does not require any external components to
support this feature.
8.3.5.2 System Present Operation
The BQ40Z50-R2 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external
system, the BQ40Z50-R2 detects this as system present.
8.3.5.3 Emergency Shutdown
For battery maintenance, the emergency shutdown feature enables a push button action connecting the
SHUTDN pin to shut down an embedded battery pack system before removing the battery. A high-to-low
transition of the SHUTDN pin signals the BQ40Z50-R2 to turn off the CHG and DSG FETs, disconnecting the
power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by
another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.
8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
In a 1-series cell configuration, VC4 is shorted to VC, VC2, and VC1. In a 2-series cell configuration, VC4 is
shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.
8.3.5.5 Cell Balancing
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the
device's internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same
time. Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell
balancing mode, only one cell at a time can be balanced.
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The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
8.3.6 Battery Parameter Measurements
8.3.6.1 Charge and Discharge Counting
The BQ40Z50-R2 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement,
and a second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures
bipolar signals from –0.1 V to 0.1 V. The BQ40Z50-R2 detects charge activity when VSR = V(SRP) – V(SRN)
is positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The BQ40Z50-R2 continuously
integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.
8.3.7 Battery Trip Point (BTP)
Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has
depleted to a certain value set in a DF register. This feature enables a host to program two capacity-based
thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin, and the setting or clearing of the
OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pullup is applied when the BTP feature is active. Depending on the system design, an external
pullup may be required to put on the BTP_INT pin. See Section 7.12 for details.
8.3.8 Lifetime Data Logging Features
The BQ40Z50-R2 offers lifetime data logging for several critical battery parameters. The following parameters
are updated every 10 hours if a difference is detected between values in RAM and data flash:
• Maximum and Minimum Cell Voltages
• Maximum Delta Cell Voltage
• Maximum Charge Current
• Maximum Discharge Current
• Maximum Average Discharge Current
• Maximum Average Discharge Power
• Maximum and Minimum Cell Temperature
• Maximum Delta Cell Temperature
• Maximum and Minimum Internal Sensor Temperature
• Maximum FET Temperature
• Number of Safety Events Occurrences and the Last Cycle of the Occurrence
• Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination
• Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
• Number of Shutdown Events
• Cell Balancing Time for Each Cell
•
(This data is updated every 2 hours if a difference is detected.)
Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
8.3.9 Authentication
The BQ40Z50-R2 supports authentication by the host using SHA-1.
8.3.10 LED Display
The BQ40Z50-R2 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a
permanent fail (PF) error code indication.
8.3.11 IATA Support
The BQ40Z50-R2 supports IATA with several new commands and procedures. See the BQ40Z50-R2 Technical
Reference Manual (SLUUBK0) for further details.
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8.3.12 Voltage
The BQ40Z50-R2 updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the
BQ40Z50-R2 measures the voltage, and scales and calibrates it appropriately. This data is also used to
calculate the impedance of the cell for the Impedance Track gas gauging.
8.3.13 Current
The BQ40Z50-R2 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 1-mΩ to 3-mΩ typ. sense resistor.
8.3.14 Temperature
The BQ40Z50-R2 has an internal temperature sensor and inputs for four external temperature sensors. All
five temperature sensor options can be individually enabled and configured for cell or FET temperature usage.
Two configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which use a different thermistor profile.
8.3.15 Communications
The BQ40Z50-R2 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS
specification.
8.3.15.1 SMBus On and Off State
The BQ40Z50-R2 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing
this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
8.3.15.2 SBS Commands
See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for further details.
8.4 Device Functional Modes
The BQ40Z50-R2 supports three power modes to reduce power consumption:
• In NORMAL mode, the BQ40Z50-R2 performs measurements, calculations, protection decisions, and data
updates in 250-ms intervals. Between these intervals, the BQ40Z50-R2 is in a reduced power stage.
• In SLEEP mode, the BQ40Z50-R2 performs measurements, calculations, protection decisions, and data
updates in adjustable time intervals. Between these intervals, the BQ40Z50-R2 is in a reduced power stage.
The BQ40Z50-R2 has a wake function that enables exit from SLEEP mode when current flow or failure is
detected.
• In SHUTDOWN mode, the BQ40Z50-R2 is completely disabled.
See the BQ40Z50-R2 Technical Reference Manual (SLUUBK0) for further details.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The BQ40Z50-R2 is a gas gauge with primary protection support, and can be used with 1-series to 4-series
Li-ion/Li-polymer battery packs. To implement and design a comprehensive set of parameters for a specific
battery pack, users need the Battery Management Studio (BQSTUDIO) graphical user-interface tool installed on
a PC during development. The firmware installed on the BQSTUDIO tool has default values for this product,
which are summarized in the BQ40Z50-R2 Technical Reference Manual (SLUUBK0). Using the BQSTUDIO tool,
these default values can be changed to cater to specific application requirements during development once
the system parameters, such as fault trigger thresholds for protection, enable/disable of certain features for
operation, configuration of cells, chemistry that best matches the cell used, and more are known. This data is
referred to as the "golden image."
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29
4P
3P
2P
1P
1N
1
2
3
4
5
1
100
C5
0.1uF
0.1uF
0.1uF
C6
C10
0.1uF
1
2
3
4
VDD
OUT
U1
CD
V1
VSS
V4
V3
V2
GND
8
7
6
5
C8
0.1uF
C9
0.1uF
1
AGND
F1
3
Q5
5,6,8
1,2,
4,7
R2
1.0k
1.0k
C11
0.1uF
3
R10
51k
3
R1
Q2
7,8
5,6,
R11
5.1k
3
1
Q1
GND
10
11
12
13
6
8
15
16
2
3
4
5
1
26
1
7
14
29
-30V
2
R6
10Meg
R12
5.1k
U3
VCC
PBI
VC4
VC3
VC2
VC1
C1
0.1uF
C2
1,2,3
Q3
R14
5.1k
BAT
PTC
PTCEN
CHG
FUSE
PCHG
DSG
PACK
VSS
PAD
SMBC
SMBD
DISP
LEDCNTLC
LEDCNTLB
LEDCNTLA
7,8
5,6,
0.1uF
3
R13
100
BTP_INT
PRES/SHUTDN
SRP
SRN
TS1
TS2
TS3
TS4
NC
NC
NC
24
32
23
25
30
31
28
27
22
21
20
17
18
19
9
33
R4
10Meg
GND
2
3
300
1,2,3
R3
10Meg
5.1k
R19
C7
0.1uF
5.1k
D1
C13
R18
30V
2.2uF
BTP_INT 1
PRES / SHUTDOWN
RT5
GND
4
1
2
Q4
1
R5
10k
4
3
CHGND
L
R15
10k
GND
1
2
3
t°
IC ground should be connected to the 1N cell tab.
Place RT1 close to Q2 and Q3.
D5
LED2
D6
U5
LED1
R8
CHGND
LED5
D4
U2
4
3
SHUTDOWN
1
2
200
C3
0.1uF
SMBD
SMBC
PACK-
CHGND
C4
0.1uF
J3
GND
4
3
2
1
5
4
3
2
1
J1
Replace D1 and R13 with a 10 ohm res
istor for single cell applications
PRES / SHUTDOWN
2
C12
0.1uF
RT1
LED4
D3
100
D2
R24
100
LED3
R25
U4
Copyright © 2017, Texas Instruments Incorporated
PACK+
P
Sys Pres
PACKPACK- ACK+ ED DISPLAY
Product Folder Links: BQ40Z50-R2
1
2
R7
R9
1.0k
C14
0.1uF
GND
4
t°
R16
100
C15
0.1uF
RT4
GND
t°
1.0k
R20
100
C16
RT3
GND
t°
R17
R21
100
100
R22
R23
RT2
GND
10.0k ohm
0.1uF
R27
100
10.0k ohm
C17
GND
C18
0.1uF
R28
10.0k ohm
J2
NT1
GND
R26
100
t°
PAD
9
2
4
0.001
10.0k ohm
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1
2
1
2
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SLUSCS4C – JUNE 2017 – REVISED APRIL 2021
BQ40Z50-R2
9.2 Typical Applications
Figure 9-1. Application Schematic
BQ40Z50-R2
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SLUSCS4C – JUNE 2017 – REVISED APRIL 2021
9.2.1 Design Requirements
Table 9-1 shows the default settings for the main parameters. Use the BQSTUDIO tool to update the settings to
meet the specific application or battery pack configuration requirements.
The device should be calibrated before any gauging test. Follow the procedures on the BQSTUDIO Calibration
page to calibrate the device, and use the information on the BQSTUDIO Chemistry page to update the match
chemistry profile to the device.
Table 9-1. Design Parameters
DESIGN PARAMETER
(1)
EXAMPLE
Cell Configuration
3s1p (3-series with 1 parallel)(1)
Design Capacity
4400 mAh
Device Chemistry
1210 (LiCoO2/graphitized carbon)
Cell Overvoltage at Standard Temperature
4300 mV
Cell Undervoltage
2500 mV
Shutdown Voltage
2300 mV
Overcurrent in CHARGE Mode
6000 mA
Overcurrent in DISCHARGE Mode
–6000 mA
Short Circuit in CHARGE Mode
0.1 V/Rsense across SRP, SRN
Short Circuit in DISCHARGE Mode
0.1 V/Rsense across SRP, SRN
Safety Overvoltage
4500 mV
Cell Balancing
Disabled
Internal and External Temperature Sensor
External temperature sensor is used.
Undertemperature Charging
0°C
Undertemperature Discharging
0°C
BROADCAST Mode
Disabled
Battery Trip Point (BTP) with active high interrupt
Disabled
When using the device the first time and if a 1-s or 2-s battery pack is used, then a charger or power supply should be connected
to the PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the BQ40Z50-R2 Technical Reference
Manual [SLUUBK0] for details) before removing the charger connection.
9.2.2 Detailed Design Procedure
9.2.2.1 High-Current Path
The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the
pack, it finds its way through protection FETs, a chemical fuse, the Li-ion cells and cell connections, and the
sense resistor, and then returns to the PACK– terminal (see Figure 9-2). In addition, some components are
placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge.
9.2.2.1.1 Protection FETs
Select the N-channel charge and discharge FETs for a given application. Most portable battery applications are a
good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩ when the
gate drive voltage is 8 V.
If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account
for the power dissipation of the series resistor. The precharge current is limited to (VCHARGER – VBAT)/R1 and
maximum power dissipation is (Vcharger – Vbat)2/R1.
The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source
to ensure they are turned off if the gate drive is open.
Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation
if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads
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must be designed to be as short and wide as possible. Ensure that the voltage ratings of both C1 and C2 are
adequate to hold off the applied voltage if one of the capacitors becomes shorted.
Figure 9-2. BQ40Z50-R2 Protection FETs
9.2.2.1.2 Chemical Fuse
The chemical fuse (Dexerials, Uchihashi, and so on) is ignited under command from either the bq294700
secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive
voltage to the gate of Q5, shown in Figure 9-3, which then sinks current from the third terminal of the fuse,
causing it to ignite and open permanently.
It is important to carefully review the fuse specifications and match the required ignition current to that available
from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device.
The fuse control circuit is discussed in detail in Section 9.2.2.2.5.
4P
to 2nd Level Protector
to FUSE Pin
Figure 9-3. FUSE Circuit
9.2.2.1.3 Li-Ion Cell Connections
For cell connections, it is important to remember that high current flows through the top and bottom connections;
therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid any errors
due to a drop in the high-current copper trace. The location marked 4P in Figure 9-4 indicates the Kelvin
connection of the most positive battery node. The connection marked 1N is equally important. The VC5 pin
(a ground reference for cell voltage measurement), which is in the older generation devices, is not in the
BQ40Z50-R2 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid
an unwanted voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.
32
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Figure 9-4. Li-Ion Cell Connections
9.2.2.1.4 Sense Resistor
As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense
resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement
drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and
short-circuit ranges of the BQ40Z50-R2 device. Select the smallest value possible to minimize the negative
voltage generated on the BQ40Z50-R2 VSS node(s) during a short circuit. This pin has an absolute minimum
of –0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to
support a 1-mΩ to 3-mΩ sense resistor.
The BQ40Z50-R2 ground scheme is different from that of the older generation devices. In previous devices,
the device ground (or low current ground) is connected to the SRN side of the RSENSE resistor pad. In the
BQ40Z50-R2 device, however, it connects the low-current ground on the SRP side of the RSENSE resistor pad
close to the battery 1N terminal (see Section 9.2.2.1.3). This is because the BQ40Z50-R2 device has one less
VC pin (a ground reference pin VC5) compared to the previous devices. The pin was removed and was internally
combined to SRP.
Figure 9-5. Sense Resistor
9.2.2.1.5 ESD Mitigation
A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the
mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack
if one of the capacitors becomes shorted.
Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.
9.2.2.2 Gas Gauge Circuit
The gas gauge circuit includes the BQ40Z50-R2 and its peripheral components. These components are divided
into the following groups: differential low-pass filter, PBI, system present, SMBus communication, fuse circuit,
and LED.
9.2.2.2.1 Coulomb-Counting Interface
The BQ40Z50-R2 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from
the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP
and SRN inputs.
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Figure 9-6. Differential Filter
9.2.2.2.2 Power Supply Decoupling and PBI
The BQ40Z50-R2 device has an internal LDO that is internally compensated and does not require an external
decoupling capacitor.
25
FUSE
27
VCC 26
PACK
29
NC
DSG 28
PCHG 30
CHG 31
PWPD
BAT
32
33
The PBI pin is used as a power supply backup input pin, providing power during brief transient power outages. A
standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground, as shown in Figure 9-7.
1 PBI
23
3
VC3
LEDCNTLC 22
4
VC2
LEDCNTLB 21
5
VC1
LEDCNTLA 20
PTC
6 SRN
SMBC
7
SMBD
NC
NC
1 5 BTP_INT
14
TS4
13
TS3
12
TS1
TS2
11
10
9
vss
8 SRP
PRES or SHUTDN
2.2 μF
24
VC4
19
18
DISP 17
16
C13
PTCEN
2
Copyright © 2017 , Texas Instruments Incorporated
Figure 9-7. Power Supply Decoupling
9.2.2.2.3 System Present
The system present signal informs the gas gauge whether the pack is installed into or removed from the system.
In the host system, this pin is grounded. The PRES pin of the BQ40Z50-R2 device is occasionally sampled to
test for system present. In ACTIVE mode, the PRES pin is pulsed every 250 ms for a duration of 5 ms (RHOEN
is on), and just before it is turned off, the state of the PRES pin is checked to see if it is low or high. The average
of the four measurements is used to determine if the PRES is asserted or not. In SLEEP mode, the PRES pin is
pulsed every "Sleep Voltage Time," and the state of the PRES pin is determined. A resistor can be used to pull
the signal low and the resistance must be 20 kΩ or lower to ensure that the test pulse is lower than the VIL limit.
The pullup current source is typically 10 µA to 20 µA. When the PRES pin is not pulsed, the PRES pin is tied
internally to VSS (RHOUT is on), and any pullup on the PRES pin will cause a battery drain when not charging.
Refer to the PRES pin diagram in
34
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16
PRES
BTP_INT
15
NC
14
13
TS4
SLUSCS4C – JUNE 2017 – REVISED APRIL 2021
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