BUF08800

BUF08800 SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 Programmable Reference Generator and 400mA VCOM Driver FEATURES D 10-BIT RESOLUTION D 7- OR 8-CHANNEL GAMMA CORRECTION D INTEGRATED VCOM DRIVER: D D D D D D D 400mA PEAK CURRENT DIGITAL GATE VOLTAGE ADJUSTMENT CIRCUITS RAIL-TO-RAIL OUTPUT LOW SUPPLY CURRENT: 1mA/ch SUPPLY VOLTAGE: 7V to 22V DIGITAL SUPPLY: 2.0V to 5.5V INDUSTRY-STANDARD, TWO-WIRE INTERFACE HIGH ESD RATING: 4kV HBM DESCRIPTION The BUF08800 reference generator offers eight programmable reference channels that can be used depending on the application needs. For example, all eight channels can be used for gamma correction, or some as gamma references and some to digitally adjust the gate voltages or VCOM. All gamma/VCOM channels swing to within 100mV of the positive or negative supply rail with a 10mA load. All channels are programmed using a standard two-wire interface that supports standard operation up to 400kHz and also high-speed data transfer up to 3.4MHz. The integrated VCOM driver features up to 400mA peak current drive. VCOM voltage compensation at different locations on the LCD panel can be accomplished using the negative input of the integrated VCOM op amp. The Gate High and Low voltages can differ because of changes in panel size or technology. The BUF08800 supports digital adjustment circuits for the gate voltages. This feature enables the adjustment of gate voltages through software without changing hardware, thus reducing development time and risk. The BUF08800 is manufactured using Texas Instruments’ proprietary, state-of-the-art, high-voltage CMOS process. This process allows very dense logic as well as high supply voltage operation of up to 22V. The BUF08800 is available in a small TSSOP-20 PowerPad  package, and is specified from −40°C to +85°C. OUT 7 APPLICATIONS D TFT-LCD REFERENCE DRIVERS D REFERENCE VOLTAGE GENERATORS VSD BUF08800 10−Bit DAC 250kΩ VS +IN (VCOM) VCOM (OUT 1) −IN (VCOM) OUT 2 Gamma/VCOM Register Bank 1 Gamma/VCOM Register Bank 2 10−Bit DAC 10−Bit DAC OUT 3 10−Bit DAC 10−Bit DAC RELATED PRODUCTS OUT 8 FEATURES 12-Channel Gamma Correction Buffer 20-Channel Programmable Buffer, 10-Bit, VCOM 16-, 20-Channel Prog. Buffer with Memory Programmable VCOM Driver 18V Supply, Traditional Gamma Buffers 22V Supply, Traditional Gamma Buffers PRODUCT BUF12800 BUF20800 BUF20820 BUF01900 BUF11704 BUF11705 SDA SCL Control IF A0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2007, Texas Instruments Incorporated www.ti.com BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +24V Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Supply Input Terminals, SCL, SDA, AO, LD: Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Short-Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Short-circuit to ground. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT BUF08800 PACKAGE-LEAD HTSSOP-20 PACKAGE DESIGNATOR PWP PACKAGE MARKING BUF08800 ORDERING NUMBER BUF08800AIPWPR (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATIONS Top View BUF08800 HTSSOP GND GND +IN (VCOM) − IN (VCOM) VSD SCL SDA A0 LD GND (digital) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCOM (OUT 1) VS VS OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 2 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range: TA = −40°C to +85°C. At TA = +25°C, VS = +18V, VSD = 2.5V, RL = 1.5kΩ to GND, and CL = 200pF, unless otherwise noted. BUF08800 PARAMETER ANALOG Gamma Buffer Channels Reset Value Buffer 2−4 Output Swing: High Buffer 2−4 Output Swing: Low Buffer 5−8 Output Swing: High Buffer 5−8 Output Swing: Low Continuous Output Current Output Accuracy vs Temperature Integral Nonlinearity INL Differential Nonlinearity DNL Load Regulation, 10mA REG VCOM Driver/OUT 1 Reset Value Driver Input Range Driver Offset VCOM/OUT 1 Output Swing: High VCOM/OUT 1 Output Swing: Low VCOM/OUT 1 Output Swing: High VCOM/OUT 1 Output Swing: Low VBIAS Output Impedance Overall Output Accuracy vs Temperature Integral Nonlinearity INL Differential Nonlinearity DNL Load Regulation, 100mA REG Program to Out Delay tD ANALOG POWER SUPPLY Operating Range Total Analog Supply Current Over Temperature DIGITAL Logic 1 Input Voltage Logic 0 Input Voltage Logic 0 Output Voltage Input Leakage Clock Frequency DIGITAL POWER SUPPLY Operating Range Digital Supply Current(1) Over Temperature TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance(2) HTSSOP-20 HTSSOP-20 −40 −40 −65 35 20 IS Outputs at Reset Values, No Load CONDITIONS MIN TYP MAX UNITS Code = 512 Code = 1023, Sourcing 10mA Code = 0, Sinking 10mA Code = 1023, Sourcing 10mA Code = 0, Sinking 10mA 17.8 17.0 Code 512 Code = 512, IOUT = +5mA to −5mA Step Code = 00, No Load on Pin 2, IOUT = 0 IOUT = 0mA Referred to Pin 2, Code = 512 Pin 9, Code = 1023, Sourcing 10mA Pin 9, Code = 0, Sinking 10mA Pin 9, Code = 1023, Sourcing 400mA Pin 9, Code = 0, Sinking 400mA Pin 2 Pin 20 Code = 512 Pin 20 Pin 20 Pin 20, Code = 512, IOUT = +200mA to −200mA Step All Channels 9 17.85 0.7 17.2 0.2 30 ±10 ±20 0.3 0.3 0.5 9 1 0.25 ±50 1 2.5 1.5 V V V V V mA mV µV/°C Bits Bits mV/mA V V mV V V V V kΩ mV µV/°C Bits Bits mV/mA µs V mA mA V V V µA kHz MHz V µA µA 0.7 17.8 14 1 17.9 0.7 14.6 3.5 250 ±20 ±25 0.3 0.3 0.5 5 17.9 ±5 1 4 ±50 1 2.5 1.5 7 7 22 15 15 VIH VIL VOL 0.7 × VSD ISINK = 3mA Standard/Fast Mode High-Speed Mode 0.15 ±0.01 0.3 × VSD 0.4 ±10 400 3.4 5.5 25 100 +85 +95 +150 50 VSD ISD Outputs at Reset Values, No Load, Two-Wire Bus Inactive 2.0 Junction Temperature < +125°C °C °C °C °C/W °C/W qJA qJC (1) See typical characteristic curve Digital Supply Current vs Two-Wire Bus Activity. (2) Thermal pad attached to printed circuit board (PCB), 0lfm airflow, and 76mm × 76mm copper area. 3 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 TYPICAL CHARACTERISTICS At TA = +25°C, VS = +18V, VSD = 2.5V, RL = 1.5kΩ to GND, and CL = 200pF, unless otherwise noted. ANALOG SUPPLY CURRENT vs TEMPERATURE 8 7 6 5 IQ (mA) IQ (µA) 4 3 2 1 0 − 50 − 25 0 25 50 75 100 125 Temperature (_ C) 0 − 50 5 10 15 20 DIGITAL SUPPLY CURRENT vs TEMPERATURE − 25 0 25 50 75 100 125 Temperature (_ C) Figure 1 CHANNEL 2 FULL−SCALE OUTPUT SWING Figure 2 CHANNEL 8 FULL−SCALE OUTPUT SWING 5V/div 1µs/div 5V/div 1µs/div Figure 3 Figure 4 VCOM CHANNEL FULL−SCALE OUTPUT SWING DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE 1.0 0.8 0.6 DNL Error (LSB) 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 − 1.0 Limited by Range of Voltage Buffer 0 128 256 384 512 640 768 896 1024 VCOM OUT 1, OUT 2 (5 units shown) 5V/div 5µs/div Input Code Figure 5 4 Figure 6 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +18V, VSD = 2.5V, RL = 1.5kΩ to GND, and CL = 200pF, unless otherwise noted. DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE 1.0 0.8 0.6 DNL Error (LSB) INL Error (LSB) 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 − 1.0 0 128 256 Limited by Range of Voltage Buffer 384 512 640 768 896 1024 OUT 8 (4 units shown) 1.0 0.8 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 − 1.0 0 INTEGRAL NONLINEARITY ERROR vs INPUT CODE VCOM OUT 1, OUT 2 (5 units shown) Limited by Range of Voltage Buffer 128 256 384 512 640 768 896 1024 Input Code Input Code Figure 7 INTEGRAL NONLINEARITY ERROR vs INPUT CODE 1.0 0.8 0.6 INL Error (LSB) 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 − 1.0 0 128 256 Limited by Range of Voltage Buffer 384 512 640 768 896 OUT 8 (4 units shown) Figure 8 1024 Input Code Figure 9 5 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 APPLICATIONS INFORMATION The BUF08800 programmable voltage reference allows fast and easy adjustment of eight programmable reference outputs, each with 10-bit resolution. It allows very simple, time-efficient adjustment of the VCOM and gamma reference voltages. The BUF08800 is programmed through a high-speed, standard two-wire interface. The BUF08800 features a double-register structure for each digital-to-analog converter (DAC) channel to simplify the implementation of dynamic gamma control (see the Dynamic Control section). This architecture allows pre-loading of register data and rapid updating of all channels simultaneously. VCOM (OUT 1) and buffers 2−4 are able to swing to within 200mV of the positive supply rail, and to within 1V of the negative supply rail. Buffers 5−8 are able to swing to within 1V of the positive supply rail, and to within 250mV of the negative supply rail. (See the Electrical Characteristics table for further information.) Buffers 2−8 are capable of full-scale change in output voltage in less than 4µs; see Figure 4. The BUF08800 uses an analog supply of 7V to 22V and a digital supply of 2V to 5.5V. The digital supply must be applied prior to or simultaneously with the analog supply to avoid excessive current and power consumption; damage to the device may occur if it is left connected only to the analog supply for an extended time. Figure 10 shows the BUF08800 in a typical configuration. In this configuration, the BUF08800 device address is 74h. The output of each DAC is immediately updated as soon as data is received in the corresponding register (LD = 0). BUF08800 1 GND V COM (O UT 1) 20 (1) (1) V COM 2 GND VS 19 10 µ F 100 µ F VS 3 +IN (V COM) VS 18 4 − IN (V COM) (1) O UT 2 17 Source Driver 3.3V 1µ F 5 100nF V SD (1) O UT 3 16 (1) 6 Timing Controller SCL O UT 4 15 (1) 7 SDA O UT 5 14 8 A0 (1) O UT 6 13 9 LD (1) O UT 7 12 10 GND (digital)(2) (1) O UT 8 11 (1) RC combination optional (2) GND and GND (digital) are internally connected and must be at the same voltage potential. Figure 10. Typical Application Configuration 6 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 TWO-WIRE BUS OVERVIEW The BUF08800 communicates through an industry-standard, two-wire interface to receive data in slave mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are driven to a logic low level only. The device that initiates the communication is called a master, and the devices controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and 8 bits of data are sent followed by an Acknowledge Bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted as a START or STOP condition. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The BUF08800 can act only as a slave device; therefore, it never drives SCL. SCL is an input only for the BUF08800. DATA RATES The two-wire bus operates in one of three speed modes: D Standard: allows a clock frequency of up to 100kHz; D Fast: allows a clock frequency of up to 400kHz; and D High-speed mode (also called Hs mode): allows a clock frequency of up to 3.4MHz. The BUF08800 is fully compatible with all three modes. No special action is required to use the device in Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special address byte of 00001xxx, with SCL = 400kHz, following the START condition; xxx are bits unique to the Hs-capable master, and can be any value. The BUF08800 responds to the High-speed mode command regardless of the value of these last three bits. This byte is called the Hs master code. (Note that this is different from normal address bytes—the low bit does not indicate read/write status.) The BUF08800 does not acknowledge this byte; the communication protocol prohibits acknowledgment of the Hs master code. On receiving a master code, the BUF08800 switches on its Hs mode filters, and communicates at up to 3.4MHz. Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a STOP. The BUF08800 switches out of Hs mode at the first occurrence of a STOP condition. GENERAL CALL RESET AND POWER-UP The BUF08800 responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). The BUF08800 acknowledges both bytes. Upon receiving a General Call Reset, the BUF08800 performs a full internal reset, as though it had been powered off and then on. It always acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call data bytes other than 06h (0000 0110). The BUF08800 automatically performs a reset upon power-up. As part of the reset, the BUF08800 is configured for all outputs to change to mid-value, VS/2. The BUF08800 resets all outputs to mid-value (VS/2) when the device address is sent, followed by a valid DAC address with bits D7 to D5 set to ‘100’. If these bits are set to ‘010’, only the DAC being addressed in this most significant byte and the following least significant byte will be reset. ADDRESSING THE BUF08800 The address of the BUF08800 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the device acknowledges on address 74h (1110100). If the A0 pin is HIGH, the device acknowledges on address 75h (1110101), as shown in Table 1. Other valid addresses are possible through a simple mask change. Contact your TI representative for information. Table 1. BUF08800 Bus Address Options BUF08800 ADDRESS A0 pin is LOW (device will not acknowledge on address 74h) A0 pin is HIGH (device will acknowledge on address 74h) ADDRESS 111 0100 111 0101 Table 2. Quick-Reference Table of Commands COMMAND General Call Reset High-Speed Mode CODE Address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. 7 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 OUTPUT VOLTAGE Buffer output values are determined by the supply voltage and the decimal value of the binary input code used to program that buffer. The value is calculated using Equation 1: VOUT + VS 1024 Decimal Value of Code 4. Send two bytes of data for the specified DAC. Begin by sending the most significant byte first (bits D15−D8, of which only bits D9 and D8 are used), followed by the least significant byte (bits D7−D0). The DAC register is updated after receiving the second byte. Send a STOP condition on the bus. (1) 5. The BUF08800 outputs 2−8 are capable of a full-scale voltage output change in typically 4µs—no intermediate steps are required. Output swing is limited to the voltages specified in the Electrical Characteristics table. VCOM (OUT 1) through OUT 4 can swing from 1V to VS − 0.2V; OUT 5 through OUT 8 can swing between 0.25V and VS − 1V. The BUF08800 acknowledges each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not the same as updating the DAC output voltage. See the Output Latch section. The process of updating multiple registers begins the same as when updating a single register. However, instead of sending a STOP condition after writing the addressed register, the master continues to send data for the next register. The BUF08800 automatically and sequentially steps through subsequent registers as additional data are sent. The process continues until all desired registers have been updated or a STOP condition is sent. To write to multiple registers: 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF08800 acknowledges this byte. Send either the VCOM (OUT 1) address byte to start at the first DAC (VCOM OUT 1) or send the address of whichever DAC is the first to be updated. The BUF08800 begins with this DAC and steps through subsequent DACs in sequential order. Send the bytes of data. The first two bytes are for the DAC addressed in step 3. Its register is automatically updated after receiving the second byte. The next two bytes are for the following DAC. The DAC register is updated after receiving the fourth byte. The last two bytes are for DAC_8. The DAC register is updated after receiving the 24th byte. For each DAC, begin by sending the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning), followed by the least significant byte (bits D7−D0). Send a STOP condition on the bus. READ/WRITE OPERATIONS The BUF08800 is able to read from a single DAC or multiple DACs, or write to the register of a single DAC, or multiple DACs in a single communication transaction. See the timing diagrams; Figure 11 through Figure 14. DAC addresses begin with 0000, which correspond to VCOM (OUT 1), through 0111, which correspond to DAC_8; this address archetecture is shown in Table 3. Write commands are performed by setting the read/write bit LOW. Setting the read/write bit HIGH performs a read transaction. Table 3. Quick-Reference Table of DAC Addresses DAC VCOM OUT 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 DAC 8 ADDRESS 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4. Writing To write to a single DAC register: 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF08800 acknowledges this byte. Send a DAC address byte. Bits D7−D3 are unused and must be set to 0. Bits D2−D0 are the DAC address. Only DAC addresses 0000 to 0111 are valid and will be acknowledged. 5. The BUF08800 acknowledges each byte. To terminate communication, send a STOP or START condition on the bus. Only DACs that have received both bytes will be updated. 8 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 Reading To read the register of one DAC: 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF08800 acknowledges this byte. Send a DAC address byte. Bits D7−D3 have no meaning and must be ‘0’; bits D2−D0 are the DAC address. Only DAC addresses 0000 to 0111 are valid and will be acknowledged. Send a START or STOP/START condition on the bus. Send correct device address and read/write bit = HIGH. The BUF08800 acknowledges this byte. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning); the next is the least significant byte (bits D7−D0). Acknowledge after receiving each byte. Send a STOP condition on the bus. To read multiple DAC registers: 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF08800 acknowledges this byte. Send either the VCOM DAC (VCOM OUT 1) address byte to start at the first DAC or send the address byte for whichever DAC is the first in the sequence of DACs to be read. The BUF08800 begins with this DAC and steps through subsequent DACs in sequential order. Send the device address and read/write bit = HIGH. Receive bytes of data. The first two bytes are for the specified DAC. The first received byte is the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning). The next byte is the least significant byte (bits D7−D0). Acknowledge after receiving each byte. When all desired DACs have been read, send a STOP or START condition on the bus. 4. 5. 6. 4. 5. 6. 7. 7. 8. Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge. Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge. 9 10 Write Operation DAC LSbyte Ackn DAC MSbyte. D14 −D10 have no meaning. Ackn DAC address pointer. D7 −D3 have no meaning. Ackn Write Device Address Write single DAC register. P3 −P0 specify the DAC address. Start SCL D2 D2 D3 D4 D5 D6 D7 Ackn D8 D9 D10 D11 D12 D13 D14 D15 Ackn P0 P1 P2 D3 D4 D5 D6 D7 Ackn W A0 A1 A2 A3 A4 D3 D4 D5 D6 D7 Ackn D8 D9 D10 D11 D12 D13 D14 D15 Ackn P0 P1 P2 D3 D4 D5 D6 D7 Ackn W A0 A1 A2 A3 A4 A5 A5 A6 A6 SDA_In Device_Out If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. Start Ackn DAC MSbyte. D15 −D10 have no meaning. Ackn Read Device Address Ackn Read Operation Read single DAC register. P3 −P0 specify DAC address. DAC address pointer. D7 −D3 have no meaning. Ackn Write Device Address Start SCL D4 D13 D13 D14 D15 Ackn R D14 D15 Ackn R D4 D5 D6 D7 Ackn D8 D9 D10 D11 D12 D5 D6 D7 Ackn D8 D9 D10 D11 D12 A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 Ackn Ackn P0 P0 P1 P1 P2 P2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Ackn Ackn W W A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 SDA_In Device_Out BUF08800 Stop Ackn Ackn D0 D1 Ackn D0 D1 SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 Figure 11. Write Single DAC Register The whole DAC Register D9 −D0 is updated in this moment. No Ackn Stop DAC LSbyte D0 D1 D2 D3 Figure 12. Read Single DAC Register No Ackn D0 D1 D2 D3 www.ti.com DAC(pointer+1) MSbyte. D14 −D10 have no meaning. Write Operation Write Ackn Ackn Start DAC address pointer. D7 −D3 have no meaning. Ackn DAC(pointer) MSbyte. D14 −D10 have no meaning. Ackn DAC(pointer) LSbyte Write multiple DAC registers. P3 −P0 specify start DAC address. Device Address Start … … … www.ti.com SCL SDA_In A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 D4 D3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn Device_Out If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 D4 D3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn … The whole DAC Register D9 −D0 is updated in this moment. … DAC(11) MSbyte. D14 −D10 have no meaning. Ackn DAC(11) LSbyte Ackn Stop … … D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D4 D3 D3 D2 D2 D1 D0 Ackn … D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn Figure 13. Write Multiple DAC Registers If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. The whole DAC Register D9 −D0 is updated in this moment. Read operation Ackn Start DAC address pointer. D7 −D3 have no meaning. Ackn Start Device Address Read Ackn DAC(pointer) MSbyte. D15 −D10 have no meaning. Device Address Write A4 A3 A2 A1 A0 W Ackn D7 D6 D5 D4 D3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 D4 D3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Read multiple DAC registers. P3 −P0 specify start DAC address. Start SCL … … … … SDA_In A6 A5 Device_Out A6 A5 … … … … D15 DAC(11) MSbyte. D15 −D10 have no meaning. Ackn DAC(11) LSbyte Ackn Stop D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Figure 14. Read Multiple DAC Registers D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 BUF08800 11 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 OUTPUT LATCH Because the BUF08800 features a double-buffered register structure, updating a DAC register is not the same as updating the DAC output voltage. There are three methods for latching transferred data from the storage registers into the DACs to update the DAC output voltage. Method 1 requires externally setting the latch pin (LD) = LOW, which updates each DAC output voltage whenever its corresponding register is updated. Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer and until LD = LOW, which simultaneously updates the output voltages of all DACs to the new register values. Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a ‘1’ in bit 15 of any DAC register. The update occurs after receiving the 16-bit data for the currently-written register. Use methods 2 and 3 to transfer a future data set into the first bank of registers in advance to prepare for a very fast update of DAC output voltages. The General Call Reset and the power-up reset update the DACs regardless of the state of the latch pin (LD). D Allows simple adjustment of gamma curves during production to accommodate changes in the panel manufacturing process or end-customer requirements. Decreases cost and space. D VCOM ADJUSTMENT The output of the VCOM digital-to-analog converter (DAC) is internally connected to the input of the VCOM buffer. As a result of the high 10-bit resolution, the VCOM voltage can directly be adjusted without the need for external circuitry. The integrated VCOM driver can deliver up to 400mA of peak current. In addition, the negative input is brought out as a separate pin on the package to facilitate VCOM compensation or equalization of the VCOM voltage across the panel (see Figure 17). Traditional VCOM adjustment uses a mechanical potentiometer and a voltage divider for adjustment, as shown in Figure 15. The programmable VCOM channel integrated in the BUF08800 is also able to use an external voltage divider connected to +IN. It can be used to set the initial VCOM voltage as well as the adjustment range (see Figure 17). Using this method, even at power-on the initial VCOM setting is close to the optimized VCOM value, without any programming. The external voltage divider also limits the adjustment range that typically leads to a smaller number of adjustment steps. In addition, the VCOM output voltage is limited only to the adjustment range, thereby protecting the panel from undesirable VCOM voltages. AVDD RA REPLACEMENT OF TRADITIONAL GAMMA BUFFER Traditional gamma buffers rely on a resistor string (often using expensive 0.1% resistors) to set the gamma voltages. During development, the optimization of these gamma voltages can be time-consuming. Programming these gamma voltages with the BUF08800 can significantly reduce the time required for gamma voltage optimization. The final gamma values can be written into the internal OTP memory to replace a traditional gamma buffer solution. Figure 16a shows the traditional resistor string; Figure 16b shows the more efficient alternative method using the BUF08800. The BUF08800 uses the most advanced high-voltage CMOS process available today, allowing it to be competitive with traditional gamma buffers. Programmability offers the following advantages: RB VCOM RC D D D D Shortens development time significantly. Increases reliability by eliminating more than 18 external components. Eliminates manufacturing variance between panels. Allows a single panel to be built for multiple customers, with loading of customer-dependent gamma curves during final production. This method significantly lowers inventory cost and risk, and simplifies inventory management. Allows demonstration of various gamma curves to LCD monitor makers by simply uploading a different set of gamma values. Figure 15. Traditional VCOM Adjustment. External voltage divider sets initial VCOM voltage as well as adjustment range. The 10-bit DAC acts as a voltage source with a nominal 250kΩ output impedance; see Figure 17. For example, at code 000h, the lowest VCOM voltage is achieved because the 250kΩ impedance is now in parallel with R2, which lowers the impedance of the lower side of the voltage divider. Consequently, code 3FFh results in the highest adjustable VCOM voltage. However, an external voltage divider is not required for correct function of the VCOM channel integrated in the BUF08800. Once the desired output level (that is, minimum flicker) is obtained, the corresponding code can be stored in the external EEPROM memory. D 12 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 a) Traditional Solution BUFxx704 b) BUF08800 Solution BUF08800 VCOM OUT 1 VCOM OUT 2 Timing Controller PC Register SDA SCL OUT 3 Gamma References OUT 7 EEPROM OUT 8 SDA Control Interface SCL LCD Panel Electronics Figure 16. Replacement of the Traditional Gamma Buffer Analog 7V to 18V R1 Code 3FF 10− Bit DAC 250kΩ +IN (VCOM) VCOM/OUT 2 Code 00 R2 − IN (VCOM) BUF08800 Figure 17. Simplified Block Diagram for VCOM Adjustment Using the BUF08800 13 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 DIGITAL GATE-VOLTAGE (VGH, VGL) ADJUSTMENT Different panel sizes and manufacturing technology often require different gate-high (VGH) and gate-low (VGL) voltages. Optimizing the gate-high and -low voltages for best panel performance can be time consuming. Using channels 7 and 8, which are capable of swinging close to GND, allows a wide range of programmable adjustment of both VGL and VGH. This procedure of optimizing VGH and VGL is greatly simplified and the LCD power-supply solution can readily be used in other panels without modification to the hardware. 2. OUT 3 would then form the four upper gamma references and OUT 4 through OUT 8 would be used for the four lower gamma references. Five-channel gamma reference, two-channel gate voltage adjust, one-channel VCOM. For applications that can accept a total of five gamma references, the BUF08800 can be used to digitally adjust the gate voltages. Two channels would be used to adjust VGH and VGL. In this case, the suggested use of channels would be to use OUT 2 through OUT 6 for generating the gamma references and OUT 7 and OUT 8 for generating the VGH and VGL references. OUT 1 would be used as the VCOM channel. Six-channel gamma, one VCOM channel. For applications requiring one VCOM channel and an even number of gamma channels, the BUF08800 would still be a very cost-competitive solution. Channels 2 through 7 would be used to generate the gamma references. TYPICAL APPLICATIONS FOR BUF08800 1. All eight channels are used for gamma correction. The VCOM channel swings very close to VS. It can therefore be used to generate the highest gamma voltage. VCOM (OUT 1) together with OUT 2 and 3. 36V Unregulated VGATE High R Programmable VGATE High VSD VS D VGH = VDIODE + OUT 8 − VBE (NPN) VGATE Adj Register 1 VGATE Adj Register 2 10−Bit DAC OUT 8 10−Bit DAC OUT 7 …… SDA Control IF SCL D 10−Bit DAC VGH = VDIODE + OUT 7 − VBE (NPN) Programmable VGATE Low R BUF08800 Unregulated VGATE Low … A0 Figure 18. Using the BUF08800 to Digitally Adjust the VGH Voltage 14 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 GENERAL POWERPAD DESIGN CONSIDERATIONS The BUF08800 is available in a thermally-enhanced PowerPAD package. This package is constructed using a downset leadframe upon which the die is mounted; see Figure 19(a) and Figure 19(b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 19(c). This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have low power dissipation. This process provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD. 1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as for the thermal pad. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns (2×4) for the HTSSOP-20 DAP package can be seen in the technical brief, PowerPAD ThermallyEnhanced Package (SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them small, so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. The vias help dissipate the heat generated by the BUF08800 IC. The additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered; thus, wicking is not a problem. Connect all holes to the internal plane that is at the same voltage potential as the GND pins. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations, making the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the BUF08800 PowerPAD package should make their connection to the internal plane with a complete connection around the entire circumference of the plated-through hole. The top-side solder mask should leave the terminals of the package and the thermal pad area with its ten holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking prevents solder from being pulled away from the thermal pad area during the reflow process. Apply solder paste to the exposed thermal pad area and all of the IC terminals. With these preparatory steps in place, the BUF08800 IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This preparation results in a properly installed part. 4. 5. 6. 2. 7. 8. 15 BUF08800 www.ti.com SBOS380A − FEBRUARY 2007 − REVISED MAY 2007 DIE Side View (a) DIE End View (b) Exposed Thermal Pad Bottom View (c) Figure 19. Views of Thermally-Enhanced DCP Package For a given qJA, the maximum power dissipation is shown in Figure 20, and is calculated by Equation 3: Maximum Power Dissipation (W) 6 5 4 3 2 1 0 −40 − 20 0 20 40 60 80 100 TA, Free−Air Temperature (_ C) PD + T MAX * T A q JA (2) Where: PD = maximum power dissipation (W) TMAX = absolute maximum junction temperature (+125°C) TA = ambient air temperature (°C) qJA = qJC + qCA qJC = thermal coefficient from junction-to-case (°C/W) qCA = thermal coefficient from case-to-ambient air (°C/W) Figure 20. Maximum Power Dissipation vs Free-Air Temperature (with PowerPAD soldered down) 16 PACKAGE OPTION ADDENDUM www.ti.com 25-Apr-2007 PACKAGING INFORMATION Orderable Device BUF08800AIPWPR BUF08800AIPWPRG4 (1) Status (1) ACTIVE ACTIVE Package Type HTSSOP HTSSOP Package Drawing PWP PWP Pins Package Eco Plan (2) Qty 20 20 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2007 Device Package Pins Site Reel Diameter (mm) 330 Reel Width (mm) 16 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 W Pin1 (mm) Quadrant 16 Q1 BUF08800AIPWPR PWP 20 TAI 6.95 7.1 1.6 TAPE AND REEL BOX INFORMATION Device BUF08800AIPWPR Package PWP Pins 20 Site TAI Length (mm) 346.0 Width (mm) 346.0 Height (mm) 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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