BUF12800
SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
REFERENCE VOLTAGE GENERATOR
for LCD GAMMA CORRECTION
FEATURES
D
D
D
D
D
D
D
D
D
D
D
APPLICATIONS
12-CHANNEL GAMMA CORRECTION
10-BIT RESOLUTION
DOUBLE-BUFFERED DAC REGISTERS
INTEGRATED REFERENCE BUFFERS
RAIL-TO-RAIL OUTPUT
LOW SUPPLY CURRENT: 900µA/ch
SUPPLY VOLTAGE: 7V to 18V
DIGITAL SUPPLY: 2.3V to 5.5V
INDUSTRY-STANDARD TWO-WIRE INTERFACE
− High-Speed Mode: 3.4MHz
HIGH ESD RATING:
− 4kV HBM, 1kV CDM, 200V MM
DEMO BOARD AND SOFTWARE AVAILABLE
V SD
4
VS
REFH
3
1, 2
BUF12800
13
Out A
14
Out B
15
Out C
16
Out D
17
18
DAC Register
DAC Register
Out E
Out F
19
Out G
20
Out H
D TFT-LCD REFERENCE DRIVERS
D REFERENCE VOLTAGE GENERATORS
D INDUSTRIAL PROCESS CONTROL
DESCRIPTION
The BUF12800 is a programmable voltage reference
generator designed for dynamic gamma correction in
TFT-LCD panels. It provides 12 programmable outputs,
each with 10-bit resolution.
TI’s new, small geometry, state-of-the-art, analog CMOS
process allows the use of one digital-to-analog converter
(DAC) per channel while still maintaining a very small chip
size. This topology has the advantage of significantly
increased programming speed over existing programmable buffers.
Programming of each output occurs through an industrystandard, two-wire serial interface. Unlike existing
programmable buffers, the BUF12800 offers a highspeed, two-wire interface mode that allows clock speeds
up to 3.4MHz. The BUF12800 features a double-buffered
DAC register structure that significantly simplifies implementation of dynamic gamma control. This further reduces
programming time, especially when many channels have
to be updated simultaneously.
Reference pins set the high and low voltages of the output
range. They are internally buffered, which simplifies
design. They may be connected to external resistors to
divide the output range for finer resolution of outputs.
The BUF12800 is available in a TSSOP-24 PowerPAD
package. It is specified from −40°C to +85°C.
21
Out I
22
Out J
23
Out K
24
Out L
6
SDA
Control IF
SCL
5
8
LD
7
A0
10
REFL
9
BUF12800 RELATED PRODUCTS
FEATURES
PRODUCT
11-Channel Gamma Correction Buffer, Int VCOM
6-Channel Gamma Correction Buffer, Int VCOM
6-Channel Gamma Correction Buffer
4-Channel Gamma Correction Buffer, Int VCOM
High-Supply Voltage Gamma Buffers
20-Channel Programmable Buffer, 10-Bit, VCOM
BUF11702
BUF07703
BUF06703
BUF05703
BUFxx704
BUF20800
11, 12
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright 2004−2007, Texas Instruments Incorporated
! !
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V
Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Signal Input Terminals, SCL, SDA, AO, LD:
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Output Short-Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 4000V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . 1000V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Short-circuit to ground, one amplifier per package.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
BUF12800
TSSOP-24
PWP
PACKAGE MARKING
BUF12800
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
PIN CONFIGURATION
Top View
TSSOP
VS
1
24
Out L
VS
2
23
Out K
REFH(2)
3
22
Out J
VSD
4
21
Out I
SCL
5
20
Out H
SDA
6
19
Out G
A0
7
18
Out F
LD
8
17
Out E
GNDD(1)
9
16
Out D
REFL(2)
10
15
Out C
GNDA(1)
11
14
Out B
GNDA(1)
12
13
Out A
PowerPAD
Lead−Frame
Die Pad
Exposed on
Underside
(1) GNDD and GNDA are internally connected and must be at the same voltage potential.
(2) Connecting a capacitor to this node is not recommended.
2
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = −40°C to +85°C.
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
BUF12800
PARAMETER
ANALOG
Buffer Output Swing—High
Buffer Output Swing—Low
Buffer Output Reset and Power-Up Value
Buffer A
Buffer B
Buffer C
Buffer D
Buffer E
Buffer F
Buffer G
Buffer H
Buffer I
Buffer J
Buffer K
Buffer L
REFH Input Range
REFL Input Range
Integral Nonlinearity
Differential Nonlinearity
Gain Error
Program to Out Delay
Output Accuracy
vs Temperature
Input Resistance at VREFH and VREFL
Load Regulation, 10mA, All Buffers
50mA, Buffers A-F
ANALOG POWER SUPPLY
Operating Voltage Range
Total Analog Supply Current
over Temperature
DIGITAL
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic 0 Output Voltage
Input Leakage
Clock Frequency
DIGITAL POWER SUPPLY
Operating Voltage Range
Digital Supply Current(1)
over Temperature
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance, TSSOP-24(2)
Junction-to-Ambient
Junction-to-Case
CONDITIONS
MIN
TYP
MAX
UNIT
Buffers A-F, Code = 1023, Sourcing 10mA, VREFH = 17.8
Buffers G-L, Code = 1023, Sourcing 10mA, VREFH = 17.8
Buffers A-F, Code = 0, Sinking 10mA, VREFL = 0.2
Buffers G-L, Code = 0, Sinking 10mA, VREFL = 0.2
17.7
16.3
17.8
16.98
1.0
0.2
1.1
0.3
V
V
V
V
Code 3E0h
Code 360h
Code 320h
Code 300h
Code 2C0h
Code 240h
(11 1110 0000)
(11 0110 0000)
(11 0010 0000)
(11 0000 0000)
(10 1100 0000)
(10 0100 0000)
16.452
14.450
13.450
12.952
11.952
9.950
16.502
14.500
13.500
13.002
12.002
10.000
16.552
14.550
13.550
13.052
12.052
10.050
V
V
V
V
V
V
Code 1C0h
Code 140h
Code 100h
Code 0E0h
Code 0A0h
Code 020h
(01 1100 0000)
(01 0100 0000)
(01 0000 0000)
(00 1110 0000)
(00 1010 0000)
(00 0010 0000)
7.955
5.958
4.957
4.459
3.457
1.457
8.005
6.008
5.007
4.509
3.507
1.507
8.055
6.058
5.057
4.559
3.557
1.557
V
V
V
V
V
V
VS − 0.2
VS − 4
4
0.2
INL
DNL
tD
VREFH and VREFL Held Constant
RINH
REG
VS
IS
VOUT = VS/2, IOUT = +5mA to −5mA Step
VOUT = VS/2, ISINKING = 50mA, ISOURCING = 50mA
0.3
0.3
0.12
5
±20
±25
100
0.5
0.5
±50
1.5
1.5
V
V
Bits
Bits
%
µs
mV
µV/°C
MΩ
mV/mA
mV/mA
9
18
15
15
V
mA
mA
0.3(VSD)
0.4
±10
400
3.4
V
V
V
µA
kHz
MHz
7
Outputs at Reset Values, No Load
0.7(VSD)
ISINK = 3mA
fCLK
VSD
ISD
0.15
±0.01
Standard/Fast Mode
High-Speed Mode
2.3
Outputs at Reset Values, No-Load, Two-Wire Bus Inactive
Junction Temperature < +125°C
qJA
qJC
25
100
−40
−40
−65
30.13
0.92
5.5
50
V
µA
µA
+85
+95
+150
°C
°C
°C
°C/W
°C/W
(1) See the typical characteristic Digital Supply Current vs Two-Wire Bus Activity.
(2) PowerPAD attached to PCB, 0lfm airflow, and 76mm x 76mm copper area.
3
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
ANALOG SUPPLY CURRENT vs TEMPERATURE
DIGITAL SUPPLY CURRENT vs TEMPERATURE
10
30
VS = 10V
VS = 18V
25
8
VSD = 5V
20
6
IQ (µA)
I Q (mA)
VS = 10V
15
VSD = 3.3V
4
10
2
5
0
0
−40
−20
0
20
40
60
80
−40
100
−20
0
20
40
60
Temperature (_ C)
Temperature (_ C)
Figure 1
Figure 2
FULL−SCALE OUTPUT SWING
100
OUTPUT VOLTAGE vs OUTPUT CURRENT
18
Channels A−F (sourcing), Code = 3FFh
REFH = 17V
REFL = 1V
VREFL = 1V, VREFH = 17.8V
RLOAD Connected to GND
Output Voltage (V)
17
Output Voltage (5V/div)
80
Code 3FF →000
Code 000 →3FF
Channels G−L (sourcing),
Code = 3FFh, VREFL = 0.2V,
16
VREFH = 17V, RLOAD Connected to GND
2
Channels A−F (sinking), Code = 000h,
VREFL = 1V, VREFH = 17.8V,
RLOAD Connected to 18V
Channels G−L (sinking),
Code = 000h, VREFL = 0.2V,
VREFH = 17V, RLOAD Connected to 18V
1
0
Time (1µs/div)
0
20
40
60
80
100
Output Current (mA)
Figure 3
Figure 4
DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.4
0.4
DNL Error (LSB)
INL Error (LSB)
INTEGRAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.2
0
−0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
0
200
400
600
Input Code
Figure 5
4
0.2
800
1000
0
200
400
600
Input Code
Figure 6
800
1000
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
Each buffer is capable of full-scale change in output
voltage in less than 4µs; see Figure 4, typical
characteristic Full-Scale Output Swing.
APPLICATIONS INFORMATION
The BUF12800 programmable voltage reference allows fast
and easy adjustment of 12 programmable reference outputs,
each with 10-bit resolution.
It allows very simple,
time-efficient adjustment of the gamma reference voltages.
The BUF12800 is programmed through a high-speed
standard two-wire interface. The BUF12800 features a
double-register structure for each DAC channel to simplify
the implementation of dynamic gamma control (see the
Dynamic Control section). This allows pre-loading of register
data and rapid updating of all channels simultaneously.
The BUF12800 uses an analog supply of 7V to 18V and a
digital supply of 2.3V to 5.5V. The digital supply must be
applied prior to or simultaneously with the analog supply
to avoid excessive current and power consumption;
damage to the device may occur if it is left connected only
to the analog supply for an extended time.
Figure 7 shows the BUF12800 in a typical configuration.
In this configuration, the BUF12800 device address is 74h.
The output of each DAC is immediately updated as soon
as data are received in the corresponding register (LD = 0).
For maximum dynamic range, set VREFH = VS − 0.2V and
VREFL = VS + 0.2V.
Buffers A−F are able to swing to within 300mV of the
positive supply rail, and to within 1.1V of the negative
supply rail. Buffers G−L are able to swing to within 1.7V
of the positive supply rail, and to within 300mV of the
negative supply rail. (See the Electrical Characteristics
table for further information).
BUF12800
(1)
1
VS
Out L
24
2
VS
Out K
23
3
REFH
Out J
22
4
VDS
Out I
21
5
SCL
Out H
20
6
SDA
Out G
19
7
A0
Out F
18
8
LD
Out E
17
9
GNDD(2)
Out D
16
10 REFL
Out C
15
11 GNDA(2)
Out B
14
12 GNDA(2)
Out A
13
Source
Driver
VS
10µF
100nF
3.3V
1µF
(1)
(1)
100nF
(1)
Timing
Controller
VS
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1) RC combination optional.
(2) GNDD and GNDA are internally connected and must be at the same voltage potential.
Figure 7. Typical Application Configuration
5
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
TWO-WIRE BUS OVERVIEW
acknowledge this byte; the communication protocol prohibits
acknowledgment of the Hs master code. On receiving a
master code, the BUF12800 will switch on its Hs mode filters,
and communicate at up to 3.4MHz. Additional high-speed
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The
BUF12800 will switch out of Hs mode at the first occurrence
of a STOP condition.
The BUF12800 communicates through an industry-standard, two-wire interface to receive data in slave mode. This
standard uses a two-wire, open-drain interface that supports
multiple devices on a single bus. Bus lines are driven to a
logic low level only. The device that initiates the
communication is called a master, and the devices controlled
by the master are slaves. The master generates the serial
clock on the clock signal line (SCL), controls the bus access,
and generates the START and STOP conditions.
GENERAL CALL RESET AND POWER-UP
To address a specific device, the master initiates a START
condition by pulling the data signal line (SDA) from a HIGH
to LOW logic level while SCL is HIGH. All slaves on the bus
shift in the slave address byte, with the last bit indicating
whether a read or write operation is intended. During the
ninth clock pulse, the slave being addressed responds to
the master by generating an Acknowledge and pulling
SDA LOW.
The BUF12800 responds to a General Call Reset, which is
an address byte of 00h (0000 0000) followed by a data byte
of 06h (0000 0110). The BUF12800 acknowledges both
bytes. Upon receiving a General Call Reset, the BUF12800
performs a full internal reset, as though it had been powered
off and then on. It always acknowledges the General Call
address byte of 00h (0000 0000), but does not acknowledge
any General Call data bytes other than 06h (0000 0110).
Data transfer is then initiated and 8 bits of data are sent
followed by an Acknowledge Bit. During data transfer,
SDA must remain stable while SCL is HIGH. Any change
in SDA while SCL is HIGH will be interpreted as a START
or STOP condition.
When the BUF12800 powers up, it automatically performs
a reset. As part of the reset, the BUF12800 is configured
based on the codes shown in Table 1.
Once all data has been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The BUF12800 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the BUF12800.
ADDRESSING THE BUF12800
The address of the BUF12800 is 111010x, where x is the
state of the A0 pin. When the A0 pin is LOW, the device will
acknowledge on address 74h (1110100). If the A0 pin is
HIGH, the device will acknowledge on address 75h
(1110101).
Other valid addresses are possible through a simple mask
change. Contact your TI representative for information.
DATA RATES
The two-wire bus operates in one of three speed modes:
D Standard: allows a clock frequency of up to 100kHz;
D Fast: allows a clock frequency of up to 400kHz; and
D High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz.
The BUF12800 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of
00001xxx, with SCL = 400kHz, following the START
condition; xxx are bits unique to the Hs-capable master,
which can be any value. The BUF12800 will respond to the
High-speed mode command regardless of the value of these
last three bits. This byte is called the Hs master code. (Note
that this is different from normal address bytes—the low bit
does not indicate read/write status.) The BUF12800 will not
6
Table 1. BUF12800 Reset Codes
RESET CODES
BUFFER
BUFFER A
BUFFER B
BUFFER C
BUFFER D
BUFFER E
BUFFER F
BUFFER G
BUFFER H
BUFFER I
BUFFER J
BUFFER K
BUFFER L
(Hex)
(Decimal)
(Binary)
Code 3E0
Code 360
Code 320
Code 300
Code 2C0
Code 240
Code 1C0
Code 140
Code 100
Code 0E0
Code 0A0
Code 020
992
864
800
768
704
576
448
320
256
224
160
32
11 1110 0000
11 0110 0000
11 0010 0000
11 0000 0000
10 1100 0000
10 0100 0000
01 1100 0000
01 0100 0000
01 0000 0000
00 1110 0000
00 1010 0000
00 0010 0000
Buffer values are calculated using Equation 1:
V OUT +
ƪ
V REFH * V REFL
1024
ƫ
decimal value of code ) V REFL
(1)
Other reset values are available as a custom
modification—contact your TI representative for details.
OUTPUT VOLTAGE
Buffer output values are determined by the reference
voltages (VREFH and VREFL) and the decimal value of the
binary input code used to program that buffer. The value is
calculated using Equation 1; see the Reset and Power-Up
section. The valid voltage ranges for the reference
voltages are:
4V v VREFH v VS * 0.2V and 0.2V v V REFL v V S * 4V
The BUF12800 outputs are capable of a full-scale voltage
output change in less than 4µs—no intermediate steps are
required.
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
READ/WRITE OPERATIONS
The BUF12800 is able to read from a single DAC or
multiple DACs, or write to the register of a single DAC, or
multiple DACs in a single communication transaction.
DAC addresses begin with 0000, which corresponds to
DAC_A, through 1011, which corresponds to DAC_L.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH will perform a read
transaction.
5.
bytes are for DAC_L. The DAC register is updated
after receiving the 24th byte. For each DAC, begin by
sending the most significant byte (bits D15−D8, of
which only bits D9 and D8 have meaning), followed by
the least significant byte (bits D7−D0).
Send a STOP condition on the bus.
Writing
The BUF12800 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DACs that have received both bytes will be
updated.
To write to a single DAC register:
Reading
1.
2.
Send a START condition on the bus.
Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
To read the register of one DAC:
3.
Send a DAC address byte. Bits D7−D4 are unused
and should be set to 0. Bits D3−D0 are the DAC
address. Only DAC addresses 0000 to 1011 are valid
and will be acknowledged.
4.
5.
Send two bytes of data for the specified DAC. Begin
by sending the most significant byte first (bits D15−D8,
of which only bits D9 and D8 are used), followed by the
least significant byte (bits D7−D0). The DAC register
is updated after receiving the second byte.
Send a STOP condition on the bus.
The BUF12800 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register will not be updated. Updating the DAC register is
not the same as updating the DAC output voltage. See the
Output Latch section.
The process of updating multiple registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master will continue to send data
for the next register. The BUF12800 will automatically and
sequentially step through subsequent registers as additional data is sent. The process will continue until all desired registers have been updated or a STOP condition is
sent.
To write to multiple registers:
1.
2.
3.
4.
Send a START condition on the bus.
Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
Send either the DAC_A address byte to start at the
first DAC or send the address of whichever DAC will
be the first to be updated. The BUF12800 will begin
with this DAC and step through subsequent DACs in
sequential order.
Send the bytes of data. The first two bytes are for the
DAC addressed in step 3. Its register is automatically
updated after receiving the second byte. The next two
bytes are for the following DAC. The DAC register is
updated after receiving the fourth byte. The last two
1.
2.
7.
Send a START condition on the bus.
Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
Send a DAC address byte. Bits D7−D4 have no
meaning; Bits D3−D0 are the DAC address. Only DAC
addresses 0000 to 1011 are valid and will be
acknowledged.
Send a START or STOP/START condition on the bus.
Send correct device address and read/write
bit = HIGH. The BUF12800 will acknowledge this
byte.
Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8, of which only bits D9 and D8 have
meaning); the next is the least significant byte (bits
D7−D0).
Acknowledge after receiving each byte.
8.
Send a STOP condition on the bus.
3.
4.
5.
6.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
To read multiple DAC registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF12800 will acknowledge this byte.
3. Send either the DAC_A address byte to start at the
first DAC or send the address byte for whichever DAC
will be the first in the sequence of DACs to be read.
The BUF12800 will begin with this DAC and step
through subsequent DACs in sequential order.
4. Send the device address and read/write bit = HIGH.
5. Receive bytes of data. The first two bytes are for the
specified DAC. The first received byte is the most
significant byte (bits D15−D8, of which only bits D9
and D8 have meaning). The next byte is the least
significant byte (bits D7−D0).
6. Acknowledge after receiving each byte.
7. When all desired DACs have been read, send a STOP
or START condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
7
8
Figure 8. Write Single DAC Register
A6
A6
SDA_In
Start
Device_Out
SCL
A6
Device_Out
A5
A5
A4
A4
A3
A3
A2
A2
A5
A5
A4
A4
A3
A3
A2
A2
Device Address
A1
A1
A0
A0
A1
A1
W
W
Read Operation
A0
A0
Ackn
Ackn
D7
D7
D6
D6
D5
D5
D4
D4
W
W
Ackn
Ackn
D7
D7
D6
D6
D5
D5
D4
D4
P3
P3
P2
P2
P1
P1
P0
P0
P2
P2
P1
P1
P0
P0
Ackn
Ackn
Ackn
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
Ackn
Ackn
Start
A6
A6
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A1
A1
A0
A0
R
R
Ackn
Ackn
Read Ackn
D8
D8
Ackn
Ackn
Ackn
D7
D7
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
DACMSbyte. D15 −D10 have no meaning.
D9
D9
DAC MSbyte. D14 −D10 have no meaning.
If D15 = 0, the DACs are updated on the Latch pin.
If D15 = 1, all DACs are updated when the current DAC register is updated.
P3
P3
DAC address pointer. D7 −D4 have no meaning.
Write Operation
Write Ackn
Write Ackn DAC address pointer. D7 −D4 have no meaning. Ackn
Read single DAC register. P3 −P0 specify DAC address.
A6
SDA_In
SCL
Device Address
Write single DAC register. P3 −P0 specify the DAC address.
Start
D8
D8
Ackn
Ackn
Ackn
D6
D6
D7
D7
D5
D5
D6
D6
D4
D4
D5
D5
D1
D1
D0
D0
Ackn
Ackn
Ackn
Stop
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
No Ackn
Stop
No Ackn
The whole DAC Register D9 −D0
is updated in this moment.
D2
D2
DACLSbyte
D3
D3
DAC LSbyte
"#$%&''
SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
www.ti.com
TIMING DIAGRAMS
Figure 9. Read Single DAC Register
Figure 10. Write Multiple DAC Registers
A6
A6
Device_Out
Start
SDA_In
SCL
A6
Device_Out
A5
A5
A4
A4
A3
A3
A2
A2
Device Address
A1
A1
A0
A0
A5
A5
A4
A4
A3
A3
A2
A2
Device Address
A1
A1
A0
A0
Write Operation
W
W
Ackn
Ackn
Ackn
Ackn
D7
D7
D6
D6
D5
D5
D4
D4
P3
P3
P2
P2
P1
P1
D6
D6
D7
D7
D5
D5
D4
D4
P3
P3
P2
P2
P1
P1
P0
P0
D15
D12
D11
D10
D10
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
A6
A6
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
D9
D9
D8
D8
A1
A1
D15
…
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
DAC(11) MSbyte. D15 −D10 have no meaning.
D15
Ackn
D14
D14
Start
…
…
…
P0
Ackn
D13
D11
D8
D8
Ackn
Ackn
D7
D7
D6
D6
Ackn
Ackn
Ackn
D7
D7
D6
D6
D5
D5
D8
D8
Ackn
Ackn
Ackn
A0
A0
R
R
D7
D7
Ackn
Ackn
Read Ackn
D5
D15
D6
D4
D4
D3
D3
D1
D1
D0
D0
D13
D13
D12
D12
D5
D5
D4
D4
D3
D3
DAC(11) LSbyte
D14
D14
A ckn
A ckn
D1
D1
D0
D0
Ackn
Ackn
Ackn
Stop
D2
D2
D11
D11
D1
D1
D10
D10
D0
D0
Ackn
D9
D9
D8
D8
Stop
…
…
…
…
…
…
…
…
The whole DAC Register D9 −D0
is updated in this moment.
D2
D2
The whole DAC Register D9 −D0
is updated in this moment.
D2
D2
D3
D3
DAC(pointer) MSbyte. D15 −D10 have no meaning.
D15
D6
D4
D4
Ackn
DAC(pointer+1) MSbyte.
D14 −D10 have no meaning.
DAC(pointer) LSbyte
DAC(11) LSbyte
D5
If D15 = 0, the DACs are updated on the Latch pin.
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
…
Ackn
D14
D12
Ackn
If D15 = 0, the DACs are updated on the Latch pin.
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D13
DAC(11) MSbyte. D14 −D10 have no meaning.
Ackn
D14
DAC(pointer) MSbyte. D14 −D10 have no meaning.
Ackn D15
…
…
…
P0
Start DAC address pointer. D7 −D4 have no meaning.
Read operation
W
W
Write Ackn Start DAC address pointer. D7 −D4 have no meaning. Ackn
Write Ackn
Read multiple DACregisters. P3 −P0 specify start DACaddress.
A6
Start
SDA_In
SCL
Write multiple DAC registers. P3 −P0 specify start DAC addre ss.
"#$%&''
www.ti.com
SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
Figure 11. Read Multiple DAC Registers
9
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
Table 2. BUF12800 Bus Address Options
OUTPUT LATCH
Because the BUF12800 features a double-buffered
register structure, updating the DAC register is not the
same as updating the DAC output voltage. There are three
methods for latching transferred data from the storage
registers into the DACs to update the DAC output voltage.
Method 1 requires externally setting the latch pin low,
LD = LOW, which will update each DAC output voltage
whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC
output voltages to retain their values during data transfer
and until LD = LOW, which will simultaneously update the
output voltages of all 12 DACs to the new register values.
Method 3 uses software control. LD is maintained HIGH,
and all 12 DACs are updated when the master writes a ‘1’
in bit 15 of any DAC register. The update will occur after
receiving the 16-bit data for the currently-written register.
Use methods 2 and 3 to transfer a future data set into the
first bank of registers in advance to prepare for a very fast
update of DAC output voltages.
The General Call Reset and the power-up reset will update
the DACs regardless of the state of the latch pin.
BUF12800 ADDRESS
ADDRESS
A0 Pin is LOW
(device will acknowledge on address 74h)
111 0100
A0 Pin is HIGH
(device will acknowledge on address 75h)
111 0101
Table 3. Quick-Reference Table of DAC
Addresses
DAC
ADDRESS
DAC A
0000 0000
DAC B
0000 0001
DAC C
0000 0010
DAC D
0000 0011
DAC E
0000 0100
DAC F
0000 0101
DAC G
0000 0110
DAC H
0000 0111
DAC I
0000 1000
DAC J
0000 1001
DAC K
0000 1010
DAC L
0000 1011
Table 4. Quick-Reference Table of Commands
10
COMMAND
CODE
General Call Reset
Address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110).
High-Speed Mode
00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master.
This byte is called the Hs master code.
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to improve
the picture quality in LCD TV applications. The brightness
in each picture frame is analyzed and the gamma curves
are adjusted on a frame-by-frame basis. The gamma
curves are typically updated during the short vertical
blanking period in the video signal. Figure 12 shows a
block diagram using the BUF12800 for dynamic gamma
control.
The BUF12800 is ideally suited for rapidly changing the
gamma curves due to its unique topology:
a picture is still being displayed. Because the data is only
stored into the first register bank, the DAC output values
remain unchanged—the display is unaffected. During the
vertical sync period, the DAC outputs (and therefore, the
gamma voltages) can be quickly updated either by using
an additional control line connected to the LD pin, or
through software—writing a ‘1’ in bit 15 of any DAC
register. For details on the operation of the double register
input structure, see the Output Latch section.
Example: Update all 12 registers simultaneously via
software.
Step 1: Check if LD pin is placed in HIGH state.
•
double register input structure to the DAC
•
fast serial interface
•
simultaneous updating of all DACs by software.
See the Read/Write Operations to write to all
registers and Output Latch sections.
Step 2: Write DAC Registers 1−12 with bit 15 always 0.
Step 3: Write any DAC register a second time with
identical data. Make sure that bit 15 is ‘1’. All DAC
channels will be updated simultaneously after receiving
the last bit of data.
The double register input structure saves programming
time by allowing updated DAC values to be pre-stored into
the first register bank. Storage of this data can occur while
Histogram
Gamma
Adjustment
Algorithm
Digital
Picture
Data
Black
White
SDA
SCL
BUF12800
Gamma References
A through L
Timing Controller/µController
Source Driver
Source Driver
Figure 12. Dynamic Gamma Control
11
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
REPLACEMENT OF TRADITIONAL GAMMA
BUFFER
BUF12800 uses the most advanced high-voltage CMOS
process available today, which allows it to be competitive
with traditional gamma buffers.
Traditional gamma buffers rely on a resistor string (often
using expensive 0.1% resistors) to set the gamma
voltages. During development, the optimization of these
gamma voltages can be time consuming. Programming
these gamma voltages with the BUF12800 can
significantly reduce the time required for gamma voltage
optimization. The final gamma values can be written into
an external EEPROM to replace a traditional gamma
buffer solution. During power-up of the LCD panel, the
timing controller can read the EEPROM and load the
values into the BUF12800 to generate the desired gamma
voltages. Figure 13a shows the traditional resistor string;
Figure 13b shows the more efficient alternative method
using the BUF12800.
a) Traditional
This technique offers significant advantages:
•
It shortens development time significantly.
•
It allows demonstration of various gamma curves
to LCD monitor makers by simply uploading a
different set of gamma values.
•
It allows simple adjustment of gamma curves
during production to accommodate changes in
the panel manufacturing process.
•
It decreases cost and space.
b) BUF12800 Solution
BUFxx704
BUF12800
Timing
Controller
Out A
PC
SDA
Out B
Register
SCL
EEPROM
Out K
Out L
SDA
Control Interface
SCL
LCD Panel Electronics
Figure 13. Replacement of Traditional Gamma Buffer
12
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
PROGRAMMABLE VCOM
REFH AND REFL INPUT RANGE
Channels A−F of the BUF12800 can drive more than
100mA up to 2V to the supply rails (see Figure 4, typical
characteristic Output Voltage vs Output Current).
Therefore, any of these channels can be used to drive the
VCOM node on the LCD panel. To store the gamma and the
VCOM values, an external EEPROM is required. During
power-up of the LCD panel, the timing controller can then
read the EEPROM and load the values into the BUF12800
to generate the desired gamma voltages as well as VCOM
voltages. Figure 14 shows channels A and B of the
BUF12800 being used for VCOM voltages.
Best performance and output swing range of the
BUF12800 are achieved by applying REFH and REFL
voltages that are slightly below the power-supply
voltages. Most specifications have been tested at
REFH = VS − 200mV and REFL = GND + 200mV. The
REFH internal buffer is designed to swing very closely to
VS and the REFL internal buffer to GND. However, there
is a finite limit on how close they can swing before
saturating. To avoid saturation of the internal REFH and
REFL buffers, the REFH voltage should not be greater
than VS − 100mV and REFL voltage should not be lower
than GND + 100mV. The other consideration when trying
to maximize the output swing capability of the gamma
buffers is the limitation in the swing range of output buffers
(OUT A−L), which depends on the load current. A typical
load in the LCD application is 5−10mA. For example, if
OUT A is sourcing 10mA, the swing is typically limited to
about VS − 200mV. The same applies to OUT L, which
typically limits at GND + 200mV when sinking 10mA. An
increase in output swing can only be achieved for much
lighter loads. For example, a 3mA load typically allows the
swing to be increased to approximately VS − 100mV and
GND + 100mV.
BUF12800
Out A
VCOM
Out B
Register
Out C
Out D
Gamma
References
Out K
Out L
Connecting REFH directly to VS and REFL directly to GND
does not damage the BUF12800. However, as discussed
above, the output stages of the REFH and REFL buffers
will saturate. This condition is not desirable and can result
in a small error in the measured output voltages of OUT
A−L. As described above, this method of connecting
REFH and REFL does not help to maximize the output
swing capability.
SDA
Control Interface
SCL
Figure 14. BUF12800 Used for Programmable
VCOM
13
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
INDEPENDENTLY PROGRAMMABLE RGB
GAMMA: BUF20800
Some very high resolution LCD screens require the
adjustment of the gamma voltages for each color
(Red—R, Green—G, Blue—B). The BUF20800 offers 20
programmable gamma channels. By using 6 channels for
each color, 18 channels would be used in total for adjusting
the gamma. In addition to those, 1 or 2 channels could be
used to program VCOM.
TOTAL TI PANEL SOLUTION
In addition to the BUF12800 programmable voltage
reference, TI offers a complete set of ICs for the LCD
panel market, including gamma correction buffers,
source and gate drivers, timing controllers, various
power-supply solutions, and audio power solutions.
Figure 15 shows the total IC solution from TI.
Reference
VCOM
Gamma Correction
BUF12800
2.7 V−5 V
TPS65140
TPS65100
LCD
Supply
15 V
26 V
−14 V
3.3 V
TPA3005D2
TPA3008D2
Audio
Speaker
Driver
n
Logic and
Timing
Controller
Gate Driver
Source Driver
High−Resolution
TFT−LCS Panel
Figure 15. TI LCD Solution
14
n
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
BUF12800 IN INDUSTRIAL APPLICATIONS
Figure 16 provides ideas on how the BUF12800 can be
used in an application. A microcontroller with a two-wire
serial interface controls the various DACs of the
BUF12800. The BUF12800 can be used for:
The wide supply range, high output current and very low
cost make the BUF12800 attractive for a range of medium
accuracy industrial applications such as programmable
power supplies, multi-channel data-acquisition systems,
data loggers, sensor excitation and linearization,
power-supply generation, and others. Each DAC channel
features 1LSB DNL and INL.
D
D
D
D
D
D
Many systems require different levels of biasing and power
supply for various components as well as sensor
excitation, control-loop set-points, voltage outputs, current
outputs, and other functions. The BUF12800, with its 12
programmable DAC channels, provides great flexibility to
the whole system by allowing the designer to change all
these parameters via software.
+18V
sensor excitation
programmable bias/reference voltages
variable power-supplies
high-current voltage output
4-20mA output
set-point generators for control loops.
NOTE: At power-up the output voltages of the BUF12800
DACs are pre-defined by the codes in Table 1. Therefore,
each DAC voltage will be set to a different level at
power-up or reset.
+5V
BUF1 2 8 0 0
Voltage
Output
High Current
Voltage Output
0.3V to 17V
+5V
2V to 16V, 100mA
Sensor Excitation/Linearization
Control Loop
Set Point
4−20mA
+5V
Bias Voltage
Generator
4−20mA
Generator
+2.5V Bias
LED Driver
Offset
Adjustment
INA
Ref
+4V
+4.3V
Comparator
Threshold
Supply Voltage
Generator
Ref
Reference
for MDAC
SOA SCL
+7.5V
MDAC
µC
Figure 16. Industrial Application Ideas
15
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
GENERAL PowerPAD DESIGN
CONSIDERATIONS
The BUF12800 is available in the thermally-enhanced
PowerPAD package. This package is constructed using
a downset leadframe upon which the die is mounted, as
shown in Figure 17(a) and (b). This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package; see Figure 17(c).
Due to this thermal pad having direct thermal contact
with the die, excellent thermal performance is achieved
by providing a good thermal path away from the thermal
pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper
area, heat can be conducted away from the package
into either a ground plane or other heat-dissipating
device. Soldering the PowerPAD to the PCB is
always required, even with applications that have
low power dissipation. This provides the necessary
thermal and mechanical connection between the lead
frame die pad and the PCB.
The PowerPAD must be connected to the device’s most
negative supply voltage, GNDA and GNDD.
1. Prepare the PCB with a top-side etch pattern. There
should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal
pad. Ideal thermal land size and thermal via patterns
(2x4) can be seen in the technical brief, PowerPAD
Thermally-Enhanced Package (SLMA002), available for download at www.ti.com. These holes
should be 13 mils (0.330mm) in diameter. Keep
them small, so that solder wicking through the holes
is not a problem during reflow.
16
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the
BUF12800 IC. These additional vias may be larger
than the 13-mil diameter vias directly under the
thermal pad. They can be larger because they are
not in the thermal pad area to be soldered; thus,
wicking is not a problem.
4. Connect all holes to the internal plane that is at the
same voltage potential as the GND pins.
5. When connecting these holes to the internal plane,
do not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This
makes the soldering of vias that have plane
connections easier. In this application, however, low
thermal resistance is desired for the most efficient
heat transfer. Therefore, the holes under the
BUF12800 PowerPAD package should make their
connection to the internal plane with a complete
connection around the entire circumference of the
plated-through hole.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its
eight holes exposed. The bottom-side solder mask
should cover the holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the
BUF12800 IC is simply placed in position and run
through the solder reflow operation as any standard
surface-mount component. This preparation results
in a properly installed part.
"#$%&''
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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007
Exposed Thermal Pad
DIE
Side View (a)
DIE
End View (b)
Bottom View (c)
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 17. Views of Thermally-Enhanced DGN Package
PD +
ǒT
* TA
q JA
MAX
Ǔ
Where:
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature (125°C)
TA = free-ambient air temperature (°C)
qJA = qJC + qCA
6
Maximum Power Dissipation (W)
For a given qJA, the maximum power dissipation is
shown in Figure 18, and is calculated by the following
formula:
5
4
3
2
1
0
−40
−20
0
20
40
60
80
100
TA, Free−Air Temperature (_C)
qJC = thermal coefficient from junction to case (°C/W)
qCA = thermal coefficient from case-to-ambient air (°C/W)
Figure 18. Maximum Power Dissipation vs FreeAir Temperature (with PowerPAD soldered down)
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BUF12800AIPWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BUF12800
BUF12800AIPWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BUF12800
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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