BUF20800AIDCPR

BUF20800 SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 18-Channel GAMMA VOLTAGE GENERATOR with Two Programmable VCOM Channels FEATURES D D D D D D D D D 18-CHANNEL GAMMA CORRECTION D 2-CHANNEL PROGRAMMABLE VCOM: 100mA IOUT 10-BIT RESOLUTION RAIL-TO-RAIL OUTPUT LOW SUPPLY CURRENT: 900µA/ch SUPPLY VOLTAGE: 7V to 18V DIGITAL SUPPLY: 2.0V to 5.5V INDUSTRY-STANDARD, TWO-WIRE INTERFACE: 3.4MHz High-Speed Mode HIGH ESD RATING: 4kV HBM, 1kV CDM, 200V MM DEMO BOARD AND SOFTWARE AVAILABLE Analog (7V to 18V) Digital (2.0V to 5.5V) REFH APPLICATIONS D REPLACES RESISTOR-BASED GAMMA SOLUTIONS D TFT-LCD REFERENCE DRIVERS D DYNAMIC GAMMA CONTROL DESCRIPTION The BUF20800 is a programmable voltage reference generator designed for gamma correction in TFT-LCD panels. It provides 18 programmable outputs for gamma correction and two channels for VCOM adjustment, each with 10-bit resolution. This programmability replaces the traditional, timeconsuming process of changing resistor values to optimize the various gamma voltages and allows designers to determine the correct gamma voltages for a panel very quickly. Required changes can also be easily implemented without hardware changes. The BUF20800 uses TI’s latest, small-geometry analog CMOS process, which makes it a very competitive choice for full production, not just evaluation. Programming of each output occurs through an industrystandard, two-wire serial interface. Unlike existing programmable buffers, the BUF20800 offers a high-speed mode that allows clock speeds up to 3.4MHz. For lower channel count, please contact your local sales or marketing representative. The BUF20800 is available in an HTSSOP-38 PowerPAD package. It is specified from −40°C to +85°C. BUF20800 REFH OUT VCO M OUT1 VCO M OUT2 DAC Registers DAC Registers OUT 1 OUT 2 … … 18 Output Channels plus Two VCOM Channels OUT 17 BUF20800 RELATED PRODUCTS FEATURES PRODUCT BUF20820 BUF12800 BUF01900 BUFxx704 SN10501 TPS65100 18-Channel Programmable, Two VCOM + OTP Memory 12-Channel Programmable Buffer, 10-Bit Programmable VCOM 11-, 6-, 4-Channel Gamma Correction Buffer, 18V Supply High-Speed VCOM, 1 and 2 Channels Complete LCD DC/DC Solution OUT 18 REFL OUT SDA Control IF SCL LD AO REFL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2005−2006, Texas Instruments Incorporated www.ti.com BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +19V Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Signal Input Terminals, SCL, SDA, AO, LD: Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Short Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Short-circuit to ground, one amplifier per package. ORDERING INFORMATION(1) PRODUCT BUF20800 PACKAGE-LEAD HTSSOP-38 PACKAGE DESIGNATOR DCP PACKAGE MARKING BUF20800 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = −40°C to +85°C. At TA = +25°C, VS = 18V, VSD = 5V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. BUF20800 PARAMETER ANALOG Gamma Output Swing—High Gamma Output Swing—Low VCOM Buffer Output Swing—High VCOM Buffer Output Swing—Low Output Current(1) REFH Input Range(2) REFL Input Range(2) Integral Nonlinearity Differential Nonlinearity Gain Error Program to Out Delay Output Accuracy Over Temperature Input Resistance at VREFH and VREFL Load Regulation, All References 40mA, All Channels ANALOG POWER SUPPLY Operating Range Total Analog Supply Current over Temperature DIGITAL Logic 1 Input Voltage Logic 0 Input Voltage Logic 0 Output Voltage Input Leakage Clock Frequency DIGITAL POWER SUPPLY Operating Voltage Range Digital Supply Current(3) over Temperature TEMPERATURE Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Resistance, HTSSOP-38 Junction-to-Ambient Junction-to-Case CONDITIONS OUT 1−9, Sourcing 10mA, VREFH = 17.8V, Code 1023 OUT 10−18, Sourcing 10mA, VREFH = 17.8V, Code 1023 OUT 1−9, Sinking 10mA, VREFL = 0.2V, Code 00 OUT 10−18, Sinking 10mA, VREFL = 0.2V, Code 00 VCOM, Sourcing 100mA, VREFH = 17.8V VCOM, Sinking 100mA, VREFL = 0.2V All Channels, Code 512, Sinking/Sourcing MIN 17.7 17.0 TYP 17.8 17.2 0.6 0.2 15.5 1 45 MAX UNIT V V V V V V mA V V Bits Bits % µs mV mV MΩ mV/mA mV/mA V mA mA V V V µA kHz MHz V µA µA °C °C °C °C/W °C/W 1.0 0.3 2.0 VS VS − 4 1.5 1 13 40 4 GND IO INL DNL tD No Load, VREFH = 17V, VREFL = 1V No Load, VREFH = 17V, VREFL = 1V No Load, VREFH = 17V, VREFL = 1V RINH REG VOUT = VS/2, IOUT = +5mA to −5mA Step VOUT = VS/2, ISINKING = 40mA, ISOURCING = 40mA 7 No Load 0.3 0.3 0.12 5 ±20 ±25 100 0.5 0.5 ±50 1.5 1.5 18 28 28 VS IS 18 VIH VIL VOL fCLK 0.7 × VSD ISINK = 3mA Standard/Fast Mode High-Speed Mode 2.0 Outputs at Reset Values, No-Load, Two-Wire Bus Inactive 25 100 −40 −40 −65 30 15 0.15 ±0.01 0.3 × VSD 0.4 ±10 400 3.4 5.5 50 VSD ISD Junction Temperature < 125°C +85 +95 +150 qJA qJC (1) See typical characteristic Output Voltage vs Output Current. (2) See applications information section REFH and REFL Input Range. (3) See typical characteristic Digital Supply Current vs Temperature. 3 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 PIN CONFIGURATIONS Top View VCOM OUT 2 REFH NC(1) NC(1) OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 GNDA (2) HTSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PowerPAD Lead−Frame Die Pad Exposed on Underside 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 VCOM OUT 1 REFL NC (1) NC (1) REFL OUT OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 GNDA(2) VS OUT 13 OUT 12 OUT 11 OUT 10 GNDD(2) LD AO VS OUT 7 OUT 8 OUT 9 REFH OUT VSD SCL SDA (1) NC denotes no connection. (2) GNDD and GNDA are internally connected and must be at the same voltage potential. 4 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 TYPICAL CHARACTERISTICS At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. ANALOG SUPPLY CURRENT vs TEMPERATURE 16 VS = 18V 14 12 Analog I Q (mA) 10 8 6 4 2 0 − 40 − 20 0 20 40 60 80 100 Temperature (_ C) 5 0 − 40 VS = 10V 25 Digital IQ (µA) 20 15 10 30 DIGITAL SUPPLY CURRENT vs TEMPERATURE VS = 5V VS = 3.3V − 20 0 20 40 60 80 100 Temperature (_ C) Figure 1 Figure 2 FULL−SCALE OUTPUT SWING 18 REFH = 17V REFL = 1V Output Voltage (5V/div) Code 3FF →000 Output Voltage (V) 17 16 15 OUTPUT VOLTAGE vs OUTPUT CURRENT OUT10−18 (sourcing), Code = 3FFh VREFL = 0.2V, VREFH = 17V OUT1−9, V RLOAD Connected to GND COM 1−2 (sourcing) Code = 3FFh VREFL = 1V, VREFH = 17.8V RLOAD Connected to GND OUT10−18 (sinking), Code = 000h VREFL = 0.2V, VREFH = 17V RLOAD Connected to 18V 3 2 1 0 OUT1−9, VCOM1−2 (sinking) Code = 000h VREFL = 1V, VREFH = 17.8V RLOAD Connected to 18V Code 000 →3FF Time (1µ s/div) 0 10 20 30 40 50 60 70 80 90 100 Output Current (mA) Figure 3 Figure 4 INTEGRAL NONLINEARITY ERROR vs INPUT CODE 0.6 0.4 DNL Error (LSB) INL Error (LSB) 0.2 0 − 0.2 − 0.4 − 0.6 0 200 400 600 800 1000 Input Code 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE 0 200 400 600 800 1000 Input Code Figure 5 Figure 6 5 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 APPLICATIONS INFORMATION The BUF20800 programmable voltage reference allows fast, easy adjustment of 18 programmable reference outputs and two channels for VCOM adjustment, each with 10-bit resolution. It offers very simple, time-efficient adjustment of the gamma reference and VCOM voltages. The BUF20800 is programmed through a high-speed, standard, two-wire interface. The BUF20800 features a double-register structure for each DAC channel to simplify the implementation of dynamic gamma control. This structure allows pre-loading of register data and rapid updating of all channels simultaneously. Buffers 1−9 are able to swing to within 200mV of the positive supply rail, and to within 0.6V of the negative supply rail. Buffers 10−18 are able to swing to within 0.8V of the positive supply rail and to within 200mV of the negative supply rail. The BUF20800 can be powered using an analog supply voltage from 7V to 18V, and a digital supply from 2V to 5.5V. The digital supply must be applied prior to or simultaneously with the analog supply to avoid excessive current and power consumption; damage to the device may occur if it is left connected only to the analog supply for extended periods of time. Figure 7 shows the power supply timing requirements. the serial clock on the clock signal line (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the 9th clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and eight bits of data are sent followed by an Acknowledge Bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted as a START or STOP condition. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The BUF20800 can act only as a slave device; therefore, it never drives SCL. SCL is only an input for the BUF20800. Table 1 and Table 2 summarize the address and command codes, respectively, for the BUF20800. ADDRESSING THE BUF20800 VSD Digital Supply: GND D VS Analog Supply: GND t1 t1: 0s minimum delay between Digital Supply and Analog Supply. The address of the BUF20800 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on address 75h (1110101). Other valid addresses are possible through a simple mask change. Contact your TI representative for information. Figure 7. Power Supply Timing Requirements Figure 8 shows the BUF20800 in a typical configuration. In this configuration, the BUF20800 device address is 74h. The output of each digital-to-analog converter (DAC) is immediately updated as soon as data is received in the corresponding register (LD = 0). For maximum dynamic range, set VREFH = VS − 0.2V and VREFL = GND + 0.2V. Table 1. Quick-Reference Table of BUF20800 Addresses DEVICE/COMPONENT BUF20800 Address: A0 pin is LOW (device will acknowledge on address 74h) A0 pin is HIGH (device will acknowledge on address 75h) 1110100 1110101 ADDRESS TWO-WIRE BUS OVERVIEW The BUF20800 communicates through an industrystandard, two-wire interface to receive data in slave mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are driven to a logic low level only. The device that initiates the communication is called a master, and the devices controlled by the master are slaves. The master generates 6 Table 2. Quick-Reference Table of Command Codes COMMAND General Call Reset CODE Address byte of 00h followed by a data byte of 06h. 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. High-Speed Mode BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 BUF20800 VCOM 1 (1) 1 VC OM OUT2 (1) VCOM OU T1 38 V CO M2 VS 2 REFH REFL 37 VS 3 NC NC 36 4 NC NC 35 (1) 5 OUT1 REFL OUT 34 (1) (1) 6 OUT2 OUT18 33 (1) 7 Source Driver (1) OUT3 (1) OUT17 32 8 OUT4 (1) OUT16 31 Source Driver (1) (1) 9 OUT5 OUT15 30 (1) 10 OUT6 (1) OUT14 29 11 GNDA (2) GNDA (2) 28 VS 100nF (1) 10µ F 12 VS VS 27 100nF (1) 10 µF VS 13 OUT7 OUT13 26 Source Driver (1) (1) 14 OUT8 OUT12 25 Source Driver (1) 15 OUT9 (1) OUT11 24 (1) 16 REFH OUT OUT10 23 3.3V 1µ F 17 100nF VSD GND D(2) 22 18 Timing Controller 19 SCL LD 21 SDA AO 20 Figure 8. Typical Application Configuration 7 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 DATA RATES The two-wire bus operates in one of three speed modes: OUTPUT VOLTAGE Buffer output values are determined by the reference voltages (VREFH and VREFL) and the decimal value of the binary input code used to program that buffer. The value is calculated using Equation 1: VOUT + VREFH * VREFL 1024 Decimal Value of Code ) VREFL D D D Standard: allows a clock frequency of up to 100kHz; Fast: allows a clock frequency of up to 400kHz; and High-speed mode (or Hs mode): allows a clock frequency of up to 3.4MHz. The BUF20800 is fully compatible with all three modes. No special action is required to use the device in Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special address byte of 00001xxx, with SCL = 400kHz, following the START condition; xxx are bits unique to the Hs-capable master, which can be any value. This byte is called the Hs master code. (Note that this is different from normal address bytes—the low bit does not indicate read/write status.) The BUF20800 will respond to the High-speed command regardless of the value of these last three bits. The BUF20800 will not acknowledge this byte; the communication protocol prohibits acknowledgement of the Hs master code. On receiving a master code, the BUF20800 will switch on its Hs mode filters, and communicate at up to 3.4MHz. Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a STOP. The BUF20800 will switch out of Hs mode with the next STOP condition. (1) The valid voltage ranges for the reference voltages are: 4V v V REFH v VS * 0.2V and 0.2V v VREFL v VS * 4V (2) The BUF20800 outputs are capable of a full-scale voltage output change in typically 5µs—no intermediate steps are required. OUTPUT LATCH Updating the DAC register is not the same as updating the DAC output voltage, because the BUF20800 features a double-buffered register structure. There are three methods for latching transferred data from the storage registers into the DACs to update the DAC output voltages. Method 1 requires externally setting the latch pin (LD) LOW, LD = LOW, which will update each DAC output voltage whenever its corresponding register is updated. Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer and until LD = LOW, which will then simultaneously update the output voltages of all DACs to the new register values. Use this method to transfer a future data set in advance to prepare for a very fast output voltage update. Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a 1 in bit 15 of any DAC register. The update will occur after receiving the 16-bit data for the currently-written register. The General Call Reset and the power-up reset will update the DAC regardless of the state of the latch pin. GENERAL CALL RESET AND POWER-UP The BUF20800 responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). The BUF20800 acknowledges both bytes. Upon receiving a General Call Reset, the BUF20800 performs a full internal reset, as though it had been powered off and then on. It always acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call data bytes other than 06h (0000 0110). The BUF20800 automatically performs a reset upon power up. As part of the reset, all outputs are set to (VREFH − VREFL)/2. Other reset values are available as a custom modification—contact your TI representative for details. The BUF20800 resets all outputs to (VREFH − VREFL)/2 after sending the device address, if a valid DAC address is sent with bits D7 to D5 set to ‘100’. If these bits are set to ‘010’, only the DAC being addressed in this most significant byte (MSB) and the following least significant byte (LSB) will be reset. READ/WRITE OPERATIONS The BUF20800 is able to read from a single DAC, or multiple DACs, or write to the register of a single DAC, or multiple DACs in a single communication transaction. DAC addresses begin with 0000 0000, which corresponds to DAC_1, through 0001 0011, which corresponds to VCOM OUT2. Write commands are performed by setting the read/write bit LOW. Setting the read/write bit HIGH will perform a read transaction. 8 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 Writing: To write to a single DAC register: To write to multiple DAC registers: 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF20800 will acknowledge this byte. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be updated. The BUF20800 will begin with this DAC and step through subsequent DACs in sequential order. Send the bytes of data; begin by sending the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning), followed by the least significant byte (bits D7−D0). The first two bytes are for the DAC addressed in step 3 above. Its register is automatically updated after receiving the second byte. The next two bytes are for the following DAC. That DAC register is updated after receiving the fourth byte. This process continues until the registers of all following DACs have been updated. Send a STOP condition on the bus. 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF20800 will acknowledge this byte. Send a DAC address byte. Bits D7−D5 must be set to 0. Bits D4−D0 are the DAC address. Only DAC addresses 00000 to 10011 are valid and will be acknowledged. Table 3 shows the DAC addresses. Send two bytes of data for the specified DAC register. Begin by sending the most significant byte first (bits D15−D8, of which only bits D9 and D8 are used, and bits D15−D14 must not be 01), followed by the least significant byte (bits D7−D0). The register is updated after receiving the second byte. Send a STOP condition on the bus. 4. 4. 5. Table 3. DAC Addresses DAC DAC_1 DAC_2 DAC_3 DAC_4 DAC_5 DAC_6 DAC_7 DAC_8 DAC_9 DAC_10 DAC_11 DAC_12 DAC_13 DAC_14 DAC_15 DAC_16 DAC_17 DAC_18 VCOM OUT1 VCOM OUT2 ADDRESS 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 0001 0000 0001 0001 0001 0010 0001 0011 5. The BUF20800 will acknowledge each byte. To terminate communication, send a STOP or START condition on the bus. Only DAC registers that have received both bytes of data will be updated. Reading: Reading a DAC register will return the data stored in the DAC. This data can differ from the data stored in the DAC register. See the Output Latch section. To read the DAC value: 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF20800 will acknowledge this byte. Send the DAC address byte. Bits D7−D5 must be set to 0; Bits D4−D0 are the DAC address. Only DAC addresses 00000 to 10011 are valid and will be acknowledged. Send a START or STOP/START condition on the bus. Send correct device address and read/write bit = HIGH. The BUF20800 will acknowledge this byte. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8; only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0). Acknowledge after receiving the first byte. Do not acknowledge the second byte to end the read transaction. 4. The BUF20800 will acknowledge each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not the same as updating the DAC output voltage. See the Output Latch section. The process of updating multiple DAC registers begins the same as when updating a single register. However, instead of sending a STOP condition after writing the addressed register, the master continues to send data for the next register. The BUF20800 automatically and sequentially steps through subsequent registers as additional data is sent. The process continues until all desired registers have been updated or a STOP condition is sent. 5. 6. 7. 8. Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge. 9 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 To Read Multiple DACs: 6. 1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF20800 will acknowledge this byte. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be read. The BUF20800 will begin with this DAC and step through subsequent DACs in sequential order. Send a START or STOP/START condition on the bus. Send correct device address and read/write bit = HIGH. The BUF20800 will acknowledge this byte. 7. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8, only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0). Acknowledge after receiving each byte of data except for the last byte. The acknowledge bit of the last byte should be HIGH to end the read operation. When all desired DACs have been read, send a STOP or repeated START condition on the bus. 8. 4. 5. Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge. 10 www.ti.com Write single DAC register. P4−P0 specify DAC address. Write Ackn DAC address pointer. D7−D5 must be 000. Ackn DAC MSbyte. D14 must be 0. Ackn DAC LSbyte Ackn Write Operation Stop Start Device Address SCL SDA_in A c kn A c kn A c kn A6 A5 A4 A3 A2 A1 A0 W D7 D6 D5 P4 P3 P2 P1 P0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A ck n Device_out A c kn A c kn A c kn A6 If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. A5 A4 A3 A2 A1 A0 W D7 D6 D5 P4 P3 P2 P1 P0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A ck n SCL SDA_in Device_out a. Write Single DAC Write Operation Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn DAC (pointer) MSbyte. D14 must be 0. Ackn DAC (pointer) LSbyte A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. The entire DAC register D9−D0 is updated in this moment. Write multiple DAC registers. P4−P0 specify start DAC address. Start Device Address Ackn DAC (pointer + 1) MSbyte. D14 must be 0. A6 A5 A4 A3 D0 Ackn D15 D14 D13 A6 A5 A4 A3 D0 Ackn D15 D14 D13 Figure 9. Timing Diagram for Write DAC Register DAC 20 (VCOM OUT2) MSbyte. D14 must be 0. Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 If D15 = 0, the DACs are uploaded on the Latch pin. If D15 = 1, all the DACs are updated when the current DAC register is updated. The entire DAC register D9−D0 is updated in this moment. DAC 20 LSbyte Ackn Stop b. Write Multiple DACs D5 D4 D3 D2 D1 D0 Ackn D5 D4 D3 D2 D1 D0 Ackn The entire DAC register D9−D0 is updated in this moment. SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 BUF20800 11 12 Write Start Read Operation Ackn DAC address pointer. D7−D5 must be 000. Ackn Device Address Read Ackn DAC MSbyte. D15−D10 have no meaning. Ackn DACLSbyte. No Ackn BUF20800 Read single DAC register. P4−P0 specifyDAC address. Start Device Address Stop SCL A1 Ackn Ackn Ackn SDA_in A1 Ackn Ackn Ackn A6 A0 W D7 D6 D5 P4 P3 P2 P1 P0 A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 A5 A4 A3 A2 A0 W D7 D6 D5 P4 P3 P2 P1 P0 A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D0 SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 Device_out A6 A5 A4 A3 A2 SDA_in Device_out a. Read Single DAC Read Operation Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn Start Device Address Read Ackn DAC (pointer) MSbyte. D15−D10 have no meaning. Ackn A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn DAC 20 (VCOM OUT2) MSbyte. D15−D10 have no meaning. Ackn DAC 20 LSbyte. No Ackn Read multiple DAC registers. P4−P0 specify start DAC address. Start Device Address SCL A6 A5 A4 A3 A6 A5 A4 A3 Figure 10. Timing Diagram for Read DAC Register D15 D14 D13 D12 D11 D10 D9 D8 A c kn Stop D7 D6 D5 D4 D3 D2 D1 D0 b. Read Multiple DACs D15 D14 D13 D12 D11 D10 D9 D8 A c kn D7 D6 D5 D4 D3 D2 D1 D0 A ck n www.ti.com BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 REPLACEMENT OF TRADITIONAL GAMMA BUFFER Traditional gamma buffers rely on a resistor string (often using expensive 0.1% resistors) to set the gamma voltages. During development, the optimization of these gamma voltages can be time-consuming. Programming these gamma voltages with the BUF20800 can significantly reduce the time required for gamma voltage optimization. The final gamma values can be written into an external EEPROM to replace a traditional gamma buffer solution. During power-up of the LCD panel, the timing controller reads the EEPROM and loads the values into the BUF20800 to generate the desired gamma voltages. Figure 11a shows the traditional resistor string; Figure 11b shows the more efficient alternative method using the BUF20800. BUF20800 uses the most advanced high-voltage CMOS process available today, which allows it to be competitive with traditional gamma buffers. This technique offers significant advantages: D D D It shortens development time significantly. It allows demonstration of various gamma curves to LCD monitor makers by simply uploading a different set of gamma values. It allows simple adjustment of gamma curves during production to accommodate changes in the panel manufacturing process or end-customer requirements. It decreases cost and space. D a) Traditional BUFxx704 b) BUF20800 Solution BUF20800 VCOM OUT1 VCOM VCOM OUT2 Timing Controller PC Register SDA SCL OUT1 OUT2 EEPROM OUT17 Gamma References OUT18 SDA Control Interface SCL LCD Panel Electronics Figure 11. Replacement of the Traditional Gamma Buffer 13 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 PROGRAMMABLE VCOM The VCOM channels of the BUF20800 can swing to 2V from the positive supply rail while sourcing 100mA and to 1V above the negative rail while sinking 100mA (see Figure 4, typical characteristic Output Voltage vs Output Current). To store the gamma and the VCOM values, an external EEPROM is required. During power-up of the LCD panel, the timing controller can then read the EEPROM and load the values into the BUF20800 to generate the desired VCOM voltages, as illustrated in Figure 11 and Figure 12. The VCOM channels can be programmed independently from the gamma channels. REFH AND REFL INPUT RANGE Best performance and output swing range of the BUF20800 are achieved by applying REFH and REFL voltages that are slightly below the power-supply voltages. Most specifications have been tested at REFH = VS − 200mV and REFL = GND + 200mV. The REFH internal buffer is designed to swing very closely to VS and the REFL internal buffer to GND. However, there is a finite limit on how close they can swing before saturating. To avoid saturation of the internal REFH and REFL buffers, the REFH voltage should not be greater than VS −100mV and REFL voltage should not be lower than GND + 100mV. Figure 13 shows the swing capability of the REFH and REFL buffers. The other consideration when trying to maximize the output swing capability of the gamma buffers is the limitation in the swing range of output buffers (OUT1−18, VCOM1, and VCOM2), which depends on the load current. A typical load in the LCD application is 5−10mA. For example, if OUT1 is sourcing 10mA, the swing is typically limited to about VS − 200mV. The same applies to OUT18, which typically limits at GND + 200mV when sinking 10mA. An increase in output swing can only be achieved for much lighter loads. For example, a 3mA load typically allows the swing to be increased to approximately VS − 100mV and GND + 100mV. Connecting REFH directly to VS and REFL directly to GND does not damage the BUF20800. As discussed above however, the output stages of the REFH and REFL buffers will saturate. This condition is not desirable and can result in a small error in the measured output voltages of OUT1−18, VCOM1, and VCOM2. As described above, this method of connecting REFH and REL does not help to maximize the output swing capability. 18 OUT18 17 BUF20800 VCOM OUT1 VCOM VCOM OUT2 OUT1 Register OUT2 Gamma References OUT17 SDA Control Interface SCL Output Voltage (V) 16 15 REFH OUT (sourcing), Code = 3FFh VREFL = 1V, VREFH = 17.8V RLOAD Connected to GND 3 2 1 0 0 10 REFL OUT (sinking), Code = 000h VREFL = 0.2V, VREFH = 17V R LOAD Connected to 18V 20 30 40 50 60 70 80 90 100 Output Current (mA) Figure 12. BUF20800 Used for Programmable VCOM Figure 13. Reference Buffer Output Voltage vs Output Current 14 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 CONFIGURATION FOR 20 GAMMA CHANNELS The VCOM outputs can be used as additional gamma references in order to achieve two additional gamma channels (20 total). The VCOM outputs will behave the same as the OUT1−9 outputs when sourcing or sinking smaller currents (see the Typical Characteristics, Figure 4). The VCOM outputs are better able to swing to the positive rail than to the negative rail. Therefore, it is better to use the VCOM outputs for higher reference voltages, as shown in Figure 14. 2V−5.5V 15V 14.8V Digital BUF20800 Analog REFH REFH OUT 14.8V Source Driver V CO M OUT1 GMA 1 V CO M OUT2 GMA 2 CONFIGURATION FOR 22 GAMMA CHANNELS In addition to the VCOM outputs, the REFH and REFL OUT outputs can also be used as fixed gamma references. The output voltage will be set by the REFH and REFL input voltages, respectively. Therefore, REFH OUT should be used for the highest voltage gamma reference, and REFL OUT for the lowest voltage gamma reference. A 22-channel solution can be created by using all 18 outputs, the two VCOM outputs, and both REFH/L OUT outputs for gamma references—see Figure 15. However, the REFH and REFL OUT buffers were designed to only drive light loads on the order of 5−10mA. Driving capacitive loads is not recommended with these buffers. In addition, the REFH and REFL buffers must not be allowed to saturate from sourcing/sinking too much current from REFH OUT or REFL OUT. Saturation of the REFH and REFL buffers results in errors in the voltages of OUT1−18 and VCOM OUT1−2. The BUF01900, which is anticipated to be released in Q3 ’05, can be used to provide a programmable VCOM output. OUT1 GMA 3 DAC Registers DAC Registers OUT2 GMA 4 18 Gamma Channels OUT17 GMA 19 OUT18 GMA 20 REFL OUT 0.2V Control IF SDA SCL LD A0 REFL 15V 0.2V Figure 14. 20 Gamma Channel Solution − 2 VCOM Channels Used as Additional Gamma Channels 15 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 18V 2V−5.5V 17.8V Reference buffer and V COM OUT outputs can be used for extra gamma channels. (REFH OUT will be a fixed voltage.) Source Driver GMA 1 Digital BUF20800 Analog REFH REFH OUT 17V V COM OUT 1 GMA 2 V COM OUT 2 GMA 3 OUT1 GMA 4 DAC Registers DAC Registers OUT2 GMA 5 2 VCOM Channels plus 18 Output Channels OUT17 GMA 20 OUT18 GMA 21 REFL OUT 0.2V GMA 22 Control IF Panel LD A0 REFL Output of reference buffer can be used for an extra fixed gamma channel 18V 0.2V V COM SDA SCL 2V−5.5V 18V Digital BUF01900(1) Voltage Regulato r Program Command Analog BIAS 4 x OTP ROM Switch Control 10−Bit DAC V COM Buffer V COM OUT SDA SCL Control IF A0 NOTE: (1) Expected availability is Q4’ 06. Figure 15. 22-Channel Gamma Solution 16 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 DYNAMIC GAMMA CONTROL Dynamic gamma control is a technique used to improve the picture quality in LCD TV applications. The brightness in each picture frame is analyzed and the gamma curves are adjusted on a frame-by-frame basis. The gamma curves are typically updated during the short vertical blanking period in the video signal. Figure 16 shows a block diagram using the BUF20800 for dynamic gamma control and VCOM output. The BUF20800 is ideally suited for rapidly changing the gamma curves because of its unique topology: a picture is still being displayed. Because the data is only stored into the first register bank, the DAC output values remain unchanged—the display is unaffected. During the vertical sync period, the DAC outputs (and therefore, the gamma voltages) can be quickly updated either by using an additional control line connected to the LD pin, or through software—writing a ‘1’ in bit 15 of any DAC register. For the details on the operation of the double register input structure, see the Output Latch section. Example: Update all 18 gamma registers simultaneously via software. Step 1: Check if LD pin is placed in HIGH state. Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’. Step 3: Write any DAC register a second time with identical data. Make sure that bit 15 is ‘1’. All DAC channels will be updated simultaneously after receiving the last bit of data. (Note: this step may be eliminated by setting bit 15 of DAC 18 to ‘1’ in the previous step.) D D D double register input structure to the DAC; fast serial interface; simultaneous updating of all DACs by software. See the Read/Write Operations to write to all registers and the Output Latch sections. The double register input structure saves programming time by allowing updated DAC values to be pre-loaded into the first register bank. Storage of this data can occur while Histogram Digital Picture Data Black White Gamma Adjustment Algorithm SDA BUF20800 Gamma References 1 through 18 SCL Timing Controller/µ Controller Source Driver Source Driver VCOM Figure 16. Dynamic Gamma Control 17 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 TOTAL TI PANEL SOLUTION In addition to the BUF20800 programmable voltage reference, TI offers a complete set of ICs for the LCD panel market, including gamma correction buffers, various power-supply solutions, and audio power solutions. See Figure 17 for the total IC solution from TI. outputs, and other functions. The BUF20800, with its 20 total programmable DAC channels, provides great flexibility to the entire system by allowing the designer to change all these parameters via software. Figure 18 provides various ideas on how the BUF20800 can be used in applications. A micro-controller with two-wire serial interface controls the various DACs of the BUF20800. The BUF20800 can be used for: THE BUF20800 IN INDUSTRIAL APPLICATIONS The wide supply range, high output current, and very low cost make the BUF20800 attractive for a range of medium accuracy industrial applications such as programmable power supplies, multi-channel data-acquisition systems, data-loggers, sensor excitation and linearization, power-supply generation, and other uses. Each DAC channel features 1LSB DNL and INL. Many systems require different levels of biasing and power supply for various components as well as sensor excitation, control-loop set-points, voltage outputs, current D D D D D D sensor excitation programmable bias/reference voltages variable power-supplies high-current voltage output 4-20mA output set-point generators for control loops. NOTE: The output voltages of the BUF20800 DACs will be set to (VREFH − VREFL)/2 at power-up or reset. Gamma Correction BUF20800 2.7V−5V TPS651xx LCD Supply 15V 26V − 14V VCOM 3.3V TPA3005D2 TPA3008D2 Audio Speaker Driver n Source Driver n Gate Driver Logic and Timing Controller High−Resolution TFT−LCS Panel Figure 17. TI LCD Solution 18 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 +18V +5V Voltage Output High Current Voltage Output Control Loop Set Point 0.3V to 17V BUF2 0 8 0 0 +5V 2V to 16V, 100mA Sensor Excitation/Linearization 4−20mA +5V 4−20mA Generator +2.5V Bias Bias Voltage Generator LED Driver Offset Adjustment INA Ref +4V +4.3V Comparator Threshold Supply Voltage Generator Ref Reference for MDAC +7.5V SDA SCL MDAC µC Figure 18. Industrial Applications for the BUF20800 19 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 EVALUATION BOARD AND SOFTWARE An evaluation board is available for the BUF20800. The evaluation board features easy-to-use software that allows individual channel voltages to be set (see Figure 19). Configurations can be quickly evaluated to determine optimal codes for a given application. Contact your local TI representative for more information regarding the evaluation board. Figure 19. Evaluation Board 20 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 GENERAL POWERPAD DESIGN CONSIDERATIONS The BUF20800 is available in a thermally-enhanced PowerPAD package. This package is constructed using a downset leadframe upon which the die is mounted, as shown in Figure 20(a) and Figure 20(b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 20(c). This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have low power dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD. 1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the thermal pad. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns (2x5) can be seen in the technical brief, PowerPAD Thermally-Enhanced Package (SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them small, so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the BUF20800 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered; thus, wicking is not a problem. Connect all holes to the internal plane that is at the same voltage potential as the GND pins. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the BUF20800 PowerPAD package should make their connection to the internal plane with a complete connection around the entire circumference of the plated-through hole. The top-side solder mask should leave the terminals of the package and the thermal pad area with its ten holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking prevents solder from being pulled away from the thermal pad area during the reflow process. Apply solder paste to the exposed thermal pad area and all of the IC terminals. With these preparatory steps in place, the BUF20800 IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This preparation results in a properly installed part. 4. 5. 6. 7. 8. 2. 21 BUF20800 www.ti.com SBOS329D − JUNE 2005 − REVISED OCTOBER 2006 DIE Side View (a) DIE End View (b) Thermal Pad Bottom View (c) The thermal pad is electrically isolated from all terminals in the package. Figure 20. Views of Thermally-Enhanced DCP Package For a given qJA, the maximum power dissipation is shown in Figure 21, and is calculated by Equation 3: 6 Maximum Power Dissipation (W) 5 4 3 2 1 0 − 40 − 20 0 20 40 60 80 100 TA, Free−Air Temperature (_ C) T MAX * T A PD + q JA Where: PD = maximum power dissipation (W) (3) TMAX = absolute maximum junction temperature (125°C) TA = free-ambient air temperature (°C) qJA = qJC + qCA qJC = thermal coefficient from junction-to-case (°C/W) qCA = thermal coefficient from case-to-ambient air (°C/W) Figure 21. Maximum Power Dissipation vs Free-Air Temperature (with PowerPAD soldered down) 22 PACKAGE OPTION ADDENDUM www.ti.com 21-Sep-2006 PACKAGING INFORMATION Orderable Device BUF20800AIDCPR (1) Status (1) ACTIVE Package Type HTSSOP Package Drawing DCP Pins Package Eco Plan (2) Qty 38 2000 Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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