CC2545
www.ti.com
SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
System-on-Chip for 2.4-GHz RF Applications
FEATURES
1
•
•
•
RF section
– Single-Chip 2.4-GHz RF Transceiver and
MCU
– Supports 250 kbps, 500 kbps, 1 Mbps and 2
Mbps data rates
– Excellent Link Budget, Enabling Long
Range Without External Front-Ends
– Programmable Output Power up to 4 dBm
– Excellent Receiver Sensitivity (–90 dBm at
2 Mbps, –98 dBm at 250 kbps)
– Suitable for Systems Targeting Compliance
With Worldwide Radio Frequency
Regulations: ETSI EN 300 328 and EN 300
440 Category 2 (Europe), FCC CFR47 Part
15 (US), and ARIB STD-T66 (Japan)
– Accurate RSSI Function
Layout
– Few External Components
– Pin Out Suitable for Single Layer PCB
Applications
– Reference Designs Available
– 48-pin 7-mm × 7-mm QFN (31 General I/O
Pins) Package
Low Power
– Active Mode RX Best Performance: 20.8 mA
– Active Mode TX (0 dBm): 26.3 mA
– Power Mode 1 (5 µs Wake-Up): 235 µA
– Power mode 2 (sleep timer on): 0.9 µA
– Power mode 3 (External interrupts): 0.4µA
– Wide Supply Voltage Range (2V to 3.6V)
– Full RAM and Register Retention in All
Power Modes
•
•
Microcontroller
– High-Performance and Low-Power 8051
Microcontroller Core With Code Prefetch
– 32-KB Flash Program Memory
– 1 KB SRAM
– Hardware Debug Support
– Extensive Baseband Automation, Including
Auto-Acknowledgement and Address
Decoding
Peripherals
– Two-Channel DMA with Access to all
Memory Areas and Peripherals
– General-Purpose Timers (One 16-Bit, Two
8-Bit)
– Radio Timer, 40-Bit
– IR Generation Circuitry
– Several Oscillators:
– 32MHz XOSC
– 16MHz RCOSC
– 32kHz XOSC
– 32kHz RCOSC
– 32-kHz Sleep Timer With Capture
– AES Security Coprocessor
– UART/SPI/I2C Serial Interface
– 31 General-Purpose I/O pins (3 × 20-mA
Drive Strength, Remaining pins have 4 mA
Drive Strength)
– Watchdog Timer
– True Random-Number Generator
– ADC and Analog Comparator
APPLICATIONS
•
•
•
Proprietary 2.4-GHz Systems
Human Interface Devices (keyboard, mouse)
Consumer Electronics
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1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
CC2545
SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CC2545 is an optimized system-on-chip (SoC) solution with data rates up to 2Mbps built with low bill-ofmaterial cost. The CC2545 combines the excellent performance of a leading RF transceiver with a single-cycle
8051 compliant CPU, 32-KB in-system programmable flash memory, up to 1-KB RAM, 31 General-Purpose I/O
pins and many other powerful features. The CC2545 has efficient power modes with RAM and register retention
below 1 μA, making it highly suited for low-duty-cycle systems where ultralow power consumption is required.
Short transition times between operating modes further ensure low energy consumption.
The CC2545 is compatible with the CC2541/CC2543/CC2544. It comes in a 7-mm × 7-mm QFN48 package, with
SPI/UART/I2C interface. The CC2545 comes complete with reference designs from Texas Instruments.
The device targets wireless consumer and HID applications. The CC2545 is tailored for peripheral devices such
as wireless keyboards.
For block diagram, see Figure 7
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage VDD
TEST CONDITIONS
MIN
MAX
UNIT
–0.3
3.9
V
–0.3
VDD+0.3 ±6-MHz offset, wanted signal at –67 dBm
38
dB
1-MHz resolution. Wanted signal at –67 dBm, f < 2 GHz
Two exception frequencies with poorer performance
–32
1-MHz resolution. Wanted signal at –67 dBm, 2 GHz > f < 3 GHz
Two exception frequencies with poorer performance
–38
1-MHz resolution. Wanted signal at –67 dBm, f > 3GHz
Two exception frequencies with poorer performance
–12
Intermodulation
Wanted signal at –64 dBm, 1st interferer is CW, 2nd interferer is GFSKmodulated signal. Offsets of interferers are:
6 and 12 MHz
8 and 16 MHz
10 and 20 MHz
–43
Frequency error tolerance (1)
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
–300
300
kHz
Symbol rate error tolerance (2)
Sensitivity better than -70 dBm. 250 byte payload.
–120
120
ppm
Out-of-band blocking rejection
dBm
dBm
2 Mbps, GFSK, 500 kHz DEVIATION, 0.1% BER
Receiver sensitivity
Saturation
Co-channel rejection
Frequency error tolerance
(1)
Symbol rate error tolerance (2)
dBm
–3
dBm
–10
dB
±2 MHz offset, wanted signal at –67 dBm
–3
dB
±4 MHz offset, wanted signal at –67 dBm
36
dB
>±6 MHz offset, wanted signal at –67 dBm
44
dB
Wanted signal at –67 dBm
In-band blocking rejection
–90
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
–300
300
kHz
Sensitivity better than -70 dBm. 250 byte payload.
–120
120
ppm
1 Mbps, GFSK, 250 kHz DEVIATION, 0.1% BER
Receiver sensitivity
Saturation
Co-channel rejection
In-band blocking rejection
Wanted signal at –67 dBm
6
dBm
–7
dB
0
±2 MHz offset, wanted signal –67 dBm
30
±3 MHz offset, wanted signal –67 dBm
34
>±5 MHz offset, wanted signal –67 dBm
38
Frequency error tolerance
Symbol rate error tolerance
Sensitivity better than –70 dBm. 250 byte payload.
4
dBm
±1 MHz offset, wanted signal –67 dBm
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
(1)
(2)
–94
dB
–250
250
kHz
-80
80
ppm
Difference between center frequency of the received RF signal and local oscillator frequency
Difference between incoming symbol rate and the internally generated symbol rate
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CC2545
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SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1 Mbps, GFSK, 160 kHz DEVIATION, 0.1% BER
Receiver sensitivity
Saturation
Co-channel rejection
In band blocking rejection
Wanted signal at –67 dBm
–91
dBm
6
dBm
–8
dB
±1 MHz offset, wanted signal at –67 dBm
2
±2 MHz offset, wanted signal at –67 dBm
28
±3 MHz offset, wanted signal at –67 dBm
33
>±5 MHz offset, wanted signal at –67 dBm
36
Frequency error tolerance
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Symbol rate error tolerance
Maximum packet length
dB
–250
250
kHz
–80
80
ppm
500 kbps, MSK, 0.1% BER
Receiver sensitivity
–98
dBm
6
dBm
Wanted signal at –67 dBm
–5
dB
±1 MHz offset, wanted signal at –67 dBm
21
±2 MHz offset, wanted signal at –67 dBm
32
>±2 MHz offset, wanted signal at –67 dBm
33
Saturation
Co-channel rejection
In band blocking rejection
Frequency error tolerance
Including both initial tolerance and drift, Sensitivity better than –67dBm
Symbol rate error tolerance
Maximum packet length
dB
–150
150
kHz
–60
60
ppm
250 kbps, GFSK, 160 kHz DEVIATION , 0.1% BER
Receiver sensitivity
Saturation
Co-channel rejection
In-band blocking rejection
–98
dBm
6
dBm
Wanted signal at –67 dBm
–2
dB
±1 MHz offset, wanted signal at –67 dBm
22
±2 MHz offset, wanted signal at –67 dBm
32
>±2 MHz offset, wanted signal at –67 dBm
dB
32
Frequency error tolerance
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Symbol rate error tolerance
Maximum packet length
–150
150
kHz
–60
60
ppm
250 kbps, MSK, 0.1% BER
Receiver sensitivity
–98
dBm
6
dBm
Wanted signal at –67 dBm
–5
dB
±1 MHz offset, wanted signal at –67 dBm
21
±2 MHz offset, wanted signal at –67 dBm
32
>2 MHz offset, wanted signal at –67 dBm
33
Saturation
Co-channel rejection
In-band blocking rejection
Frequency error tolerance
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Symbol rate error tolerance
Maximum packet length
dB
–150
150
kHz
–60
60
ppm
ALL RATES/FORMATS
Spurious emission in RX.
Conducted measurement
f < 1 GHz
–67
dBm
Spurious emission in RX.
Conducted measurement
f > 1 GHz
–60
dBm
Copyright © 2012–2013, Texas Instruments Incorporated
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output power, maximum setting
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting.
5
dBm
Output power, minimum setting
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting.
–20
dBm
25
dB
f < 1 GHz
–46
dBm
f > 1 GHz
–44
dBm
Programmable output power range Delivered to a single-ended 50-Ω load through a balun.
Spurious emission in TX.
Conducted measurement
Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN
300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Use a simple LC filter (1.6nH and 1.8pF in parallel to ground) to pass ETSI conducted requirements below 1GHz
in restricted bands. For radiated measurements low antenna gain for these frequencies (depending on antenna
design) can achieve the same attenuation of these low frequency components (see EM reference design).
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
Crystal frequency accuracy
requirement
TYP
MAX
32
250 kbps and 500 kbps data rates
1 Mbps data rate
2 Mbps data rate
Equivalent series resistance
MHz
–30
–40
–60
30
40
60
ppm
6
60
Ω
pF
Crystal shunt capacitance
1
7
Crystal load capacitance
10
16
Start-up time
Power-down guard time
0.25
The crystal oscillator must be in power down for a guard time
before it is used again. This requirement is valid for all modes of
operation. The need for power-down guard time can vary with
crystal type and load.
UNIT
pF
ms
3
ms
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Crystal frequency
Crystal frequency accuracy
requirement (1)
TYP
MAX
32.768
-100
UNIT
kHz
+100
ppm
Equivalent series resistance
40
130
Ω
Crystal shunt capacitance
0.9
2
pF
Crystal load capacitance
12
16
pF
Start-up time
0.4
(1)
6
s
Crystal frequency accuracy requirement is highly dependent on application. Higher accuracy enables more accurate duty-cycling which
in turn will reduce current consumption. The chip can handle much less accurate crystals.
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CC2545
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SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Calibrated frequency
32.753
Frequency accuracy after calibration
±0.2%
Temperature coefficient
MAX
UNIT
kHz
0.4
%/ºC
Supply-voltage coefficient
3
%/V
Calibration time
2
ms
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Calibrated frequency
TYP
MAX
16
Uncalibrated frequency accuracy
±18%
Frequency accuracy after calibration
±0.6%
UNIT
MHz
Start-up time
10
µs
Initial calibration time
50
µs
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
2Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
RSSI range (1)
RSSI offset (1)
Reduced gain by AC algorithm
64
High gain by AGC algorithm
64
Reduced gain by AGC algorithm
79
High gain by AGC algorithm
99
dB
dBm
Absolute uncalibrated accuracy (1)
±3
dB
Step size (LSB value)
1
dB
All Other Rates/Formats
RSSI range (1)
64
dB
RSSI offset (1)
99
dBm
Absolute uncalibrated accuracy
±3
dB
Step size (LSB value)
1
dB
(1)
Assuming CC2545 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
Phase noise, unmodulated carrier
TEST CONDITIONS
MIN
TYP
At ±1 MHz from carrier
–112
At ±3 MHz from carrier
–119
At ±5 MHz from carrier
–122
Copyright © 2012–2013, Texas Instruments Incorporated
MAX
UNIT
dBc/Hz
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ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
Output
Temperature coefficient
Voltage coefficient
Initial accuracy without calibration
Measured using integrated ADC, internal band-gap
voltage reference, and maximum resolution
TYP
MAX
UNIT
1480
12-bit
4.5
/ 0.1ºC
1
/ 0.1V
±10
ºC
Accuracy using 1-point calibration
±5
ºC
Current consumption when enabled
0.5
mA
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2545 reference designs, post-calibration.
PARAMETER
MIN
TYP MAX
VDD
Common-mode minimum voltage
–0.3
Input offset voltage
Offset vs temperature
Offset vs operating voltage
8
TEST CONDITIONS
Common-mode maximum voltage
UNIT
V
1
mV
16
µV/°C
4
mV/V
Supply current
230
nA
Hysteresis
0.15
mV
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ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
PARAMETER
ENOB (1)
TEST CONDITIONS
MIN
VDD is voltage on AVDD5 pin
0
VDD
V
VDD is voltage on AVDD5 pin
0
VDD
V
External reference voltage differential VDD is voltage on AVDD5 pin
0
VDD
Simulated using 4-MHz clock speed
197
kΩ
Full-scale signal (1)
Peak-to-peak, defines 0 dBFS
2.97
V
Effective number of bits
Total harmonic distortion
Signal to nonharmonic ratio
Single-ended input, 7-bit setting
5.7
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
9.3
Single-ended input, 12-bit setting
10.3
Differential input, 7-bit setting
6.5
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
10.9
7-bit setting, both single and differential
0–20
Single ended input, 12-bit setting, –6 dBFS (1)
–75.2
Differential input, 12-bit setting, –6 dBFS (1)
–86.6
79.3
(1)
dB
78.8
88.9
Common-mode rejection ratio
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
>84
dB
Crosstalk
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
>84
dB
Offset
Midscale
–3
mV
Differential nonlinearity
0.68%
12-bit setting, mean (1)
0.05
(1)
0.9
12-bit setting, maximum (1)
13.3
12-bit setting, maximum
Integral nonlinearity
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Signal-to-noise-and-distortion
Conversion time
(1)
dB
Differential input, 12-bit setting, –6 dBFS (1)
12-bit setting, mean (1)
SINAD
(–THD+N)
kHz
70.2
Differential input, 12-bit setting (1)
Single-ended input, 12-bit setting, –6 dBFS
bits
9.7
12-bit setting, clocked by RCOSC
Gain error
INL
V
Input resistance, signal
Single-ended input, 12-bit setting (1)
DNL
UNIT
External reference voltage
Useful power bandwidth
CMRR
MAX
Input voltage
10-bit setting, clocked by RCOSC
THD
TYP
LSB
4.6
10
LSB
29
Single ended input, 7-bit setting (1)
35.4
Single ended input, 9-bit setting (1)
46.8
Single ended input, 10-bit setting (1)
57.5
Single ended input, 12-bit setting (1)
66.6
Differential input, 7-bit setting (1)
40.7
Differential input, 9-bit setting (1)
51.6
Differential input, 10-bit setting (1)
61.8
Differential input, 12-bit setting (1)
70.8
7-bit setting
20
9-bit setting
36
10-bit setting
68
12-bit setting
132
dB
μs
Measured with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Power consumption
MAX
UNIT
1.2
Internal reference VDD coefficient
mA
4
Internal reference temperature
coefficient
Internal reference voltage
mV/V
0.4
mV/10°C
1.15
V
DC CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
V
Logic-0 input voltage
Logic-1 input voltage
2.5
Logic-0 input current
–50
50
nA
V
Logic-1 input current
–50
50
nA
I/O pin pullup and pulldown resistors
20
Logic-0 output voltage 4-mA pins
Output load 4 mA
Logic-1 output voltage 4-mA pins
Output load 4 mA
Logic-0 output voltage 20-mA pins
Output load 20 mA
Logic-1 output voltage, 20-mA pins
Output load 20 mA
(1)
kΩ
0.5
V
2.4
V
0.5
V
2.4
V
Note that only two of the three 20-mA pins can drive in the same direction at the same time, and toggle at the same time.
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
16
RESET_N low duration
See item 1, Figure 1. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
1
µs
Interrupt pulse duration
See item 2, Figure 1.This is the shortest pulse that is recognized as
an interrupt request.
20
ns
RESET_N
1
2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
10
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SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
t1
TEST CONDITIONS
SCK period
MIN
Master, RX and TX
250
Slave, RX and TX
250
TYP MAX
UNIT
ns
SCK duty cycle
Master
t2
SSN low to SCK,
Figure 2 and Figure 3
Master
63
Slave
63
t3
SCK to SSN high
Master
63
Slave
63
t4
MOSI early out
Master, load = 10 pF
7
ns
t5
MOSI late out
Master, load = 10 pF
10
ns
t6
MISO setup
Master
90
t7
MISO hold
Master
10
SCK duty cycle
Slave
t10
MOSI setup
Slave
35
ns
t11
MOSI hold
Slave
10
ns
t8
MISO early out
Slave, load = 10 pF
0
ns
t9
MISO late out
Slave, load = 10 pF
95
ns
Operating frequency
50%
ns
ns
ns
ns
50%
ns
Master, TX only
8
Master, RX and TX
4
Slave, RX only
8
Slave, RX and TX
4
MHz
SCK
t2
t3
SSN
t4
D0
MOSI
t6
MISO
X
t5
X
D1
t7
D0
X
T0478-01
Figure 2. SPI Master AC Characteristics
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SCK
t2
t3
SSN
t8
D0
MISO
X
t10
MOSI
X
t9
D1
t11
D0
X
T0479-01
Figure 3. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
MHz
fclk_dbg
Debug clock frequency (see Figure 4)
t1
Allowed high pulse on clock (see Figure 4)
35
ns
t2
Allowed low pulse on clock (see Figure 4)
35
ns
t3
EXT_RESET_N low to first falling edge on debug
clock (see Figure 5)
167
ns
t4
Falling edge on clock to EXT_RESET_N high (see
Figure 5)
83
ns
t5
EXT_RESET_N high to first debug command (see
Figure 5)
83
ns
t6
Debug data setup (see Figure 6)
2
ns
t7
Debug data hold (see Figure 6)
4
ns
t8
Clock-to-data delay (see Figure 6)
Load = 10 pF
30
ns
Time
DEBUG_ CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4. Debug Clock – Basic Timing
12
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Time
DEBUG_ CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 5. Debug Enable Timing
Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2545)
P2_1
DEBUG_DATA
(from CC2545)
P2_1
t6
t8
t7
T0438-03
Figure 6. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
Input capture pulse duration
TEST CONDITIONS
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
Copyright © 2012–2013, Texas Instruments Incorporated
MIN
1.5
TYP
MAX
UNIT
tSYSCLK
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DEVICE INFORMATION
P1_2
P1_5/ XOSC32K_Q1
VDD
DCPL1
VDD
P1_0
P1_1
P3_6
P3_7
VSS
P3_4
P3_5
RGZ PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
P3_3
1
P3_2
2
35
P1_6/ XOSC32K_Q2
RBIAS
P3_1
3
34
VDD
P3_0
4
P2_3
5
33
32
VDD
VSS
RF_N
P2_2
P2_0
P0_7
6
7
8
9
P0_6
10
P0_5
P0_4
26
11
12 13 14 15 16 17 18 19 20 21 22 23 24 25
31
30
RF_P
VSS
28
VDD
27
XOSC_Q2
XOSC_Q1
VDD
P1_3/DD
P2_5
P2_4
VDD
RESET_N
P1_4/DC
P2_7
P2_6
P0_1
P0_0
29
P0_3
P0_2
P2_1
VSS
Ground Pad
36
NOTE: The exposed ground pad must be connected to a solid ground plane; this is the main ground connection for
the chip.
Table 1. Pin Description Table
14
NAME
PIN
P3_3
1
Digital I/O
PIN TYPE
Port 3.3
P3_2
2
Digital I/O
Port 3.2
P3_1
3
Digital I/O
Port 3.1
P3_0
4
Digital I/O
Port 3.0
P2_3
5
Digital I/O
Port 2.3
P2_2
6
Digital I/O
Port 2.2
P2_1
7
Digital I/O
Port 2.1
P2_0
8
Digital I/O
Port 2.0
P0_7
9
Digital I/O
Port 0.7
P0_6
10
Digital I/O
Port 0.6
P0_5
11
Digital I/O
Port 0.5
P0_4
12
Digital I/O
Port 0.4
P0_3
13
Digital I/O
Port 0.3
P0_2
14
Digital I/O
Port 0.2
P0_1
15
Digital I/O
Port 0.1
P0_0
16
Digital I/O
Port 0.0
P2_7
17
Digital I/O
Port 2.7
P2_6
18
Digital I/O
Port 2.6
P2_5
19
Digital I/O
Port 2.5
P2_4
20
Digital I/O
Port 2.4
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DESCRIPTION
Copyright © 2012–2013, Texas Instruments Incorporated
CC2545
www.ti.com
SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
Table 1. Pin Description Table (continued)
NAME
PIN
VDD
21
Power (analog)
PIN TYPE
2-V-3.6V analog power-supply connection
DESCRIPTION
RESET_N
22
Digital input
Reset, active-low
P1_4/DC
23
Digital I/O / Debug
Port 1.4/Debug
P1_3/DD
24
Digital I/O / Debug
Port 1.3/Debug
VDD
25
Power (analog)
2-V-3.6V analog power-supply connection
XOSC_Q1
26
Analog I/O
32-MHz crystal oscillator pin 1or external-clock input
XOSC_Q2
27
Analog I/O
32-MHz crystal oscillator pin 2
VDD
28
Power (analog)
2-V-3.6V analog power-supply connection
VSS
29
Unused pin
Connect to ground
RF_P
30
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_N
31
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
VSS
32
Unused pin
Connect to ground
VDD
33
Power (analog)
2-V-3.6V analog power-supply connection
VDD
34
Power (analog)
2-V-3.6V analog power-supply connection
RBIAS
35
Analog I/O
External precision bias resistor for reference current
P1_6/
XOSC32K_
Q2
36
Digital I/O / Analog I/O
Port 1.6/32.768-kHz XOSC
P1_5/
XOSC32k_
Q1
37
Digital I/O / Analog I/O
Port 1.5/32.768-kHz XOSC
P1_2
38
Digital I/O
Port 1.2, 20mA
P1_1
39
Digital I/O
Port 1.1, 20mA
P1_0
40
Digital I/O
Port 1.0, 20mA
VDD
41
Power (analog)
2-V-3.6V analog power-supply connection
DCPL1
42
Power (digital)
1.8-V digital power-supply decoupling. Do not use for supplying external
circuits.
VDD
43
Power (analog)
2-V-3.6V analog power-supply connection
VSS
44
Unused pin
Connect to ground
P3_7
45
Digital I/O
Port 3.7
P3_6
46
Digital I/O
Port 3.6
P3_5
47
Digital I/O
Port 3.5
P3_4
48
Digital I/O
Port 3.4
VSS
Ground Pad Ground
Copyright © 2012–2013, Texas Instruments Incorporated
Must be connected to solid ground as this is the main ground connection
for the chip. See Pinout Diagram.
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CC2545
SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
www.ti.com
BLOCK DIAGRAM
A block diagram of the CC2545 is shown in Figure 7. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given. See CC2543/44/45 User's
Guide (SWRU283) for more details.
XOSC_Q2
32-MHz
CRYSTAL OSC
32.768-kHz
CRYSTAL OSC
DEBUG
INTERFACE
P3_7
HIGHSPEED
RC-OSC
VDD (2 V–3.6 V)
ON-CHIP VOLTAGE
REGULATOR
CLOCK MUX
and
CALIBRATION
SFR Bus
RESET
XOSC_Q1
POWER ON RESET
BROWN OUT
WATCHDOG
TIMER
RESET_N
DCOUPL
SLEEP TIMER
32-kHz
RC-OSC
POWER MANAGEMENT CONTROLLER
P3_6
P3_5
PDATA
P3_4
8051 CPU
CORE
P3_3
P3_2
P3_1
XRAM
IRAM
SFR
DMA
SRAM
FLASH
FLASH
MEMORY
ARBITRATOR
P3_0
P2_7
RAM
UNIFIED
P2_6
IRQ CTRL
P2_5
FLASH CTRL
P2_4
P2_3
SRAM
FIFOCTRL
ANALOG COMPARATOR
P2_2
Radio Arbiter
PSEUDO
RANDOM
NUMBER
GENERATOR
P2_0
P1_4
P1_3
P1_2
P1_1
AES
ENCRYPTION
AND
DECRYPTION
ΔΣ
ADC
AUDIO/DC
P1_0
RADIO REGISTERS
Link Layer Engine
SFR Bus
P1_5
I/O CONTROLLER
P1_6
ROM
DEMODULATOR
SYNTH
P2_1
MODULATOR
P0_7
P0_6
USART 0
P0_4
P0_3
RECEIVE
P0_2
P0_1
P0_0
TIMER 1 (16-Bit)
FREQUENCY
SYNTHESIZER
P0_5
TRANSMIT
TIMER 2
(RADIO TIMER)
DIGITAL
TIMER 3 (8-Bit)
RF_P
RF_N
ANALOG
TIMER 4 (8-Bit)
MIXED
B0301-13
Figure 7. CC2545 Block Diagram
16
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SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
BLOCK DESCRIPTIONS
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 15-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 7 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 1-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.
The 18-KB/32-KB flash block provides in-circuit programmable non-volatile program memory for the device,
and maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile two-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USART, timers, etc.)
can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or
XREG address and flash/SRAM.
The interrupt controller services a total of 17 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (when
in sleep mode, the device is in low-power mode PM1, PM2 or PM3).
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between several different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can use either an external 32.768-kHz XOSC or an internal
32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes. Typical applications of this
timer are as a real-time counter or as a wake-up timer to get out of power modes 1 or 2.
A built-in watchdog timer allows the CC2545 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
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Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit
overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture
register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the
exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflowcompare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and
TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has
its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured
as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling
scheme, and are thus well-suited for high data rates.
I2C module provides a digital peripheral connection with two pins and supports both master and slave operation.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ultralow power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is mapped into the digital I/O port and can be treated by the MCU as a regular digital input.
18
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SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
TYPICAL CHARACTERISTICS
All curves are for measurements performed at 2Mbps, GFSK, 320-kHz deviation.
RX CURRENT
vs
TEMPERATURE
TX CURRENT
vs
TEMPERATURE
32
24
31
Current (mA)
23
Current (mA)
3-V Supply
TXPOWER Setting = 0xE5
3-V Supply
Standard Gain Setting
−70 dBm Input
2 Mbps, GFSK, 320 kHz deviation
22
21
19
−40
−20
0
20
40
Temperature (°C)
60
27
−40
80
0
G001
20
40
Temperature (°C)
Figure 9.
RX SENSITIVITY
vs
TEMPERATURE
TX POWER
vs
TEMPERATURE
60
80
G002
10
3-V Supply
TXPOWER Setting = 0xE5
3-V Supply
Standard Gain Setting
2 Mbps, GFSK, 320 kHz deviation
−82
8
Power Level (dBm)
Sensitivity Level (dBm)
−20
Figure 8.
−80
−84
−86
6
4
2
−88
−90
−40
−20
0
20
40
Temperature (°C)
60
0
−40
80
−20
0
G003
20
40
Temperature (°C)
Figure 10.
Figure 11.
RX CURRENT
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
24
60
80
G004
32
TA = 25°C
Standard Gain Setting
−70 dBm Input
2 Mbps, GFSK, 320 kHz deviation
TA = 25°C
TXPOWER Setting = 0xE5
31
Current (mA)
23
Current (mA)
29
28
20
22
21
30
29
28
20
19
30
27
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
Figure 12.
Copyright © 2012–2013, Texas Instruments Incorporated
3.4
3.6
G005
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
G006
Figure 13.
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CC2545
SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All curves are for measurements performed at 2Mbps, GFSK, 320-kHz deviation.
RX SENSITIVITY
vs
SUPPLY VOLTAGE
TX POWER
vs
SUPPLY VOLTAGE
10
TA = 25°C
TXPOWER Setting = 0xE5
TA = 25°C
Standard Gain Setting
2 Mbps, GFSK, 320 kHz deviation
−82
8
Power Level (dBm)
Sensitivity Level (dBm)
−80
−84
−86
0
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
Figure 14.
Figure 15.
RX SENSITIVITY
vs
FREQUENCY
TX POWER
vs
FREQUENCY
3.2
3.4
3.6
G008
10
3-V Supply
TA = 25°C
Standard Gain Setting
2 Mbps, GFSK, 320 kHz deviation
8
Power Level (dBm)
Sensitivity Level (dBm)
2
G007
−80
−82
4
2
−88
−90
6
−84
−86
6
4
2
−88
−90
2400
3-V Supply
TA = 25°C
TXPOWER Setting = 0xE5
2420
2440
2460
Frequency (MHz)
0
2400
2480
2420
G009
Figure 16.
2440
2460
Frequency (MHz)
2480
G011
Figure 17.
RX INTERFERER REJECTION (SELECTIVITY)
vs
INTERFERER FREQUENCY
0
−10
Rejection (dBm)
−20
−30
−40
−50
3-V Supply
TA = 25°C
Standard Gain Setting
Wanted Signal at
2440 MHz with
−67 dBm Level
−60
−70
−80
−90
2400
2420
2440
2460
Frequency (MHz)
2480
G010
Figure 18.
20
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SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
TYPICAL CHARACTERISTICS (continued)
Table 2. Recommended Output Power Settings (1)
(1)
TXPOWER Register Setting
Typical Output Power (dBm)
0xE5
5
0xD5
4
0xC5
3
0xB5
2
0xA5
0
0x95
–2
0x85
–3
0x75
–4
0x65
–6
0x55
–8
0x45
–11
0x35
–13
0x25
–15
0x15
–17
0x05
–20
Measured on Texas Instruments CC2545 EM reference design with TA = 25°C, VDD = 3 V, and fc = 2440 MHz. See SWRU283 for
recommended register settings.
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CC2545
SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
www.ti.com
APPLICATION INFORMATION
APPLICATION INFORMATION
Few external components are required for the operation of the CC2545. A typical application circuit is shown in
Figure 19. For suggestions of component values other than those listed in Table 3, see reference design
CC2545EM. The performance stated in this data sheet is only valid for the CC2545EM reference design. To
obtain similar performance, the reference design should be copied as closely as possible.
2.0V-3.6V
Power Supply
Optional32-kHz Crystal
C421
XOSC32K_Q1
P1_5 37
P1_1 39
P1_2 38
VDD 41
P1_0 40
DCPL1 42
VSS 44
VDD 43
P3_6 46
P3_7 45
P3_5 47
P3_4 48
XOSC32K_Q1
1 P3_3
P1_6 36
2 P3_2
RBIAS 35
3 P3_1
VDD 34
4 P3_0
VDD 33
R351
Antenna
(50 Ohm)
VSS 32
5 P2_3
CC2545
6 P2_2
RF_N 31
RF_P 30
7 P2_1
8 P2_0
VSS 29
DIE ATTACH PAD:
VDD 28
9 P0_7
24 P1_3/DD
22 RESET_N
23 P1_4/DC
21 VDD
19 P2_5
20 P2_4
17 P2_7
18 P2_6
16 P0_0
VDD 25
15 P0_1
XOSC_Q1 26
12 P0_4
13 P0_3
XOSC_Q2 27
11 P0_5
14 P0_2
10 P0_6
C261
C271
Power supply decoupling capacitors are not shown
Digital I/O not connected
Figure 19. CC2545 Application Circuit
Table 3. Overview of External Components (Excluding Balun, Crystal and Supply Decoupling Capacitors)
Component
Description
Value
C421
Decoupling capacitor for the internal 1.8V digital voltage
regulator
1 µF
R351
Precision resistor ±1%, used for internal biasing
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2545EM,
for recommended balun.
22
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SWRS106B – JUNE 2012 – REVISED FEBRUARY 2013
Crystal
An external 32-MHz crystal with two loading capacitors is used for the 32-MHz crystal oscillator. The load
capacitance seen by the 32-MHz crystal is given by:
1
+ Cparasitic
CL =
1
1
+
C261 C271
(1)
A series resistor may be used to comply with ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C421) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
spacer
REVISION HISTORY
Changes from Original (June 2012) to Revision A
Page
•
Deleted Product Preview banner .......................................................................................................................................... 1
•
Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ......................................................................... 8
•
Changed Figure 19 ............................................................................................................................................................. 22
Changes from Revision A (August 2012) to Revision B
•
Page
Changed From: RTC Pin Package To: RGZ Pin Package ................................................................................................. 14
Copyright © 2012–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CC2545RGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2545
CC2545RGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CC2545
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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