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CCBTLV3257MPWREP

CCBTLV3257MPWREP

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP16

  • 描述:

    IC FET MULTI/DEMUX 4X2:1 16TSSOP

  • 数据手册
  • 价格&库存
CCBTLV3257MPWREP 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents SN74CBTLV3257-EP SCDS271A – MAY 2008 – REVISED MAY 2019 SN74CBTLV3257-EP Low-Voltage 4-Bit 1-of-2 FET Multiplexer/Demultiplexer 1 Features 2 Applications • • 1 • • • • • • • • • (1) Controlled baseline – One assembly site – One test site – One fabrication site Extended temperature performance of –55°C to 125°C Enhanced diminishing manufacturing sources (DMS) support Enhanced product-change notification Qualification pedigree (1) 5-Ω switch connection between two ports Rail-to-rail switching on data I/O ports Ioff supports partial-power-down mode operation Latch-up performance exceeds 100 mA per JESD 78, class II ESD protection exceeds JESD 22 – 2000-V human-body model (A114-A) – 200-V machine model (A115-A) Supports defense, aerospace, and medical applications 3 Description The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current does not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Device Information(1) PART NUMBER GRADE CCBTLV3257MPWREP TA = –55°C to 125°C PACKAGE TSSOP – PW Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. PW PACKAGE (TOP VIEW) S 1B1 1B2 1A 2B1 2B2 2A GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC OE 4B1 4B2 4A 3B1 3B2 3A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN74CBTLV3257-EP SCDS271A – MAY 2008 – REVISED MAY 2019 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 Absolute Maximum Ratings ...................................... 4 6.2 Recommended Operating Conditions....................... 4 6.3 Electrical Characteristics........................................... 5 6.4 Switching Characteristics .......................................... 5 7 8 Parameter Measurement Information .................. 6 Device and Documentation Support.................... 7 8.1 8.2 8.3 8.4 8.5 9 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2008) to Revision A Page • Changed ORDERING INFORMATION table to Device Information table.............................................................................. 1 • Added Applications section, Table of Contents, Revision History section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.............................................................................. 1 2 Submit Documentation Feedback Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP SN74CBTLV3257-EP www.ti.com SCDS271A – MAY 2008 – REVISED MAY 2019 5 Pin Configuration and Functions Table 1. Function Table INPUTS OE FUNCTION S L L A port = B1 port L H A port = B2 port H X Disconnect 4 2 1A 1B1 SW 3 1B2 SW 7 5 2A 2B1 SW 6 2B2 SW 3A 9 11 SW 3B1 10 SW 12 3B2 14 4A 4B1 SW 13 SW 4B2 1 S 15 OE Figure 1. Logic Diagram (Positive Logic) Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP Submit Documentation Feedback 3 SN74CBTLV3257-EP SCDS271A – MAY 2008 – REVISED MAY 2019 www.ti.com A B (OE) Figure 2. Simplified Schematic, Each FET Switch 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage –0.5 4.6 VI Input voltage (2) –0.5 4.6 V 128 mA Continuous channel current UNIT V IIK Input clamp current VIO < 0 –50 mA θJA Package thermal impedance PW package (3) 108 °C/W Tstg Storage temperature 150 °C (1) (2) (3) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. 6.2 Recommended Operating Conditions (1) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage TA Operating free-air temperature (1) 4 MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V V VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 –55 UNIT 125 V °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs. Submit Documentation Feedback Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP SN74CBTLV3257-EP www.ti.com SCDS271A – MAY 2008 – REVISED MAY 2019 6.3 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VIK VCC = 3 V, II = –18 mA –1.2 V II VCC = 3.6 V, VI = VCC or GND ±1 μA Ioff VCC = 0, VI or VO = 0 to 3.6 V 15 μA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 μA 300 μA ΔICC (2) Ci Cio(OFF) Control inputs VCC = 3.6 V, one input at 3 V, other inputs at VCC or GND Control inputs VI = 3 V or 0 A port B port 3 VO = 3 V or 0, OE = VCC VI = 0 VCC = 2.3 V, TYP at VCC = 2.5 V VI = 1.7 V ron (3) VI = 0 VCC = 3 V VI = 2.4 V (1) (2) (3) pF 10.5 pF 5.5 II = 64 mA 5 8 II = 24 mA 5 8 II = 15 mA 27 40 II = 64 mA 5 7 II = 24 mA 5 7 II = 15 mA 10 15 Ω All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 6.4 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) A or B (1) B or A S A or B 1.8 8.1 1.8 7.3 ten S A or B 1.7 7.5 1.7 6.5 ns tdis S A or B 1 6.3 1 6.0 ns ten OE A or B 1.9 7.1 2 6.2 ns tdis OE A or B 1 7.0 1.6 6.5 ns PARAMETER tpd (1) MIN MAX MIN 0.15 MAX 0.25 UNIT ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP Submit Documentation Feedback 5 SN74CBTLV3257-EP SCDS271A – MAY 2008 – REVISED MAY 2019 www.ti.com 7 Parameter Measurement Information 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ± 0.2 V 3.3 V ± 0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 VCC/2 Data Input 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC Output Control Output Waveform 2 S1 at GND (see Note B) VCC/2 VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP SN74CBTLV3257-EP www.ti.com SCDS271A – MAY 2008 – REVISED MAY 2019 8 Device and Documentation Support 8.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 8.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 8.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP Submit Documentation Feedback 7 SN74CBTLV3257-EP SCDS271A – MAY 2008 – REVISED MAY 2019 www.ti.com 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 8 Submit Documentation Feedback Copyright © 2008–2019, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3257-EP PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CCBTLV3257MPWREP ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CL257EP V62/08615-01XE ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CL257EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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CCBTLV3257MPWREP

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