CD4049UBPWRE4

CD4049UB, CD4050B CD4049UB, SCHS046K – AUGUST 1998 – REVISEDCD4050B JUNE 2020 SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com CD4049UB and CD4050B CMOS Hex Inverting Buffer and Converter 1 Features 3 Description • • • • • • The CD4049UB and CD4050B devices are inverting and noninverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logiclevel conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. (VCC = 5 V, VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.) • CD4049UB Inverting CD4050B Noninverting High Sink Current for Driving 2 TTL Loads High-to-Low Level Logic Conversion 100% Tested for Quiescent Current at 20 V Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V Parametric Ratings 2 Applications • • • CMOS to DTL or TTL Hex Converters CMOS Current Sink or Source Drivers CMOS High-to-Low Logic Level Converters Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) CD4049UBE, CD4050BE PDIP (16) 6.35 mm × 19.30 mm CD4049UBD, CD4050BD SOIC (16) 9.90 mm × 3.91 mm CD4049UBDW, CD4050BDW SOIC (16) 10.30 mm × 7.50 mm CD4049UBNS, CD4050BNS SO (16) 10.30 mm × 5.30 mm CD4049UBPW, CD4050BPW TSSOP (16) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VCC VCC P P P N N OUT R R IN IN OUT N VSS Copyright © 2016, Texas Instruments Incorporated VSS Copyright © 2016, Texas Instruments Incorporated 1 of 6 Identical Units 1 of 6 Identical Units Schematic Diagram of CD4049UB Schematic Diagram of CD4050B An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: CD4049UB CD4050B 1 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics: DC..................................... 5 6.6 Electrical Characteristics: AC......................................9 6.7 Typical Characteristics.............................................. 10 7 Parameter Measurement Information.......................... 11 7.1 Test Circuits...............................................................11 8 Detailed Description......................................................13 8.1 Overview................................................................... 13 8.2 Functional Block Diagram......................................... 13 8.3 Feature Description...................................................13 8.4 Device Functional Modes..........................................14 9 Application and Implementation.................................. 15 9.1 Application Information............................................. 15 9.2 Typical Application.................................................... 15 10 Power Supply Recommendations..............................16 11 Layout........................................................................... 16 11.1 Layout Guidelines................................................... 16 11.2 Layout Example...................................................... 16 12 Device and Documentation Support..........................17 12.1 Documentation Support.......................................... 17 12.2 Related Links.......................................................... 17 12.3 Receiving Notification of Documentation Updates..17 12.4 Support Resources................................................. 17 12.5 Trademarks............................................................. 17 12.6 Electrostatic Discharge Caution..............................17 12.7 Glossary..................................................................17 13 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (September 2016) to Revision K (June 2020) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated Device Information Table with correct package dimensions................................................................ 1 Changes from Revision I (May 2004) to Revision J (September 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1 • Changed Storage temperature minimum value from 65 to –65..........................................................................4 • Changed RθJA values for the CD4049UB device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.6, E (PDIP) from 67 to 49.5, NS (SO) from 64 to 84.3, and PW (TSSOP) from 108 to 108.9................................... 5 • Changed RθJA values for the CD4050B device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.2, E (PDIP) from 67 to 49.7, NS (SO) from 64 to 83.8, and PW (TSSOP) from 108 to 108.4................................... 5 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 5 Pin Configuration and Functions VCC 1 16 NC VCC 1 16 NC G 2 15 L G 2 15 L A 3 14 F A 3 14 F H 4 13 NC H 4 13 NC B 5 12 K B 5 12 K I 6 11 E I 6 11 E C 7 10 J C 7 10 J VSS 8 9 D VSS 8 9 D Not to scale Not to scale Figure 5-1. CD4049UB D, DW, N, NS, and PW Figure 5-2. CD4050B D, DW, N, NS, and PW Packages 16-Pin SOIC, PDIP, SO, and TSSOP Top Packages 1G6-Pin SOIC, PDIP, SO, and TSSOP Top View View Pin Functions: CD4049UB PIN NAME NO. I/O DESCRIPTION A 3 I Input 1 B 5 I Input 2 C 7 I Input 3 D 9 I Input 4 E 11 I Input 5 F 14 I Input 6 G 2 O Inverting output 1. G = A H 4 O Inverting output 2. H = B I 6 O Inverting output 3. I = C J 10 O Inverting output 4. J = D K 12 O Inverting output 5. K = E L 15 O Inverting output 6. L = F NC 13, 16 — No connection VCC 1 — Power pin VSS 8 — Negative supply Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 3 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 Pin Functions: CD4050B PIN NAME NO. I/O DESCRIPTION A 3 I Input 1 B 5 I Input 2 C 7 I Input 3 D 9 I Input 4 E 11 I Input 5 F 14 I Input 6 G 2 O Inverting output 1. G = A H 4 O Inverting output 2. H = B I 6 O Inverting output 3. I = C J 10 O Inverting output 4. J = D K 12 O Inverting output 5. K = E L 15 O Inverting output 6. L = F NC 13, 16 — No connection VCC 1 — Power pin VSS 8 — Negative supply 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.5 20 V Any one input ±10 mA SOIC, lead tips only 265 °C Supply voltage VCC to VSS DC input current, IIK Lead temperature (soldering, 10 s) Junction temperature, TJ Storage temperature, Tstg (1) –65 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) 4 VCC Supply voltage TA Operating temperature Submit Document Feedback MIN MAX 3 18 UNIT V –55 125 °C Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 6.4 Thermal Information CD4049UB THERMAL METRIC(1) CD4050B D (SOIC) DW (SOIC) E (PDIP) NS (SO) PW (TSSOP) D (SOIC) DW (SOIC) E (PDIP) NS (SO) PW (TSSOP) 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance(2) 81.6 81.6 49.5 84.3 108.9 81.6 81.2 49.7 83.8 108.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 41.5 44.5 36.8 43 43.7 41.5 44.1 37 42.5 43.2 °C/W RθJB Junction-to-board thermal resistance 39 46.3 29.4 44.6 54 39 45.9 29.6 44.1 53.5 °C/W ψJT Junction-to-top characterization parameter 10.7 16.5 21.7 12.8 4.6 10.7 16.1 21.9 12.5 4.5 °C/W ψJB Junction-to-board characterization parameter 38.7 45.8 29.3 44.3 53.4 38.7 45.4 29.5 43.8 52.9 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The package thermal impedance is calculated in accordance with JESD 51-7. 6.5 Electrical Characteristics: DC PARAMETER TEST CONDITIONS MIN TYP TA = –55 °C VIN = 0 or 10 V, VCC = 10 V IDD(Max) Quiescent device current TA = 25 °C 1 0.02 TA = 85 °C 30 30 TA = –55 °C 2 TA = –40 °C 2 0.02 VIN = 0 or 20 V, VCC = 20 V 2 TA = 85 °C 60 TA = 125 °C 60 TA = –55 °C 4 TA = –40 °C VIN = 0 or 15 V, VCC = 4 V 1 TA = 125 °C TA = 25 °C TA = 25 °C µA 4 0.02 4 TA = 85 °C 120 TA = 125 °C 120 TA = –55 °C 20 TA = –40 °C 20 TA = 25 °C UNIT 1 TA = –40 °C VIN = 0 or 5 V, VCC = 5 V MAX 0.04 20 TA = 85 °C 600 TA = 125 °C 600 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 5 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 PARAMETER TEST CONDITIONS MIN TYP TA = –55 °C TA = 25 °C 3.1 2.6 5.2 TA = 85 °C 2.1 TA = 125 °C 1.8 TA = –55 °C 4 TA = –40 °C VOUT = 0.4 V, VIN = 0 or 5 V, VCC = 5 V IOL(Min) Output low (sink) current VOUT = 0.5 V, VIN = 0 or 10 V, VCC = 10 V TA = 25 °C 3.8 3.2 6.4 TA = 85 °C 2.9 TA = 125 °C 2.4 TA = –55 °C 10 TA = –40 °C 9.6 TA = 25 °C 8 6.6 TA = 125 °C 5.6 TA = –55 °C 26 VOUT = 4.6 V, VIN = 0 or 5 V, VCC = 5 V TA = 25 °C 25 24 48 TA = 85 °C 20 TA = 125 °C 18 TA = –55 °C –0.81 TA = –40 °C –0.73 TA = 25 °C –0.65 –1.2 TA = 85 °C –0.58 TA = 125 °C –0.48 TA = –55 °C –2.6 TA = –40 °C VOUT = 2.5 V, VIN = 0 or 5 V, VCC = 5 V IOH(Min) Output high (source) current VOUT = 9.5 V, VIN = 0 or 10 V, VCC = 10 V TA = 25 °C –2.4 –2.1 –3.9 TA = 85 °C –1.9 TA = 125 °C –1.55 TA = –55 °C –2 TA = –40 °C –1.8 TA = 25 °C –1.65 –1.35 TA = 125 °C –1.18 TA = –55 °C –5.2 6 TA = 25 °C –4.8 –4.3 –8 TA = 85 °C –3.5 TA = 125 °C –3.1 Submit Document Feedback mA –3 TA = 85 °C TA = –40 °C VOUT = 1.3 V, VIN = 0 or 15 V, VCC = 15 V mA 16 TA = 85 °C TA = –40 °C VOUT = 1.5 V, VIN = 0 or 15 V, VCC = 15 V UNIT 3.3 TA = –40 °C VOUT = 0.4 V, VIN = 0 or 5 V, VCC = 4.5 V MAX Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 PARAMETER TEST CONDITIONS MIN TYP TA = –55 °C 0.05 TA = 25 °C 0 VIN = 0 or 10 V, VCC = 10 V VIN = 0 or 15 V, VCC = 15 V 0.05 TA = 125 °C 0.05 TA = –55 °C 0.05 0.05 TA = 25 °C 0 VOH(Min) Output voltage high level VIN = 0 or 10 V, VCC = 10 V TA = 85 °C 0.05 0.05 TA = –55 °C 0.05 TA = –40 °C 0.05 TA = 25 °C 0 0.05 TA = 125 °C 0.05 TA = –55 °C 4.95 TA = 25 °C 4.95 4.95 5 TA = 85 °C 4.95 TA = 125 °C 4.95 TA = –55 °C 9.95 TA = –40 °C 9.95 TA = 25 °C 9.95 10 9.95 TA = –55 °C 14.95 TA = –40 °C Input low voltage (CD4049UB) VIL(Max) Input low voltage (CD4050B) V 9.95 TA = 125 °C TA = 25 °C V 0.05 TA = 85 °C TA = 85 °C VIN = 0 or 15 V, VCC = 15 V 0.05 TA = 125 °C TA = –40 °C VIN = 0 or 5 V, VCC = 5 V 0.05 TA = 85 °C TA = –40 °C VOL(Max) Out voltage low level UNIT 0.05 TA = –40 °C VIN = 0 or 5 V, VCC = 5 V MAX 14.95 14.95 15 TA = 85 °C 14.95 TA = 125 °C 14.95 VOUT = 4.5 V, VCC = 5 V, Full temperature range 1 VOUT = 9 V, VCC = 10 V, Full temperature range 2 VOUT = 13.5 V, VCC = 15 V, Full temperature range 2.5 VOUT = 0.5 V, VCC = 5 V, Full temperature range 1.5 VOUT = 1 V, VCC = 10 V, Full temperature range 3 VOUT = 1.5 V, VCC = 15 V, Full temperature range 4 V Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 7 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 PARAMETER TEST CONDITIONS MIN TYP TA = –55 °C VIH(Min) Input high voltage (CD4049UB) TA = 25 °C 4 4 TA = 85 °C 4 TA = 125 °C 4 TA = –55 °C 8 TA = –40 °C VOUT = 1 V, VCC = 10 V VOUT = 1.5 V, VCC = 15 V TA = 25 °C 8 V 8 TA = 85 °C 8 TA = 125 °C 8 TA = –55 °C 12.5 TA = –40 °C 12.5 TA = 25 °C 12.5 TA = 85 °C 12.5 TA = 125 °C 12.5 TA = –55 °C 3.5 TA = –40 °C VOUT = 4.5 V, VCC = 5 V Input high voltage (CD4050B) VIH VOUT = 9 V, VCC = 10 V TA = 25 °C 3.5 3.5 TA = 85 °C 3.5 TA = 125 °C 3.5 TA = –55 °C 7 TA = –40 °C 7 TA = 25 °C 7 V TA = 85 °C 7 TA = 125 °C 7 TA = –55 °C 11 TA = –40 °C VOUT = 13.5 V, VCC = 15 V TA = 25 °C 11 11 TA = 85 °C 11 TA = 125 °C 11 TA = –55 °C ±0.1 TA = –40 °C IIN(Max) 8 Input current VIN = 0 or 18 V, VCC = 18 V ±0.1 ±10–5 TA = 25 °C ±0.1 TA = 85 °C ±1 TA = 125 °C ±1 Submit Document Feedback UNIT 4 TA = –40 °C VOUT = 0.5 V, VCC = 5 V MAX µA Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 6.6 Electrical Characteristics: AC TA = 25°C, Input tr and tf = 20 ns, CL = 50 pF, RL = 200 kΩ (unless otherwise noted) PARAMETER Propagation delay time Low to high (CD4049UB) tPLH Propagation delay time Low to high (CD4050B) Propagation delay time High to low (CD4049UB) tPHL Propagation delay time High to low (CD4050B) tTLH tTHL CIN Transition time Low to high Transition time High to low TEST CONDITIONS MIN TYP MAX VIN = 5 V, VCC = 5 V 60 120 VIN = 10 V, VCC = 10 V 32 65 VIN = 10 V, VCC = 5 V 45 90 VIN = 15 V, VCC = 15 V 25 50 VIN = 15 V, VCC = 5 V 45 90 VIN = 5 V, VCC = 5 V 70 140 VIN = 10 V, VCC = 10 V 40 80 VIN = 10 V, VCC = 5 V 45 90 VIN = 15 V, VCC = 15 V 30 60 VIN = 15 V, VCC = 5 V 40 80 VIN = 5 V, VCC = 5 V 32 65 VIN = 10 V, VCC = 10 V 20 40 VIN = 10 V, VCC = 5 V 15 30 VIN = 15 V, VCC = 15 V 15 30 VIN = 15 V, VCC = 5 V 10 20 VIN = 5 V, VCC = 5 V 55 110 VIN = 10 V, VCC = 10 V 22 55 VIN = 10 V, VCC = 5 V 50 100 VIN = 15 V, VCC = 15 V 15 30 VIN = 15 V, VCC = 5 V 50 100 VIN = 5 V, VCC = 5 V 80 160 VIN = 10 V, VCC = 10 V 40 80 UNIT ns ns ns ns ns VIN = 15 V, VCC = 15 V 30 60 VIN = 5 V, VCC = 5 V 30 60 VIN = 10 V, VCC = 10 V 20 40 VIN = 15 V, VCC = 15 V 15 30 15 22.5 pF 5 7.5 pF Input capacitance (CD4049UB) Input capacitance (CD4050B) ns Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 9 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 TA = 25oC TA = 25oC SUPPLY VOLTAGE (VCC) = 5V SUPPLY VOLTAGE (VCC) = 5V VO , OUTPUT VOLTAGE (V) 5 4 MINIMUM MAXIMUM 3 2 5 MINIMUM 4 MAXIMUM 3 2 1 1 1 2 3 0 4 1 2 Figure 6-2. Minimum and Maximum Voltage Transfer Characteristics for CD4050B IOL, OUTPUT LOW (SINK) CURRENT (mA) IOL, OUTPUT LOW (SINK) CURRENT (mA) Figure 6-1. Minimum and Maximum Voltage Transfer Characteristics for CD4049UB TA = 25oC 70 15V 10V 50 40 30 GATE TO SOURCE VOLTAGE (VGS) = 5V 20 10 0 1 2 3 4 5 6 7 TA = 25oC 70 15V 50 40 30 20 GATE TO SOURCE VOLTAGE (VGS) = 5V 10 0 8 1 -5 -4 -3 -2 -1 0 4 5 6 7 8 Figure 6-4. Minimum Output Low (Sink) Current Drain Characteristics -1 0 TA = 25oC TA = 25oC GATE TO SOURCE VOLTAGE VGS = -5V -10 -15 -20 -25 -10V -30 -15V -5 OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -5 GATE TO SOURCE VOLTAGE VGS = -5V -10V -10 -15 -20 -15V -25 -30 -35 Figure 6-5. Typical Output High (Source) Current Characteristics 10 3 VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 VDS, DRAIN TO SOURCE VOLTAGE (V) -6 2 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 6-3. Typical Output Low (Sink) Current Characteristics -7 10V 60 VDS , DRAIN TO SOURCE VOLTAGE (V) -8 4 VI , INPUT VOLTAGE (V) VI , INPUT VOLTAGE (V) 60 3 OUTPUT HIGH (SOURCE) 0 CURRENT CHARACTERISTICS VO , OUTPUT VOLTAGE (V) 6.7 Typical Characteristics -35 Figure 6-6. Minimum Output High (Source) Current Characteristics Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 10 9 SUPPLY VOLTAGE 8 VCC = 10V 125oC VO, OUTPUT VOLTAGE (V) VO, OUTPUT VOLTAGE (V) 10 7 6 TA = -55oC VCC = 5V 5 4 -55oC 3 125oC 2 9 6 4 3 1 0 3 4 -55oC 125oC 2 2 TA = -55oC VCC = 5V 5 1 1 VCC = 10V 7 0 0 SUPPLY VOLTAGE 125oC 8 0 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) 1 2 3 4 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) POWER DISSIPATION PER INVERTER (µW) Figure 6-7. Typical Voltage Transfer Characteristics Figure 6-8. Typical Voltage Transfer Characteristics as a Function of Temperature for CD4050B as a Function of Temperature for CD4049UB 105 TA = 25oC 104 SU 103 LY PP E AG LT O V V CC =1 5V V 10 V 10 5V LOAD CAPACITANCE CL = 50pF (11pF FIXTURE + 39pF EXT) CL = 15pF (11pF FIXTURE + 4pF EXT) 102 10 10 102 103 104 f, INPUT FREQUENCY (kHz) 105 Figure 6-9. Typical Power Dissipation versus Frequency Characteristics 7 Parameter Measurement Information 7.1 Test Circuits VCC VCC VCC INPUTS INPUTS OUTPUTS VIH + DVM VSS VIL VSS I DD Test any one input with other inputs at VCC or VSS. Figure 7-2. Input Voltage Test Circuit VSS Figure 7-1. Quiescent Device Current Test Circuit Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 11 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 VCC INPUTS CMOS 10V LEVEL TO DTL/TTL 5V LEVEL VCC = 5V OUTPUTS VCC OUTPUT TO DTL/TTL COS/MOS IN I INPUTS VSS 10V = VIH VSS 0 = VIL VSS IN Pin: A, B, C, D, E, or F B. OUT Pin: G, H, I, J, K, or L C. VCC Pin D. VSS Pin Measure inputs sequentially, to both VCC and VSS connect all unused inputs to either VCC or VSS. Figure 7-3. Input Current Test Circuit Figure 7-4. Logic Level Conversion Application VDD µF 0.1µF CL 10kHz, 100kHz, 1MHz I 1 2 3 4 5 6 7 8 CD4049UB 500 16 15 14 13 12 11 10 9 CL includes fixture capacitance. Figure 7-5. Dynamic Power Dissipation Test Circuits 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 8 Detailed Description 8.1 Overview The CD4049UB device is an inverting hex buffer; the CD4050B device is a noninverting hex buffer. These devices do logic-level conversions and have a high sink current that can drive two TTL loads. These devices also have low input current of 1 µA across the full temperature range at 18 V. The CD4049UB and CD4050B devices are designated as replacements for CD4009UB and CD4010B devices, respectively. Because the CD4049UB and CD4050B require only one power supply, they are preferred over the CD4009UB and CD4010B and should be used in place of the CD4009UB and CD4010B in all inverter, current driver, or logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Pin 16 (NC) is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. TI recommends the CD4069UB hex inverter is recommended for applications not requiring high sink-current or voltage conversion. 8.2 Functional Block Diagram CD4050B 3 2 A 5 4 B 7 10 D 11 12 E 14 A H=B B I=C C J=D D K= E E 15 F L= F F 2 G=A 5 6 C 9 3 G= A 4 H=B 7 6 I=C 9 10 J=D 11 12 K=E 14 1 15 L=F 1 VCC VCC 8 8 VSS VSS NC = 13 NC = 16 NC = 13 NC = 16 Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description CD4049UB and CD4050B have standardized symmetrical output characteristics and a wide operating voltage from 3 V to 18 V with quiescent current tested at 20 V. These devices have transition times of tTLH = 40 ns and tTHL = 20 ns (typical) at 10 V. The operating temperature is from –55°C to 125°C. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 13 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 8.4 Device Functional Modes Table 8-1 shows the functional modes for CD4049UB. Table 8-2 shows the functional modes for CD4050B. Table 8-1. Function Table for CD4049UB INPUT A, B, C, D, E, F OUTPUT G, H, I, J, K, L H L L H Table 8-2. Function Table for CD4050B 14 INPUT A, B, C, D, E, F OUTPUT G, H, I, J, K, L H H L L Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The CD4049UB and CD4050B devices have low input currents of 1 µA at 18 V over full package-temperature range and 100 nA at 18 V, 25°C. These devices have a wide operating voltage from 3 V to 18 V and used in high-voltage applications. 9.2 Typical Application VCC C Logic signal LED R Copyright © 2016, Texas Instruments Incorporated Figure 9-1. CD4049UB Application 9.2.1 Design Requirements The CD4049UB device is the industry's highest logic inverter operating at 18 V under recommended conditions. These devices have high sink current capabilities. 9.2.2 Detailed Design Procedure The recommended input conditions for Figure 9-1 includes rise time and fall time specifications (see Δt/ΔV in Recommended Operating Conditions) and specified high and low levels (see VIH and VIL in Recommended Operating Conditions). Inputs are not overvoltage tolerant and must be below VCC level because of the presence of input clamp diodes to VCC. The recommended output condition for the CD4049UB application includes specific load currents. Load currents must be limited so as to not exceed the total power (continuous current through VCC or GND) for the device. These limits are in the Absolute Maximum Ratings. Outputs must not be pulled above VCC. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 15 CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 10 102 103 104 POWER DISSIPATION PER INVERTER (µW) POWER DISSIPATION PER INVERTER (µW) 9.2.3 Application Curves 106 TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 1 10 105 102 tr, tf , INPUT RISE AND FALL TIME (ns) 106 107 103 104 105 tr, tf , INPUT RISE AND FALL TIME (ns) 108 Figure 9-2. Typical Power Dissipation vs Input Rise Figure 9-3. Typical Power Dissipation vs Input Rise and Fall Times Per Inverter for CD4049UB and Fall Times Per Buffer for CD4050B 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating in Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC pins, then TI recommends a 0.01-µF or 0.022-µF capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must never float. In many cases, digital logic device functions or parts of these functions are unused (for example, when only two inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. This rule must be observed under all circumstances specified in the next paragraph. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. See Implications of Slow or Floating CMOS Inputs for more information on the effects of floating inputs. The logic level must apply to any particular unused input depending on the function of the device. Generally, they are tied to GND or VCC (whichever is convenient). 11.2 Layout Example VCC Unused Input Input Output Unused Input Output Input Figure 11-1. Layout Diagram 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs (SCBA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY CD4049UB Click here Click here Click here Click here Click here CD4050B Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks TI E2E™ is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD4049UBD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBDWG4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM Samples CD4049UBE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4049UBE Samples CD4049UBEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4049UBE Samples CD4049UBF ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD4049UBF Samples CD4049UBF3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD4049UBF3A Samples CD4049UBNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UB Samples CD4049UBPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM049UB Samples CD4049UBPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM049UB Samples CD4050BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM Samples CD4050BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM Samples CD4050BDT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM Samples CD4050BDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD4050BDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM Samples CD4050BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4050BE Samples CD4050BEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4050BE Samples CD4050BF ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD4050BF Samples CD4050BF3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD4050BF3A Samples CD4050BNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050B Samples CD4050BPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM050B Samples CD4050BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM050B Samples JM38510/05553BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 05553BEA Samples JM38510/05554BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 05554BEA Samples M38510/05553BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 05553BEA Samples M38510/05554BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 05554BEA Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of