CD74HC164E

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 CDx4HC164, CDx4HCT164 High-Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register 1 Features 2 Description • • • The ’HC164 and ’HCT164 are 8-bit serial-in parallelout shift registers with asynchronous reset. Data is shifted on the positive edge of Clock (CLK). A LOW on the Reset (CLR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (A and B) are provided, either one can be used as a Data Enable control. Buffered inputs Asynchronous reset Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25 °C Fanout (over temperature range) – Standard Outputs : 10 LSTTL loads – Bus driver outputs : 15 LSTTL loads Wide operating temp range : – 55 °C to 125 °C Balanced propagation delay and transition times Significant power reduction compared to LSTTL logic ICs HC types – 2 V to 6 V operation – High noise immunity : NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) – CMOS input compatibility, II ≤ 1 μA at VOL, VOH • • • • • • Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HC164M SOIC (14) 8.65 mm × 3.90 mm CD74HCT164M SOIC (14) 8.65 mm × 3.90 mm CD74HC164E PDIP (14) 19.31 mm × 6.35 mm CD74HCT164E PDIP (14) 19.31 mm × 6.35 mm CD54HC164F CDIP (14) 19.55 mm × 6.71 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 8 CLK 1 A B 2 D Q D R Q D R Q D R Q D R D Q Q D R R Q D R Q R 9 CLR 4 3 QA 5 QB 6 QC 10 QD 11 QE 12 QF 13 QG Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. QH CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Prerequisite for Switching Characteristics ................. 6 5.6 Switching Characteristics ...........................................7 6 Parameter Measurement Information............................ 8 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Device Functional Modes............................................9 8 Power Supply Recommendations................................10 9 Layout.............................................................................10 9.1 Layout Guidelines..................................................... 10 10 Device and Documentation Support..........................11 10.1 Documentation Support.......................................... 11 10.2 Receiving Notification of Documentation Updates.. 11 10.3 Support Resources................................................. 11 10.4 Trademarks............................................................. 11 10.5 Electrostatic Discharge Caution.............................. 11 10.6 Glossary.................................................................. 11 11 Mechanical, Packaging, and Orderable Information.................................................................... 11 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2003) to Revision D (March 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect modern data sheet standards............................................................................................................................. 1 • Updated naming conventions to reflect modern TI function. DS1 is now A; DS2 is now B; Q0 is now QA; Q1 is now QB; Q2 is now QC; Q3 is now QD; CP is now CLK; MR is now CLR; Q4 is now QE; Q5 is now QF; Q6 is now QG; Q7 is now QH ....................................................................................................................................... 3 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 4 Pin Configuration and Functions A B 1 14 VCC 2 13 QH QA QB 3 12 4 11 QG QF QC QD 5 10 6 9 CLR GND 7 8 CLK QE J, D, and N Package 14-Pin CDIP, SOIC, and PDIP Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 3 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range (2) IIK Input clamp current IOK Output clamp current IO Continuous output current (2) MIN MAX -0.5 7 Junction temperature Tstg Storage temperature (1) (2) V (VI < 0 or VI > VCC) ±20 mA (VO < 0 or VO > VCC) ±20 mA (VO = 0 to VCC) ±25 mA ±50 mA 150 °C 150 °C Continuous current through VCC or GND TJ UNIT -65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 5.2 Recommended Operating Conditions VCC Supply voltage range VI, VO Input or output voltage HC types HCT types MIN MAX 2 6 4.5 5.5 0 VCC 2V Input rise and fall time V V 1000 4.5 V 500 6V TA UNIT ns 400 Temperature range –55 125 ℃ 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance(1) D (SOIC) N (PDIP) 14 PINS 14 PINS UNIT 86 80 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(1) VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage II Input leakage current ICC Supply current 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 IOH = – 4 mA 4.5 3.98 3.84 3.7 IOH = – 5.2 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 5.34 V V 5.2 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 IOL = 4 mA 4.5 0.26 0.33 0.4 IOL = 5.2 mA 6 0.26 0.33 0.4 V 6 ±0.1 ±1 ±1 μA 6 8 80 160 μA VI = VCC or GND V HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 2 0.8 2 0.8 V 0.8 V High level output voltage IOH = – 20 μA 4.5 4.4 4.4 4.4 High level output voltage IOH = – 4 μA 4.5 3.98 3.84 3.7 Low level output voltage IOL = 20 μA 4.5 Low level output voltage IOL = 4 μA 4.5 0.26 0.33 0.4 5.5 ±0.1 ±1 ±1 μA 8 80 160 μA V 0.1 0.1 0.1 V II Input leakage current VI = VCC or GND ICC Supply current VI = VCC or GND 5.5 Date Shift-In (1,2) 4.5 to 5.5 100 108 135 147 μA CLR 4.5 to 5.5 100 324 405 441 μA CLK 4.5 to 5.5 100 252 315 343 μA ΔICC (2) (3) (1) (2) (3) Additional supply current per input pin VI = VIH or VIL, unless otherwise noted. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. Inputs held at VCC – 2.1. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 5 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 5.5 Prerequisite for Switching Characteristics PARAMETER VCC (V) 25°C MIN – 40°C to 85°C MAX MIN MAX – 55°C to 125°C MIN MAX UNIT HC TYPES fMAX tW tw tSU tH tREM Maximum clock frequency CLR pulse width CLK pulse width Set-up time Hold time CLR to clock, Removal time 2 6 5 4 MHz 4.5 30 24 20 MHz 6 35 28 24 MHz 2 60 75 90 ns 4.5 12 15 18 ns 6 10 13 15 ns 2 80 100 120 ns 4.5 16 20 24 ns 6 14 17 20 ns 2 60 75 90 ns 4.5 12 15 18 ns 6 10 13 15 ns 2 4 4 4 ns 4.5 4 4 4 ns 6 4 4 4 ns 2 80 100 120 ns 4.5 16 20 24 ns 6 14 17 20 ns 4.5 27 22 18 MHz HCT TYPES 6 fMAX Maximum clock frequency tW CLR pulse width 6 18 23 27 ns tW CLK pulse width 4.5 18 23 27 ns tSU Set-up time tH Hold time tREM CLR to clock, Removal time Submit Document Feedback 6 12 15 18 ns 4.5 4 4 4 ns 6 16 20 24 ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 5.6 Switching Characteristics Input tr, tf = 6ns. CL = 50pF unless otherwise noted PARAMETER VCC (V) – 40°C to 85°C 25°C TYP – 55°C to 125°C UNIT MAX MAX MAX 170 212 255 ns 34 43 51 ns HC TYPES 2 tPLH, tPHL tPLH, tPHL 4.5 CLK to Q CLR to Q 6 29 36 43 ns 2 140 175 210 ns 4.5 tTLH, tTHL Output transition times fMAX Maximum clock frequency CIN Input capacitance CPD Power dissipation capacitance(1) (2) 14(3) 11(3) 28 35 42 ns 6 24 30 36 ns 2 75 110 ns 4.5 15 22 ns 13 19 ns 6 5 60(3) 5 47 ns 10 10 10 pF pF HCT TYPES tPLH, tPHL 4.5 CLK to Q 5 4.5 tPLH, tPHL CLR to Q tTLH, tTHL Output Transition time CIN Input Capacitance fMAX Maximum clock frequency CPD Power dissipation capacitance(1) (2) (1) (2) (3) (4) 5 36 45 54 ns 38 46 57 ns 15 19 22 ns 15(3) 16(3) 4.5 pF 54(4) 5 49 MHz 10 10 10 pF CPD is used to determine the dynamic power consumption, per device. PD = VCC 2fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CL = 15pF. VCC = 5. CL = 15pF. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 7 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. tw VCC VCC Input 50% Clock Input 50% 50% 0V 0V Figure 6-1. Voltage Waveforms, Standard CMOS Inputs Pulse Duration th tsu VCC Data Input 50% 50% 0V Figure 6-2. Voltage Waveforms, Standard CMOS Inputs Setup and Hold Times tw 3V 3V Input 1.3V Clock Input 1.3V 1.3V 0V 0V Figure 6-3. Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration tsu th 3V Data Input 1.3V 1.3V 0V Figure 6-4. Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 7 Detailed Description 7.1 Overview The ’HC164 and ’HCT164 are 8-bit serial-in parallel-out shift registers with asynchronous reset. Data is shifted on the positive edge of Clock (CLK). A LOW on the Reset (CLR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (A and B) are provided, either one can be used as a Data Enable control. 7.2 Functional Block Diagram 8 CLK 1 A B 2 D Q D R Q D R Q D R Q D R D Q Q D R R Q D R Q R 9 CLR 4 3 QA 5 QB 6 QC 10 QD 11 QE 12 QF 13 QG QH Figure 7-1. Functional Block Diagram 7.3 Device Functional Modes Truth Table(1) OPERATING MODE (1) INPUTS OUTPUTS CLR CLK A B QA QB- QH RESET (CLEAR) L X X X L L-L Shift H ↑ I I L qA - qF H ↑ I h L qA - qF H ↑ h I L qA - qF H ↑ h h H qA - qF H = High voltage level. h = High voltage level one set-up time prior to the low-to-high clock transition. I = Low voltage level one set-up time prior to the low-to-high clock transition. L = Low voltage level. X = Don't care. ↑ = Transition from low to high level. qn = Lower case letters indicate the state of the reference input clock transition. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 9 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 www.ti.com SCHS155D – NOVEMBER 1998 – REVISED MARCH 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. 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Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC164 CD74HC164 CD54HCT164 CD74HCT164 11 PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8970401CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8970401CA CD54HCT164F3A Samples CD54HC164F ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC164F Samples CD54HC164F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8416201CA CD54HC164F3A Samples CD54HCT164F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8970401CA CD54HCT164F3A Samples CD74HC164E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC164E Samples CD74HC164M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M Samples CD74HC164M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M Samples CD74HC164M96G4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M Samples CD74HC164ME4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M Samples CD74HC164MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M Samples CD74HCT164E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT164E Samples CD74HCT164M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M Samples CD74HCT164M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 (HCT164, HCT164M) Samples CD74HCT164M96E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 (HCT164, HCT164M) Samples CD74HCT164MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of