CD74HC173PWT

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 CDx4HC173, CDx4HCT173 High-Speed CMOS Logic Quad D-Type Flip-Flop, ThreeState 1 Features 2 Description • • • The CDx4HC173 and CDx4HCT173 contains four independent D-type flip-flops with shared clock (CP), reset (MR), and data enable (E1, E2) pins. • • • • • Three-state buffered outputs Gated input and output enables Fanout (over temperature range) – Standard outputs : 10 LSTTL loads – Bus driver outputs : 15 LSTTL loads Wide Operating Temperature Range : -55°C to 125°C Balanced propagation delay and transition times Significant power and reduction compared to LSTTL logic ICs HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V Operation – Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min) – CMOS input compatibility, Il ≤ 1µA at VOL, VOH Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD54HC173F CDIP (16) 21.34 mm × 6.92 mm CD54HCT173F3A CDIP (16) 21.34 mm × 6.92 mm CD74HC173E PDIP (16) 19.31mm × 6.35 mm CD74HCT173E PDIP (16) 19.31mm × 6.35 mm CD74HC173M SOIC (16) 9.90 mm × 3.90 mm CD74HCT173M SOIC (16) 9.90 mm × 3.90 mm CD74HC173PW TSSOP (16) 5.00 mm × 4.40 mm (1) For all packages see the orderable addendum at the end of the data sheet.. OE1 OE2 E1 E2 CP MR Shared Control Logic One of Four D-Type Flip-Flops D Dx Q Qx R Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings ....................................... 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics............................................6 5.6 Prerequisite For Switching Characteristics................. 7 6 Parameter Measurement Information............................ 8 7 Detailed Description......................................................10 7.1 Overview................................................................... 10 7.2 Functional Block Diagram......................................... 10 7.3 Device Functional Modes..........................................11 8 Power Supply Recommendations................................12 9 Layout.............................................................................12 9.1 Layout Guidelines..................................................... 12 10 Device and Documentation Support..........................13 10.1 Documentation Support.......................................... 13 10.2 Receiving Notification of Documentation Updates..13 10.3 Support Resources................................................. 13 10.4 Trademarks............................................................. 13 10.5 Electrostatic Discharge Caution..............................13 10.6 Glossary..................................................................13 11 Mechanical, Packaging, and Orderable Information.................................................................... 13 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2003) to Revision F (March 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 4 Pin Configuration and Functions J, N, D, or PW Package 16-Pin CDIP, PDIP, SOIC, or TSSOP Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 3 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 5 Specifications 5.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VCC Supply voltage IIK Input diode current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current(2) VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Output source or sink current per output pin VO > –0.5 V or VO < VCC + 0.5 V ±25 mA Continuous current through VCC or GND ±70 mA Junction temperature 150 °C 300 °C 150 °C TJ –0.5 UNIT 7 Lead temperature (soldering 10s) (SOIC - lead tips only) Tstg (1) (2) Storage temperature –65 V Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 5.2 Recommended Operating Conditions MIN UNIT 2 6 4.5 5.5 Input voltage 0 VCC V Output voltage 0 VCC V VCC Supply voltage range VI VO tt Input rise and fall time TA Temperature range HC types MAX HCT types VCC = 2V V 1000 VCC = 4.5V 500 VCC = 6V ns 400 -55 125 °C 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal (1) resistance N (PDIP) D (SOIC) NS (SOP) PW (TSSOP) 16 PINS 16 PINS 16 PINS 16 PINS UNIT 67 73 64 108 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 5.4 Electrical Characteristics TEST (1) CONDITIONS PARAMETER VCC 25°C MIN TYP –40°C to 85°C MAX MIN MAX –55°C to 125°C MIN MAX UNIT HC TYPES VIH VIL High-level input voltage Low-level input voltage High-level output voltage CMOS loads VOH High-level output voltage TTL loads Low-level output voltage CMOS loads VOL 2 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 6 4.2 4.2 4.2 V 2 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 6 1.8 1.8 1.8 V IOH = – 20μA 2 1.9 1.9 1.9 V IOH = – 20μA 4.5 4.4 4.4 4.4 V IOH = – 20μA 6 5.9 5.9 5.9 V IOH = – 6mA 4.5 3.98 3.84 3.7 V 6 5.48 5.34 5.2 V IOH = – 7.8mA IOL = 20μA 2 0.1 0.1 0.1 V IOL = 20μA 4.5 0.1 0.1 0.1 V IOL = 20μA 6 0.1 0.1 0.1 V Low-level output voltage TTL loads IOL = 6mA 4.5 0.26 0.33 0.4 V IOL = 7.8mA 6 0.26 0.33 0.4 V II Input leakage current VCC or GND 6 ±0.1 ±1 ±1 µA ICC Supply current VCC or GND 6 8 80 160 µA IOZ Three-state leakage current 6 ±0.5 ±0.5 ±10 µA HCT TYPES VIH High-level input voltage 4.5 to 5.5 VIL Low-level input voltage 4.5 to 5.5 2 2 0.8 2 0.8 V 0.8 V High-level output voltage CMOS loads IOH = – 20μA 4.5 4.4 4.4 4.4 V High-level output voltage TTL loads IOH = – 6mA 4.5 3.98 3.84 3.7 V Low-level output voltage CMOS loads IOL = 20μA 4.5 0.1 0.1 0.1 V Low-level output voltage TTL loads IOL = 6mA 4.5 0.26 0.33 0.4 V II Input leakage current VCC and GND 5.5 ±0.1 ±1 ±1 µA ICC Supply Current VCC and GND 5.5 8 80 160 µA One of D0-D3 4.5 to 5.5 15 54 67.5 73.5 µA One of E1 and E2 4.5 to 5.5 15 54 67.5 73.5 µA CP 4.5 to 5.5 25 90 112.5 122.5 µA MR 4.5 to 5.5 20 72 90 98 µA One of OE1 and OE2 4.5 to 5.5 50 180 225 245 µA VOH VOL ∆ICC (2) (3) Additional supply current per input pin Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 5 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 TEST (1) CONDITIONS PARAMETER Three-state leakage current IOZ (1) (2) (3) VCC 25°C MIN TYP 5.5 –40°C to 85°C MAX MIN ±0.5 MAX –55°C to 125°C MIN MAX ±5.0 ±10 UNIT µA VI = VIH or VIL, unless otherwise noted. For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. Inputs held at VCC – 2.1. 5.5 Switching Characteristics Input tt = 6ns. Unless otherwise specified, CL = 50pF PARAMETER VCC(V) -40°C to 85°C 25°C TYP -55°C to 125°C UNIT MAX MAX MAX 200 250 300 40 50 60 34 43 51 175 220 265 35 44 53 HC TYPES 2 Propagation delay, clock to output tpd 4.5 17 (1) 6 2 tpd Propagation delay, MR to output Propagation delay output enable to Q (Figure 6) tpd 4.5 12 (1) 6 30 37 45 2 150 190 225 4.5 12 (1) 30 38 45 6 26 33 38 2 60 75 90 4.5 12 15 18 10 13 15 ns ns ns tt Output transition times fMAX Maximum clock frequency Ci Input capacitance 10 10 10 pF CO Three-state output capacitance 10 10 10 pF 6 Cpd (2) (3) Power dissipation capacitance 5 5 60 (1) ns MHz 29 pF HCT TYPES Propagation delay, clock to output tpd 4.5 17 (1) 40 50 60 ns 18 (1) 44 55 66 ns 150 190 225 14 (1) 30 38 45 tpd Propagation delay, MR to output 4.5 tpd Propagation delay output enable to Q (Figure 6) 4.5 6 26 33 38 tt Output transition times 4.5 15 19 22 10 10 10 2 fMAX Maximum clock frequency Ci Input capacitance Cpd (1) (2) (3) 6 (2) (3) Power dissipation capacitance 5 5 60 (1) ns ns MHz 34 pF pF Typical value tested at 5V, CL = 15pF. CPD is used to determine th edynamic power consumption, per package. PD = VCC 2fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 5.6 Prerequisite For Switching Characteristics PARAMETER VCC(V) 25°C MIN -40°C to 85°C MAX MIN -55°C to 125°C MAX MIN MAX UNITS HC TYPES fMAX tW tW tSU tH tH tREM Maximum clock frequency MR pulse width Clock pulse width Set-up time, data to clock and E to clock Hold time, data to clock Hold time, E to clock Removal time, MR to clock 2 6 5 4 4.5 30 24 20 6 35 28 24 2 80 100 120 4.5 16 20 24 6 14 17 20 2 80 100 120 4.5 16 20 24 6 14 17 20 2 60 75 90 4.5 12 15 18 6 10 13 15 2 3 3 3 4.5 3 3 3 6 3 3 3 2 0 0 0 4.5 0 0 0 6 0 0 0 2 60 75 90 4.5 12 15 18 6 10 13 15 MHz ns ns ns ns ns ns HCT TYPES fMAX Maximum clock frequency 4.5 20 16 13 MHz tWtW MR pulse width 4.5 15 19 22 ns tW Clock pulse width 4.5 25 31 38 ns tSU Set-up Time, E to clock 4.5 12 15 18 ns tSU Set-up time, data to clock 4.5 18 23 27 ns tH Hold time, data to clock 4.5 0 0 0 ns tH Hold time, E to clock 4.5 0 0 0 ns tREM Removal time, MR to clock 4.5 12 15 18 ns Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 7 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 6 Parameter Measurement Information tPD is the maximum between tPLH and tPHL tt is the maximum between tTLH and tTHL NOTE: Outputs should be switching from 10% VCC to NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For 90% VCC in accordance with device truth table. FOr fMAX, input duty cycle = 50% fMAX, input duty cycle = 50% Figure 6-1. HC clock pulse rise and fall times and Figure 6-2. HCT clock pulse rise and fall times and pulse width pulse width Figure 6-3. HC and HCU transition times and propagation delay times, combination logic 8 Submit Document Feedback Figure 6-4. HCT transition times and propagation delay times, combination logic Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 Figure 6-5. HC setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits Figure 6-7. HC three-state propagation delay waveform Figure 6-6. HCT setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits Figure 6-8. HCT three-state propagation delay waveform NOTE: Opend drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF Figure 6-9. HC and HCT three-state propagation delay test circuit Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 9 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 7 Detailed Description 7.1 Overview The CDx4HC173 or CDx4HCT173 high speed three-state quad Dtype flip-flops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive 15 LSTTL loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus lines in bus oriented systems The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic “1” level. The input ENABLES allow the flip-flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic “1” level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is enabled by taking the RESET (MR) input to a logic “1” level. The data outputs change state on the positive going edge of the clock. The ’HCT173 logic family is functionally, as well as pin compatible with the standard LS logic family. 7.2 Functional Block Diagram OE1 OE2 E1 E2 CP MR Shared Control Logic One of Four D-Type Flip-Flops D Dx 10 Submit Document Feedback Q Qx R Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 7.3 Device Functional Modes (1)(2) Table 7-1. Truth Table INPUTS (1) (2) MR CP H L DATA ENABLE DATA OUTPUT Qn E1 E2 D X X X X L L X X X Q0 L ↑ H X X Q0 L ↑ X H X Q0 L ↑ L L L L L ↑ L L H H H = High voltage level. L = Low voltage level. X = Irrelevant. ↑ = Transition from low to high level. Q0 = Level before the indicated steady-state input conditions were established. When either OE1 or OE2 (or both) is (are) high, the output is disabled to the high-impedance stat, however, sequential operation of the flip-flops is not affected. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 11 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 www.ti.com SCHS158F – NOVEMBER 1998 – REVISED MARCH 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8682501EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8682501EA CD54HC173F3A Samples 5962-8875901EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8875901EA CD54HCT173F3A Samples CD54HC173F ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC173F Samples CD54HC173F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8682501EA CD54HC173F3A Samples CD54HCT173F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8875901EA CD54HCT173F3A Samples CD74HC173E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC173E Samples CD74HC173M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M Samples CD74HC173M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M Samples CD74HC173PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ173 Samples CD74HC173PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ173 Samples CD74HCT173E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT173E Samples CD74HCT173M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M Samples CD74HCT173M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of