CD54HC138, CD74HC138, CD54HCT138, CD74HCT138, CD54HC238, CD74HC238, CD54HCT238,
CD74HCT238
SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
CDx4HC138, CDx4HCT138, CDx4HC238, CDx4HCT238 High-Speed CMOS Logic 3- to
8-Line Decoder/Demultiplexer Inverting and Noninverting
1 Features
2 Description
•
The CDx4HC(T)138 and '238 are three to eight
decoders with one standard output strobe (G2) and
two active low output strobes (G 1 and G 0). When the
outputs are gated by any of the strobe inputs, they are
all forced into the high state. When the outputs are not
disabled by the strobe inputs, only the selected output
is low while all others are high.
Select one of eight data outputs:
– Active low for '138
– Active high for '238
l/O port or memory selector
Three enable inputs to simplify cascading
Typical propagation delay of 13 ns at VCC = 5 V, CL
= 15 pF, TA = 25°C
Fanout (over temperature range)
– Bus driver outputs: 15 LSTTL loads
– Standard outputs: 10 LSTTL loads
Wide operating temp range: -55°C to 125°C
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5-V to 5.5-V operation
– Direct LSTTL input logic compatibility, VIL= 0.8
V (Max), VIH = 2 V (Min)
– CMOS input compatibility, Il ≤ 1µA at VOL, VOH
•
•
•
•
•
•
•
•
•
3:8 DECODER
OUTPUT
ENABLE
000
Y0
A0
001
Y1
A1
The CDx4HC(T)238 is a three to eight decoder with
one standard output strobe (G2) and two active low
output strobes (G 1 and G 0). When the outputs are
gated by any of the strobe inputs, they are all forced
into the low state. When the outputs are not disabled
by the strobe inputs, only the selected output is high
while all others are low.
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HC138E
PDIP (16)
25.40 mm × 6.35 mm
CD74HCT138E
PDIP (16)
25.40 mm × 6.35 mm
CD74HCT238E
PDIP (16)
25.40 mm × 6.35 mm
CD74HC138M
SOIC (16)
9.90 mm × 3.90 mm
CD74HCT238M
SOIC (16)
9.90 mm × 3.90 mm
CD74HC238NS
SO (16)
10.20 mm × 5.30 mm
CD74HC238PW
TSSOP (16)
5.00 mm × 4.40 mm
CD74HCT238PW
TSSOP (16)
5.00 mm × 4.40 mm
CD54HC138F
CDIP (16)
21.34 mm × 6.92 mm
CD54HCT138F
CDIP (16)
21.34 mm × 6.92 mm
CD54HCT238F
CDIP (16)
21.34 mm × 6.92 mm
010
Y2
A2
011
Y3
G0
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
100
Y4
G1
101
Y5
G2
110
Y6
111
Y7
Functional Block Diagram '138
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC138, CD74HC138, CD54HCT138, CD74HCT138, CD54HC238, CD74HC238, CD54HCT238,
CD74HCT238
SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
(2)
5.5 Switching Characteristics ........................................ 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Documentation Support.......................................... 12
10.2 Receiving Notification of Documentation Updates..12
10.3 Support Resources................................................. 12
10.4 Trademarks............................................................. 12
10.5 Electrostatic Discharge Caution..............................12
10.6 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (August 2004) to Revision J (November 2021)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern datasheet standards.............................................................................................................................. 1
• Updated pin names to match current TI naming conventions. E3 is now G2, E 2 is now G 1, E 1 is now G 0 .... 1
2
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SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
4 Pin Configuration and Functions
A0
1
16
VCC
A1
2
Y0
A2
G0
3
15
14
4
13
G1
5
12
Y2
Y3
G2
Y7
6
11
Y4
7
8
10
Y5
Y6
GND
9
Y1
J, N, D, NS, or PW package
16-Pin CDIP, PDIP, SOIC, SO, or TSSOP
Top View
Pin Functions
PIN
SOIC or TSSOP
NO.
NAME
I/O(1)
DESCRIPTION
1
A0
I
Address select 0
2
A1
I
Address select 1
3
A2
I
Address select 2
4
G0
I
Output strobe 0, active low
5
G1
I
Output strobe 1, active low
6
G2
I
Output strobe 2
7
Y7
O
Output 7
8
GND
—
Ground
9
Y6
O
Output 6
10
Y5
O
Output 5
11
Y4
O
Output 4
12
Y3
O
Output 3
13
Y2
O
Output 2
14
Y1
O
Output 1
15
Y0
O
Output 0
16
VCC
—
Positive supply
(1)
Signal Types: I = Input, O = Output, I/O = Input or Output.
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SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
-0.5
7
UNIT
VCC
Supply voltage
IIK
Input clamp diode current
For VI < 0.5V or VI > VCC + 0.5V
±20
mA
IOK
Output clamp diode current
For VO < -0.5V or VO > VCC + 0.5V
±20
mA
IO
Output source or sink current per output
pin
For VO > -0.5V or VO < VCC + 0.5V
±25
mA
±50
mA
150
°C
150
°C
300
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
-65
Lead temperature (Soldering 10s) (SOIC - Lead Tips Only)
(1)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions
MIN
UNIT
2
6
4.5
5.5
Input voltage
0
VCC
V
Output voltage
0
VCC
V
VCC
Supply voltage range
VI
VO
tt
Input rise and fall time
TA
Temperature range
HC types
MAX
HCT types
VCC = 2V
V
1000
VCC = 4.5V
500
VCC = 6V
ns
400
-55
125
°C
5.3 Thermal Information
CD74HC(T)138, CD74HC(T)238
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal
resistance(1)
N
(PDIP)
D
(SOIC)
NS
(SOP)
PW
(TSSOP)
16 Pins
16 Pins
16 Pins
16 Pins
UNIT
67
73
64
108
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
5.4 Electrical Characteristics
PARAMETER
TEST
(1)
CONDITIONS
VCC(V)
25°C
MIN
TYP
-40°C to 85°C
MAX
MIN
MAX
-55°C to 125°C
MIN
MAX
UNIT
HC TYPES
VIH
VIL
High-level input
voltage
Low-level input
voltage
High-level output
voltage
VOH
High-level output
voltage
Low-level output
voltage
VOL
Low-level output
voltage
2
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
V
6
4.2
4.2
4.2
V
2
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
V
6
1.8
1.8
1.8
V
IOH = – 20 μA
2
1.9
1.9
1.9
V
IOH = – 20 μA
4.5
4.4
4.4
4.4
V
IOH = – 20 μA
6
5.9
5.9
5.9
V
IOH = – 4 mA
4.5
3.98
3.84
3.7
V
IOH = – 5.2 mA
6
5.48
IOL = 20 μA
2
0.1
0.1
0.1
V
IOL = 20 μA
4.5
0.1
0.1
0.1
V
IOL = 20 μA
6
0.1
0.1
0.1
V
5.34
5.2
V
IOL = 4 mA
4.5
0.26
0.33
0.4
V
IOL = 5.2 mA
6
0.26
0.33
0.4
V
II
Input leakage
current
VI = VCC or GND
6
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or GND
6
8
80
160
µA
HCT TYPES
VIH
High-level input
voltage
4.5 to
5.5
VIL
Low-level input
voltage
4.5 to
5.5
VOH
VOL
2
2
0.8
2
0.8
V
0.8
V
High-level output
voltage
IOH = – 20 μA
4.5
4.4
4.4
4.4
V
High-level output
voltage
IOH = – 4 mA
4.5
3.98
3.84
3.7
V
Low-level output
voltage
IOL = 20 μA
4.5
0.1
0.1
0.1
V
Low-level output
voltage
IOH = 4 mA
4.5
0.26
0.33
0.4
V
5.5
±0.1
±1
±1
µA
8
80
160
µA
II
Input leakage
current
VI = VCC and GND
ICC
Supply current
VI = VCC and GND
5.5
A0 - A2 inputs held
at VCC – 2.1 V
4.5 to
5.5
100
540
675
735
µA
G 0 and G 1 inputs
held at VCC – 2.1
V
4.5 to
5.5
100
450
562.5
612.5
µA
G2 input held at
VCC – 2.1 V
4.5 to
5.5
100
360
450
490
µA
∆ICC
(1)
Additional supply
current per input
pin
VI = VIH or VIL, unless otherwise noted.
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(2)
5.5 Switching Characteristics
Input tt = 6ns. (See Parameter Measurement Information)
PARAMETER
TEST CONDITIONS
VCC (V)
25°C
MIN
TYP
-40°C to 85°C
MAX
MIN
MAX
-55°C to 125°C
MIN
MAX
UNIT
HC TYPES
Address to output
CL = 50pF
tpd
Strobe G 0, G 1, G2 to
output HC/HCT 138
tt
CL = 50pF
Output transition time
Cpd
Power dissipation
(1)
capacitance
Ci
Input capacitance
CL = 50pF
CL = 50pF
CL = 15pF
2
4.5
13
(3)
150
190
225
30
38
45
6
26
33
38
2
150
190
265
4.5
30
38
53
6
26
33
45
110
ns
ns
2
75
95
4.5
15
19
22 MHz
6
13
16
19
5
67
pF
10
10
10
pF
35
44
53
ns
HCT TYPES
CL = 50pF
4.5
Strobe G2 to output HC/
HCT138
CL = 50pF
4.5
35
44
53
ns
Strobe G 0, G 1 to output
HC/HCT238
CL = 15pF
4.5
40
50
60
ns
tt
Output transition time
CL= 15pF
4.5
15
19
22
Cpd
Power dissipation
(1)
capacitance
CL = 15pF
5
Ci
Input capacitance
tpd
(1)
(2)
(3)
6
14
(3)
Address to output
67
pF
10
10
10
pF
CPD is used to determine the dynamic power consumption, per gate.
For details on power calculation, see SCAA035B
CL = 15pF and VCC = 5
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SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
VCC
Input
50%
90%
tPLH
tPHL
tr(1)
(1)
VOH
Output
50%
10%
10%
tr(1)
tPLH(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
VOH
50%
VOH
90%
Output
VOL
Output
0V
tf(1)
90%
50%
tPHL(1)
10%
10%
0V
(1)
VCC
90%
Input
50%
Figure 6-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
3V
Input
1.3V
1.3V
0V
tPLH
(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
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7 Detailed Description
7.1 Overview
The CDx4HC(T)138 and '238 are high speed silicon gate CMOS decoders well suited to memory address
decoding or data routing applications. They contain a single 3:8 decoder.
The CDx4HC(T)138 and '238 have three address select inputs (A2, A1, and A0). The circuit functions as a normal
one-of-eight decoder.
Three strobe inputs (G2, G 1 and G 0) are provided to simplify cascading and to facilitate demultiplexing. When
any input strobe is active, all outputs are forced into the high state for the '138 function. When any input strobe is
active, all outputs are forced into the low state for the '238 function.
The demultiplexing function is accomplished by first using the select inputs to choose the desired output, and
then using one of the strobe inputs as the data input.
The outputs for the CDx4HC(T)138 are normally low when selected. The outputs for the CDxHC(T)238 are
normally high when selected.
7.2 Functional Block Diagram
3:8 DECODER
OUTPUT
ENABLE
000
Y0
A0
001
Y1
A1
010
Y2
A2
011
Y3
G0
100
Y4
G1
101
Y5
G2
110
Y6
111
Y7
Figure 7-1. Functional Block Diagram '138
8
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SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
3:8 DECODER
OUTPUT
ENABLE
000
Y0
A0
001
Y1
A1
010
Y2
A2
011
Y3
G0
100
Y4
G1
101
Y5
G2
110
Y6
111
Y7
Figure 7-2. Functional Block Diagram '238
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7.3 Device Functional Modes
Table 7-1. Function Table 'HC138, 'HCT138
INPUTS
STROBE
OUTPUTS
ADDRESS
G2
G1
G0
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
Table 7-2. Function Table 'HC238, 'HCT238
INPUTS
STROBE
OUTPUTS
ADDRESS
G2
G1
G0
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
X
X
X
L
L
L
L
L
L
L
L
L
X
X
X
X
X
L
L
L
L
L
L
L
L
X
H
X
X
X
X
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
L
H
L
L
L
H
L
L
H
L
H
L
L
L
L
L
H
L
L
H
L
L
H
H
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
10
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: CD54HC138 CD74HC138 CD54HCT138 CD74HCT138 CD54HC238 CD74HC238
CD54HCT238 CD74HCT238
11
CD54HC138, CD74HC138, CD54HCT138, CD74HCT138, CD54HC238, CD74HC238, CD54HCT238,
CD74HCT238
SCHS147J – NOVEMBER 1998 – REVISED NOVEMBER 2021
www.ti.com
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: CD54HC138 CD74HC138 CD54HCT138 CD74HCT138 CD54HC238 CD74HC238
CD54HCT238 CD74HCT238
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8688401EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8688401EA
CD54HC238F3A
Samples
CD54HC138F
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC138F
Samples
CD54HC138F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8406201EA
CD54HC138F3A
Samples
CD54HC238F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8688401EA
CD54HC238F3A
Samples
CD54HCT138F
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HCT138F
Samples
CD54HCT138F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8550401EA
CD54HCT138F3A
Samples
CD54HCT238F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8974501EA
CD54HCT238F3A
Samples
CD74HC138E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC138E
Samples
CD74HC138M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC138M
Samples
CD74HC138M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC138M
Samples
CD74HC138M96E4
ACTIVE
SOIC
D
16
2500
TBD
Call TI
Call TI
-55 to 125
CD74HC138ME4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC138M
Samples
CD74HC138MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC138M
Samples
CD74HC238E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC238E
Samples
CD74HC238EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC238E
Samples
CD74HC238M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC238M
Samples
CD74HC238M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC238M
Samples
CD74HC238M96E4
ACTIVE
SOIC
D
16
2500
TBD
Call TI
Call TI
-55 to 125
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Nov-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD74HC238MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC238M
Samples
CD74HC238NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC238M
Samples
CD74HC238PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ238
Samples
CD74HC238PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HJ238
Samples
CD74HC238PWRE4
ACTIVE
TSSOP
PW
16
2000
TBD
Call TI
Call TI
-55 to 125
Samples
CD74HC238PWRG4
ACTIVE
TSSOP
PW
16
2000
TBD
Call TI
Call TI
-55 to 125
Samples
CD74HC238PWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ238
Samples
CD74HCT138E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT138E
Samples
CD74HCT138M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT138M
Samples
CD74HCT138M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HCT138M
Samples
CD74HCT238E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT238E
Samples
CD74HCT238M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT238M
Samples
CD74HCT238M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HCT238M
Samples
CD74HCT238M96G4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT238M
Samples
CD74HCT238PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HK238
Samples
CD74HCT238PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HK238
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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