CD74HC244M

CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 CDx4HC240, CDx4HCT240, CD74HC241, CDx4HCT241, CDx4HC244, CDx4HCT244 High-Speed CMOS Logic Octal Buffer/Line Drivers, Three-State 1 Features 2 Description • • • • The ’HC240 and ’HCT240 are inverting three-state buffers having two active-low output enables. The CD74HC241, ’HCT241, ’HC244 and ’HCT244 are non-inverting three-state buffers that differ only in that the 241 has one active-high and one active-low output enable, and the 244 has two active-low output enables. All three types have identical pinouts. • • • • • • • • • HC/HCT240 Inverting HC/HCT241 Non-inverting HC/HCT244 Non-inverting Typical propagation delay = 8ns at VCC = 5 V, CL = 15 pF, TA = 25℃ for HC240 Three-state outputs Buffered inputs High-current bus driver outputs Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads Wide operating temperature range: –55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC types: – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types: – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min) – CMOS input compatibility, II ≤ 1μA at VOL, VOH Package Information PART NUMBER CD74HC240 CD54HC240 CD74HCT240 CD54HCT240 CD74HC241 CD74HCT241 CD54HCT241 CD74HC244 CD54HC244 CD74HCT244 CD54HCT244 (1) (1) PACKAGE BODY SIZE (NOM) M (SOIC, 20) 12.80 mm × 7.50 mm E (PDIP, 20) 25.40 mm × 6.35 mm F (CDIP, 20) 26.92 mm × 6.92 mm M (SOIC, 20) 12.80 mm × 7.50 mm E (PDIP, 20) 25.40 mm × 6.35 mm PW (TSSOP, 20) 6.50 mm × 4.40 mm F (CDIP, 20) 26.92 mm × 6.92 mm M (SOIC, 20) 12.80 mm × 7.50 mm E (PDIP, 20) 25.40 mm × 6.35 mm M (SOIC, 20) 12.80 mm × 7.50 mm E (PDIP, 20) 25.40 mm × 6.35 mm F (CDIP, 20) 26.92 mm × 6.92 mm M (SOIC, 20) 12.80 mm × 7.50 mm E (PDIP, 20) 25.40 mm × 6.35 mm F (CDIP, 20) 26.92 mm × 6.92 mm M (SOIC, 20) 12.80 mm × 7.50 mm E (PDIP, 20) 25.40 mm × 6.35 mm F (CDIP, 20) 26.92 mm × 6.92 mm For all available packages, see the orderable addendum at the end of the data sheet. Pinout Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings(1) .................................... 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics '240..................................... 5 5.5 Electrical Characteristics '241..................................... 6 5.6 Electrical Characteristics '244..................................... 7 5.7 Switching Characteristics '240.................................... 8 5.8 Switching Characteristics '241.................................... 8 5.9 Switching Characteristics '244.................................... 9 6 Parameter Measurement Information.......................... 11 7 Detailed Description......................................................13 7.1 Overview................................................................... 13 7.2 Functional Block Diagram......................................... 13 8 Power Supply Recommendations................................15 9 Layout.............................................................................15 9.1 Layout Guidelines..................................................... 15 10 Device and Documentation Support..........................16 10.1 Receiving Notification of Documentation Updates..16 10.2 Support Resources................................................. 16 10.3 Trademarks............................................................. 16 10.4 Electrostatic Discharge Caution..............................16 10.5 Glossary..................................................................16 11 Mechanical, Packaging, and Orderable Information.................................................................... 16 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2004) to Revision F (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 Changes from Revision F (February 2022) to Revision G (October 2022) Page • Increased RθJA for packages: DW (73 to 109.1); DB (82 to 122.7); N (67 to 84.6); NS (64 to 113.4); PW (108 to 131.8)..............................................................................................................................................................4 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 4 Pin Configuration and Functions J, N, DW, or PW package 20-Pin CDIP, PDIP, SOIC, or TSSOP Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 3 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5 Specifications 5.1 Absolute Maximum Ratings(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input clamp diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output clamp diode current For VO < –0.5 V or VO >VCC + 0.5 V ±20 mA IO Drain current, per output For –0.5 V < VO < VCC + 0.5 V ±35 mA IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA ICC Continuous current through VCC or GND ±70 mA TJ Junction temperature 150 ℃ Tstg Storage temperature range 150 ℃ 300 ℃ –65 Lead temperature (Soldering 10s) (SOIC - lead tips only) (1) V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions VCC Supply voltage range VI, VO Input or output voltage tt Input rise and fall time TA Temperature range HC types HCT types MIN MAX 2 6 4.5 5.5 0 VCC 2V UNIT V V 1000 4.5 V 500 6V ns 400 –55 125 ℃ 5.3 Thermal Information THERMAL METRIC DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS UNIT 109.1 122.7 84.6 113.4 131.8 °C/W 76 81.6 72.5 78.6 72.2 °C/W RθJA Junction-to-ambient thermal (1) resistance RθJC (top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 77.6 77.5 65.3 78.4 82.8 °C/W ΨJT Junction-to-top characterization parameter 51.5 46.1 55.3 47.1 21.5 °C/W ΨJB Junction-to-board characterization parameter 77.1 77.1 65.2 78.1 82.4 °C/W RθJC (bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W (1) 4 DW (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5.4 Electrical Characteristics '240 PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 IOH = – 6 mA 4.5 3.98 3.84 3.7 IOH = – 7.8 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 5.34 V V 5.2 IOL = 6 mA 4.5 0.26 0.33 0.4 IOL = 7.8 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA IOZ Three-state leakage current 6 ±0.5 ±0.5 ±10 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 2 0.8 2 0.8 V 0.8 High level output voltage VOH = – 20 μA High level output voltage VOH = – 6 mA 4.5 Low level output voltage VOL = 20 μA 4.5 0.1 0.1 0.1 Low level output voltage VOL = 6 mA 4.5 0.26 0.33 0.4 4.5 4.4 4.4 V 4.4 V 3.98 3.84 3.7 V II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 5.5 8 80 160 μA IOZ Three-state leakage current 5.5 ±0.5 ±5 ±10 μA ΔICC (1) (1) (2) Additional supply current per input pin nA0 - A3 inputs held at VCC – 2.1 4.5 to 5.5 100 540 675 735 μA 1OE inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA 2OE inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL, unless otherwise noted. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 5 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5.5 Electrical Characteristics '241 TEST CONDITIONS(2) PARAMETER VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 IOH = – 6 mA 4.5 3.98 3.84 3.7 IOH = – 7.8 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 5.34 V V 5.2 IOL = 6 mA 4.5 0.26 0.33 0.4 IOL = 7.8 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA IOZ Three-state leakage current 6 ±0.5 ±0.5 ±10 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 0.8 2 0.8 V 0.8 High level output voltage VOH = – 20 μA High level output voltage VOH = – 6 mA 4.5 Low level output voltage VOL = 20 μA 4.5 0.1 0.1 0.1 Low level output voltage VOL = 6 mA 4.5 0.26 0.33 0.4 4.5 4.4 4.4 V 4.4 V 3.98 3.84 3.7 V II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 5.5 8 80 160 μA IOZ Three-state leakage current 5.5 ±0.5 ±5 ±10 μA ΔICC (1) (1) (2) 6 2 Additional supply current per input pin nA0 - A3 inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA 1OE inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA 2OE inputs held at VCC – 2.1 4.5 to 5.5 100 540 675 735 μA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL, unless otherwise noted. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5.6 Electrical Characteristics '244 PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 IOH = – 6 mA 4.5 3.98 3.84 3.7 IOH = – 7.8 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 5.34 V V 5.2 IOL = 6 mA 4.5 0.26 0.33 0.4 IOL = 7.8 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA IOZ Three-state leakage current 6 ±0.5 ±0.5 ±10 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 2 0.8 2 0.8 V 0.8 High level output voltage VOH = – 20 μA High level output voltage VOH = – 6 mA 4.5 Low level output voltage VOL = 20 μA 4.5 0.1 0.1 0.1 Low level output voltage VOL = 6 mA 4.5 0.26 0.33 0.4 4.5 4.4 4.4 V 4.4 V 3.98 3.84 3.7 V II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 5.5 8 80 160 μA IOZ Three-state leakage current 5.5 ±0.5 ±5 ±10 μA ΔICC (1) (1) (2) Additional supply current per input pin nA0 - A3 inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA 1OE inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA 2OE inputs held at VCC – 2.1 4.5 to 5.5 100 252 315 343 μA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL, unless otherwise noted. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 7 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5.7 Switching Characteristics '240 CL = 50 pF, Input tr, tf = 6 ns PARAMETER VCC (V) Propagation delay Data to outputs 4.5 25℃ MIN –40℃ to 85℃ TYP MAX MIN TYP –55℃ to 125℃ MAX MIN TYP MAX UNIT HC TYPES tPLH, tPHL tTHL, tTLH Output enable and disable time tTLH, tTHL Output transition time CI Input capacitance CO Three-state output capacitance CPD Power dissipation capacitance(1) (2) 2 8 (3) 100 125 150 20 25 30 ns 6 17 21 26 2 150 190 225 30 38 45 6 26 33 38 2 60 75 90 4.5 12 15 18 10 13 15 10 10 10 pF 20 20 20 pF 4.5 5 12 6 10 5 38 (3) 9 (3) ns ns pF HCT TYPES tPHL, tPLH Data to outputs 4.5 tTLH, tTHL Output enable and disable times tTHL, tTLH Output transition time CI Input capacitance CPD Power dissipation capacitance(1) (2) (1) (2) (3) 8 22 28 33 ns 4.5 30 38 45 ns 4.5 12 15 18 ns 10 10 10 pF 10 5 40 pF CPD is used to determine the dynamic power consumption, per channel. PD = VCC 2fi (CPD + CL) where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5.8 Switching Characteristics '241 CL = 50 pF, Input tr, tf = 6 ns PARAMETER VCC (V) 25℃ MIN –40℃ to 85℃ TYP MAX MIN TYP –55℃ to 125℃ MAX MIN TYP MAX UNIT HC TYPES 2 tPLH, tPHL tTHL, tTLH Propagation delay Data to outputs Output enable and disable time tTLH, tTHL Output transition time CI Input capacitance CO Three-state output capacitance CPD Power dissipation capacitance(1) (2) 4.5 9 (3) 110 140 165 22 28 33 6 19 24 28 2 150 190 225 4.5 30 38 45 6 26 33 38 2 60 75 90 4.5 12 15 18 10 13 15 10 10 10 pF 20 20 20 pF 5 12 6 10 5 34 (3) 10 (3) ns ns ns pF HCT TYPES tPHL, tPLH Data to outputs 4.5 tTLH, tTHL Output enable and disable times tTHL, tTLH Output transition time CI Input capacitance CPD Power dissipation capacitance(1) (2) (1) (2) (3) 25 31 38 ns 4.5 30 38 45 ns 4.5 12 15 18 ns 10 10 10 pF 10 5 38 pF CPD is used to determine the dynamic power consumption, per channel. PD = VCC 2fi (CPD + CL) where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 9 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 5.9 Switching Characteristics '244 CL = 50 pF, Input tr, tf = 6 ns PARAMETER VCC (V) 25℃ MIN –40℃ to 85℃ TYP MAX MIN TYP –55℃ to 125℃ MAX MIN TYP MAX UNIT HC TYPES 2 tPLH, tPHL tTHL, tTLH Propagation delay Data to outputs Output enable and disable time tTLH, tTHL Output transition time CI Input capacitance CO Three-state output capacitance CPD Power dissipation capacitance(1) (2) 4.5 9 (3) 110 140 165 22 28 33 6 19 24 28 2 150 190 225 4.5 30 38 45 6 26 33 38 2 60 75 90 4.5 12 15 18 10 13 15 10 10 10 pF 20 20 20 pF 5 12 6 10 5 46 (3) 10 (3) ns ns ns pF HCT TYPES tPHL, tPLH Data to outputs 4.5 tTLH, tTHL Output enable and disable times tTHL, tTLH Output transition time CI Input capacitance CPD Power dissipation capacitance(1) (2) (1) (2) (3) 10 25 31 38 ns 4.5 30 38 45 ns 4.5 12 15 18 ns 10 10 10 pF 10 5 40 pF CPD is used to determine the dynamic power consumption, per channel. PD = VCC 2fi (CPD + CL) where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. VCC Test Point S1 RL From Output Under Test CL(1) S2 (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for 3-State Outputs VCC Input 50% VCC Output Control 50% 50% 50% 0V 0V tPHL(1) tPLH(1) tPZL(3) VOH Output 50% VOL tPHL (1) tPLH 50% 50% 10% VOL (1) tPZH VOH Output § 9CC Output Waveform 1 S1 at VLOAD(1) 50% Output Waveform 2 S1 at GND(2) 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. tPLZ(4) (3) tPHZ (4) 90% VOH 50% §0V (1) S1 = CLOSED; S2 = OPEN. (2) S1 = OPEN; s2 = CLOSED. (3) tPLZ and tPHZ are the same as tdis. (4) tPZL and tPZH are the same as ten. Figure 6-2. Voltage Waveforms, Propagation Delays for Standard CMOS Inputs Figure 6-3. Voltage Waveforms, Standard CMOS Inputs Propagation Delays 90% VCC 90% Input 10% 10% tr(1) 0V tf(1) 90% VOH 90% Output 10% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 6-4. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 11 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 3V Input 1.3V 1.3V 3V Input 1.3V 1.3V 0V tPLH(1) VOH Output Waveform 1 50% 50% VOL 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-5. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs 12 Submit Document Feedback Output Waveform 2 S1 OPEN, S2 CLOSED tPLZ(2)
VCC 50% 10% VOL tPZH(1) VOH 50% Output Waveform 1 S1 CLOSED, S2 OPEN tPLH(1) tPHL(1) Output Waveform 2 0V tPZL(1) tPHL(1) tPHZ(2) 90% VOH 50% 0V (1) tPLZ and tPHZ are the same as tdis. (2) tPZL and tPZH are the same as ten. Figure 6-6. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 7 Detailed Description 7.1 Overview The ’HC240 and ’HCT240 are inverting three-state buffers having two active-low output enables. The CD74HC241, ’HCT241, ’HC244 and ’HCT244 are non-inverting threestate buffers that differ only in that the 241 has one activehigh and one active-low output enable, and the 244 has two active-low output enables. All three types have identical pinouts. 7.2 Functional Block Diagram xOE xA1 xY1 xA2 xY2 xA3 xY3 xA4 xY4 Figure 7-1. Functional Block Diagram '240 1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2OE 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 Figure 7-2. Functional Block Diagram '241 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 13 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 Figure 7-3. Functional Block Diagram '244 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 15 CD54HC240, CD74HC240, CD74HC241, CD54HC244 CD74HC244, CD54HCT240, CD74HCT240, CD54HCT241 CD74HCT241, CD54HCT244, CD74HCT244 www.ti.com SCHS167G – NOVEMBER 1998 – REVISED OCTOBER 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC240 CD74HC240 CD74HC241 CD54HC244 CD74HC244 CD54HCT240 CD74HCT240 CD54HCT241 CD74HCT241 CD54HCT244 CD74HCT244 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD54HC240F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407401RA CD54HC240F3A Samples CD54HC244F ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC244F Samples CD54HC244F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8409601RA CD54HC244F3A Samples CD54HCT240F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8550501RA CD54HCT240F3A Samples CD54HCT241F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT241F3A Samples CD54HCT244F ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT244F Samples CD54HCT244F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8513001RA CD54HCT244F3A Samples CD74HC240E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC240E Samples CD74HC240M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC240M Samples CD74HC240M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC240M Samples CD74HC241E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC241E Samples CD74HC241M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC241M Samples CD74HC241M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC241M Samples CD74HC244E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC244E Samples CD74HC244EE4 ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC244E Samples CD74HC244M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M Samples CD74HC244M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M Samples CD74HC244M96E4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD74HC244M96G4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC244M Samples CD74HCT240E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT240E Samples CD74HCT240EE4 ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT240E Samples CD74HCT240M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT240M Samples CD74HCT240M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT240M Samples CD74HCT240PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK240 Samples CD74HCT240PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK240 Samples CD74HCT240PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK240 Samples CD74HCT241E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT241E Samples CD74HCT241M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT241M Samples CD74HCT241M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT241M Samples CD74HCT244E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT244E Samples CD74HCT244M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT244M Samples CD74HCT244M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT244M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of