CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
CDx4HC(T)259 High-Speed SMOS Logic 8-Bit Addressable Latch
1 Features
2 Description
•
•
•
The CDx4HC(T)259 is an 8-bit addressable latch with
three active modes of operation (addressable latch,
memory, 8-line demultiplexer) and one reset mode.
•
•
•
•
•
•
Buffered inputs and outputs
Four operating modes
Typical propagation delay of 15ns at VCC = 5V, CL
= 15pF, TA = 25oC
Fanout (over temperature range)
– Standard Outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: -55oC to 125oC
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatability, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1µA at VOL, VOH
3:8 DECODER
Device Information
PACKAGE
BODY SIZE (NOM)
CD54HC259F3A
CDIP (16)
21.34 mm × 6.92 mm
CD54HCT259F3A
CDIP (16)
21.34 mm × 6.92 mm
CD74HC259E
PDIP (16)
19.31 mm × 6.35 mm
CD74HCT259E
PDIP (16)
19.31 mm × 6.35 mm
CD74HC259M
SOIC (16)
9.90 mm × 3.90 mm
CD74HCT259M
SOIC (16)
9.90 mm × 3.90 mm
(1)
For all packages see the orderable addendum at the end of
the data sheet.
LATCH
ENABLE
000
S0
001
S1
010
011
S2
100
101
G
D
(1)
PART NUMBER
110
111
OUTPUT STORAGE
D
LE
R
Q
Q0
D
LE
R
Q
Q1
D
LE
R
Q
Q2
D
LE
R
Q
Q3
D
LE
R
Q
Q4
D
LE
R
Q
Q5
D
LE
R
Q
Q6
D
LE
R
Q
Q7
CLR
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
www.ti.com
SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics.................. 6
(2)
5.6 Switching Characteristics ........................................ 7
6 Parameter Measurement Information............................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Device Functional Modes..........................................11
8 Power Supply Recommendations................................12
9 Layout.............................................................................12
9.1 Layout Guidelines..................................................... 12
10 Device and Documentation Support..........................13
10.1 Documentation Support.......................................... 13
10.2 Receiving Notification of Documentation Updates..13
10.3 Support Resources................................................. 13
10.4 Trademarks............................................................. 13
10.5 Electrostatic Discharge Caution..............................13
10.6 Glossary..................................................................13
11 Mechanical, Packaging, and Orderable
Information.................................................................... 13
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2003) to Revision D (November 2021)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern datasheet standards.............................................................................................................................. 1
• Updated pin names to match current TI naming conventions. A0 is now S0, A1 is now S1, A2 is now S2.......... 3
2
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
4 Pin Configuration and Functions
S0
1
16
VCC
S1
2
CLR
S2
3
15
14
Q0
4
13
D
Q1
5
12
Q7
Q2
6
11
Q6
Q3
GND
7
8
10
Q5
Q4
9
G
J, D or PW Package
16-Pin CDIP, SOIC or TSSOP
Top View
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
5 Specifications
5.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
-0.5
7
UNIT
VCC
Supply voltage
IIK
Input clamp diode current
±20
mA
IOK
Output clamp diode current For VO < -0.5V or VO > VCC + 0.5V
±20
mA
IO
Drain current, per output
For -0.5V < VO < VCC + 0.5V
±25
mA
IO
Output source or sink
current per output pin
For VO > -0.5V or VO < VCC + 0.5V
±25
mA
For VI < -0.5V or VI > VCC + 0.5V
V
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
300
°C
-65
Lead temperature (Soldering 10s) (SOIC - lead tips only)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions
VCC
Supply voltage range
VI
Input voltage
VO
Output voltage
HC Types
HCT Types
MIN
MAX
2
6
4.5
5.5
0
VCC
V
VCC
V
0
VCC = 2V
tt
TA
Input rise and fall time
UNIT
V
1000
VCC = 4.5V
500
VCC = 6V
400
Temperature range
-55
125
ns
°C
5.3 Thermal Information
CD74HC259, CD74HCT259
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
N (PDIP)
D (SOIC)
16 PINS
16 PINS
UNIT
67
73
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
5.4 Electrical Characteristics
TEST
CONDITIONS
PARAMETER
VCC (V)
25°C
MIN
TYP
-40°C to 85°C
MAX
MIN
MAX
-55°C to 125°C
MIN
MAX
UNIT
HC TYPES
VIH
High-level input voltage
VIL
Low-level input voltage
High-level output voltage
VOH
High-level output voltage
Low-level output voltage
VOL
Low-level output voltage
2
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
V
6
4.2
4.2
4.2
V
2
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
V
6
1.8
1.8
1.8
V
IOH = – 20 µA
2
1.9
1.9
1.9
V
IOH = – 20 µA
4.5
4.4
4.4
4.4
V
IOH = – 20 µA
6
5.9
5.9
5.9
V
IOH= – 4 mA
4.5
3.98
3.84
3.7
V
IOH = – 5.2 mA
6
5.48
IOL = 20 µA
2
0.1
0.1
0.1
V
IOL = 20 µA
4.5
0.1
0.1
0.1
V
IOL = 20 µA
6
0.1
0.1
0.1
V
IOL= 4 mA
5.34
5.2
V
4.5
0.26
0.33
0.4
V
IOL = 5.2 mA
6
0.26
0.33
0.4
V
II
Input leakage current
VI = VCC or GND
6
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or GND
6
8
80
160
µA
HCT TYPES
VIH
High-level input voltage
4.5 to
5.5
VIL
Low-level input voltage
4.5 to
5.5
2
2
0.8
2
0.8
V
0.8
V
High-level output voltage
VOH = – 20 µA
4.5
4.4
4.4
4.4
V
HIgh-level output voltage
VOH = – 4 mA
4.5
3.98
3.84
3.7
V
Low-level output voltage
VOL = 20 µA
4.5
0.1
0.1
0.1
V
Low-level output voltage
VOL = 4 mA
4.5
0.26
0.33
0.4
V
II
Input leakage current
VI = VCC or GND
5.5
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or GND
5.5
8
80
160
µA
One of A0 - A2
and LE inputs
held at VCC – 2.1
4.5 to
5.5
100
540
675
735
D input held at
VCC – 2.1
4.5 to
5.5
100
432
540
588
MR input held at
VCC – 2.1
4.5 to
5.5
100
270
337.5
367.5
VOH
VOL
∆ICC(1)
(1)
Additional supply current
per input pin
µA
VI = VIH or VIL, unless otherwise noted.
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
5.5 Prerequisite for Switching Characteristics
25°C
-40°C to 85°C
-55°C to 125°C
PARAMETER
VCC (V)
2
70
90
105
Pulse Width G
4.5
14
18
21
5
12
15
18
2
70
90
105
4.5
14
18
21
6
12
15
18
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
HC TYPES
tWL
tWL
CLR
ns
ns
2
80
100
120
4.5
16
20
24
6
14
17
20
Hold time
D to G
S to G
2
0
0
0
4.5
0
0
0
6
0
0
0
tWL
Pulse width
G
CLR
4.5
18
23
27
ns
tSU
Setup Time
D to G
S to G
4.5
17
21
26
ns
tH
Hold Time
D to G
S to G
4.5
0
0
0
pF
Setup time
D to G
S to G
tSU
tH
ns
ns
HCT TYPES
6
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
(2)
5.6 Switching Characteristics
CL = 50pF, Input tt = 6ns
PARAMETER
VCC (V)
25°C
MIN
-40°C to 85°C
TYP
MAX
MIN
MAX
-55°C to 125°C
MIN
MAX
UNIT
HC TYPES
2
4.5
D to Q
15
39
48
255
34
43
51
29
37
43
185
230
280
37
46
56
31
39
48
155
195
235
31
39
47
6
26
33
40
2
75
95
110
4.5
15
19
22
6
13
16
19
10
10
10
pF
14
15
(1)
(1)
2
4.5
Output transition time
Cpd
Power dissipation Capacitance
Ci
Input capacitance
(1)
ns
215
6
tt
56
31
4.5
CLR to Q
280
46
170
2
S to Q
230
37
2
6
tpd
185
6
4.5
G to Q
(1)
13
5
21
(1)
(1)
10
ns
ns
ns
ns
pF
HCT TYPES
D to Q
tpd
4.5
G to Q
4.5
S to Q
4.5
CLR to Q
4.5
Cpd
Power dissipaction Capacitance
Ci
Input Capacitance
tt
Output transition time
(1)
(2)
(1)
5
10
4.5
16
(1)
39
49
59
ns
16
(1)
38
48
57
ns
17
(1)
41
51
61
ns
16
(1)
39
49
59
pF
22
(1)
10
10
10
pF
15
19
22
ns
pF
CL = 15pF and VCC = 5 V.
For details on CMOS power calculation see, SCAA053B.
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
Figure 6-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
th
tsu
VCC
Data
Input
50%
50%
0V
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC
Input
50%
90%
Input
50%
tPLH
tPHL
tr(1)
(1)
VOH
Output
50%
VOL
tPHL
tPLH
(1)
VOH
Output
50%
0V
tf(1)
90%
VOH
90%
Output
50%
(1)
10%
10%
0V
(1)
VCC
90%
50%
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 6-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Input Devices
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Standard CMOS
Inputs Setup Propagation Delays
8
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
tw
3V
Clock
Input
3V
Input
1.3V
1.3V
1.3V
0V
0V
tsu
Figure 6-6. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
th
3V
Data
Input
1.3V
1.3V
0V
Figure 6-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input
1.3V
1.3V
0V
tPLH(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-8. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
7 Detailed Description
7.1 Overview
The CDx4HC(T)259 8-bit addressable latches are designed for general-purpose storage applications in
digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or
demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches
and being a 1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs:
•
•
•
•
Addressable-latch mode: CLR = HIGH; G = LOW
– Data at the data-in terminal is written into the addressed latch
– The addressed latch follows the data input, with all unaddressed latches remaining in their previous states
Memory mode: CLR = HIGH; G = HIGH
– All latches remain in their previous states and are unaffected by the data or address inputs
– To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while
the address lines are changing
1-of-8 decoding or demultiplexing mode: CLR = LOW; G = LOW
– The addressed output follows the level of the D input with all other outputs low
Clear mode: CLR = LOW; G = HIGH
– All outputs are low and unaffected by the address and data inputs
7.2 Functional Block Diagram
3:8 DECODER
000
S0
001
S1
010
011
S2
100
101
G
110
D
111
LATCH
ENABLE
OUTPUT STORAGE
D
LE
R
Q
Q0
D
LE
R
Q
Q1
D
LE
R
Q
Q2
D
LE
R
Q
Q3
D
LE
R
Q
Q4
D
LE
R
Q
Q5
D
LE
R
Q
Q6
D
LE
R
Q
Q7
CLR
10
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
7.3 Device Functional Modes
The Function Tableand Latch Selection Table below list the functional modes of the CDx4HC(T)259.
Table 7-1. Function Table
INPUTS(1)
CLR
(1)
(2)
OUTPUT OF
EACH OTHER
ADDRESSED
FUNCTION
OUTPUT(2)
(2)
LATCH
G
H
L
D
QiO
Addressable
latch
H
H
QiO
QiO
Memory
L
L
D
L
8-line
demultiplexer
L
H
L
L
Clear
H = High voltage level, L = Low voltage level
QiO = Previous output state of selected latch, D = Data input
logic value
Table 7-2. Latch Selection Table
SELECT INPUTS(1)
S2
(1)
S1
LATCH
ADDRESSED
S0
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
H = High Voltage Level, L = Low Voltage Level
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
12
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SCHS173D – NOVEMBER 1997 – REVISED NOVEMBER 2021
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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18-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
5962-8985201EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8985201EA
CD54HCT259F3A
CD54HC259F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8551901EA
CD54HC259F3A
CD54HCT259F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8985201EA
CD54HCT259F3A
CD74HC259E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC259E
CD74HC259M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC259M
CD74HC259M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC259M
CD74HC259MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC259M
CD74HCT259E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT259E
CD74HCT259EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT259E
CD74HCT259M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT259M
CD74HCT259M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT259M
CD74HCT259M96E4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT259M
CD74HCT259MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT259M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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