CD74HC393E

CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 CDx4HC393, CDx4HCT393 High-Speed CMOS Logic Dual 4-Stage Binary Counter 1 Features 2 Description • • • • • The ’HC393 and ’HCT393 are 4-stage ripple-carry binary counters. All counter stages are primaryoperative flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. • • • • • Fully static operation Buffered inputs Common reset Negative-edge clocking Fanout (over temperature range): – Standard outputs 10 LSTTL loads – Bus driver outputs 15 LSTTL loads Wide operating temperature range: –55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min) – CMOS input compatibility, II ≤ 1 µA at VOL, VOH CP Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC393M SOIC (14) 8.65 mm × 3.90 mm CD74HC393E PDIP (14) 19.31 mm × 6.35 mm CD74HCT393M SOIC (14) 8.65 mm × 3.90 mm CD74HCT393E PDIP (14) 19.31 mm × 6.35 mm CD54HC393F3A CDIP (14) 19.55 mm × 6.71 mm CD54HCT393F CDIP (14) 19.55 mm × 6.71 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Φ Q Φ R Q MR QX Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings(1) .................................... 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information ...................................................4 5.4 Electrical Characteristics.............................................5 5.5 Prerequisite for Switching Characteristics.................. 6 5.6 Switching Characteristics............................................6 6 Parameter Measurement Information............................ 8 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Device Functional Modes............................................9 8 Power Supply Recommendations................................11 9 Layout............................................................................. 11 9.1 Layout Guidelines..................................................... 11 10 Device and Documentation Support..........................12 10.1 Receiving Notification of Documentation Updates..12 10.2 Support Resources................................................. 12 10.3 Trademarks............................................................. 12 10.4 Electrostatic Discharge Caution..............................12 10.5 Glossary..................................................................12 11 Mechanical, Packaging, and Orderable Information.................................................................... 12 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2003) to Revision F (March 2022) Page • Updated the numbering, formatting, tables, figures, and cross-refrences throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 4 Pin Configuration and Functions J, N, or D package 14-PIN CDIP, PDIP, or SOIC Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 3 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 5 Specifications 5.1 Absolute Maximum Ratings(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Output source or sink current per output pin For VO> –0.5 V or VO < VCC + 0.5 V ±25 mA ±50 mA 150 °C 150 °C 300 °C Continous current through VCC or GND TJ Junction temperature Tstg Storage temperature range – 65 Lead temperature (Soldering 10s) (SOIC - lead tips only) (1) V Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 5.2 Recommended Operating Conditions MIN VCC Supply voltage range VI, VO DC input or output voltage HC types HCT types MAX 2 6 4.5 5.5 0 VCC 2V Input rise and fall time V V 1000 4.5 V 500 6V TA UNIT ns 400 Temperature range –55 125 ℃ 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) D (SOIC) N (PDIP) 14 PINS 14 PINS UNIT 86 80 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 5.4 Electrical Characteristics TEST CONDITIONS(2) PARAMETER VCC (V) 25℃ MIN TYP -40℃ to 85℃ MAX MIN MAX -55℃ to 125℃ MIN MAX UNIT HC TYPES High level input voltage VIH VIL Low level input voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 V High level output voltage CMOS loads IOH = – 20 μA 2 1.9 1.9 1.9 IOH = – 20 μA 4.5 4.4 4.4 4.4 IOH = – 20 μA 6 5.9 5.9 5.9 High level output voltage TTL loads IOH – 4 mA 4.5 3.98 3.84 3.7 IOH – 5.2 mA 6 5.48 5.34 5.2 Low level output voltage CMOS loads IOL = 20 μA 2 0.1 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 Low level output voltage TTL loads IOL = 4 mA 4.5 0.26 0.33 0.4 IOL = 5.2 mA 6 0.26 0.33 0.4 II Input leakage current VCC or GND 6 ±0.1 ±1 ±1 µA ICC Supply current VCC or GND 6 8 80 160 µA VOH VOL V V V V HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 0.8 2 0.8 V 0.8 V IOH = – 20 μA 4.5 4.4 4.4 4.4 V High level output voltage TTL loads IOH = – 4 mA 4.5 3.98 3.84 3.7 V Low level output voltage CMOS loads IOL = 20 μA 4.5 0.1 0.1 0.1 V Low level output voltage TTL loads IOL = 4 mA 4.5 0.26 0.33 0.4 V VCC and GND 5.5 ±0.1 ±1 ±1 µA 8 80 160 µA Input leakage current ICC Supply current (1) (2) 2 High level output voltage CMOS loads II ΔICC (1) 2 Additional supply current per input pin VCC or GND 5.5 nCP input held at VCC -2.1 4.5 to 5.5 100 144 180 196 µA nMR input held at VCC – 2.1 4.5 to 5.5 100 360 450 490 µA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL, unless otherwise noted. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 5 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 5.5 Prerequisite for Switching Characteristics PARAMETER VCC (V) 25℃ MIN -40℃ to 85℃ TYP MAX MIN -55℃ to 125℃ MAX MIN MAX UNIT HC TYPES fMAX tW tREC tW Maximum clock frequency Clock pulse width Reset recovery time Reset pulse width 2 6 5 4 4.5 30 24 20 6 35 28 24 2 80 100 120 4.5 16 20 24 6 14 17 20 2 5 5 5 4.5 5 5 5 6 5 5 5 2 80 100 120 4.5 16 20 24 6 14 17 20 MHz ns ns ns HCT TYPES fMAX Maximum clock frequency 4.5 27 22 18 MHz tW Clock pulse width 4.5 19 24 29 ns tREC Reset recovery time 4.5 5 5 5 ns tW Reset pulse width 4.5 16 20 24 ns 5.6 Switching Characteristics Input tr, tf = 6 ns. See (Parameter Measurement Information) TEST V (V) CONDITIONS CC PARAMETER 25℃ MIN TYP -40℃ to 85℃ MAX MIN MAX -55℃ to 125℃ MIN MAX UNIT HC TYPES tPLH, tPHL tPLH, tPHL nCP to nQ1 tPLH, tPHL nCP to nQ2 tPLH, tPHL tPLH, tPHL 6 Propagation delay time nCP to nQ0 CL = 50 pF 225 4.5 30 38 59 CL = 50 pF 6 26 33 50 2 190 245 295 4.5 38 49 59 6 33 42 50 2 240 300 360 4.5 48 60 72 CL = 50 pF CL = 50 pF Submit Document Feedback 190 5 CL = 50 pF MR to Qn 150 CL = 15 pF CL = 50 pF nCP to nQ3 2 12 ns 6 41 51 61 2 285 355 430 4.5 57 71 86 6 48 60 73 2 135 170 205 4.5 27 34 41 23 29 35 CL = 15 pF 5 CL = 50 pF 6 ns 11 ns ns ns ns ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 5.6 Switching Characteristics (continued) Input tr, tf = 6 ns. See (Parameter Measurement Information) TEST V (V) CONDITIONS CC PARAMETER tTLH, tTHL Output transition time CL = 50 pF CIN Input capacitance CL = 50 pF CPD Power dissipation capacitance(1) (2) 25℃ MIN TYP -40℃ to 85℃ MAX MIN MAX -55℃ to 125℃ MIN MAX 2 75 95 110 4.5 15 19 22 6 13 16 19 10 10 10 CL = 15 pF 5 20 UNIT ns pF pF HCT TYPES tPLH, tPHL Propagation delay time nCP to nQ0 CL = 50 pF 4.5 CL = 15 pF 5 tPLH, tPHL nCP to nQ1 CL = 50 pF 4.5 44 55 66 ns tPLH, tPHL nCP to nQ2 CL = 50 pF 4.5 50 63 75 ns tPLH, tPHL nCP to nQ3 CL = 50 pF 4.5 62 78 93 ns tPLH, tPHL MR to Qn CL = 50 pF 4.5 32 40 48 ns CL = 15 pF 5 tTLH, tTHL Output transition CL = 50 pF 4.5 CIN Input capacitance CPD (1) (2) Power dissipation 32 CL = 15 pF 5 48 ns ns 13 CL = 15 pF capacitance(1) (2) 40 13 ns 15 19 22 ns 10 10 10 pF 21 pF CPD is used to determine the dynamic power consumption, per stage. PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 7 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. Test Point From Output Under Test CL(1) (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs VCC Input 50% 90% tPLH tPHL tr(1) (1) VOH Output 50% 10% 10% tr(1) tPLH(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. VOH 50% VOH 90% Output VOL Output 0V tf(1) 90% 50% tPHL(1) 10% 10% 0V (1) VCC 90% Input 50% Figure 6-3. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-2. Voltage Waveforms, Propagation Delays for Standard CMOS Inputs 3V Input 1.3V 1.3V 0V tPLH (1) tPHL(1) VOH Output Waveform 1 50% 50% VOL tPHL(1) tPLH(1) VOH Output Waveform 2 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 7 Detailed Description 7.1 Overview The ’HC393 and ’HCT393 are 4-stage ripple-carry binary counters. All counter stages are controller flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. 7.2 Functional Block Diagram Φ CP Q Φ R Q MR QX Figure 7-1. Functional Diagram 7.3 Device Functional Modes Table 7-1. Truth Table(1) CP COUNT (1) OUTPUTS Q0 Q1 Q2 Q3 0 L L L L 1 H L L L 2 L H L L 3 H H L L 4 L L H L 5 H L H L 6 L H H L 7 H H H L 8 L L L H 9 H L L H 10 L H L H 11 H H L H 12 L L H H 13 H L H H 14 L H H H 15 H H H H H = high voltage level, L = low voltage level, X = don’t care, ↑ = transition from low to high level, ↓ = transition from high to low. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 9 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 Table 7-2. Truth Table(1) (1) 10 Submit Document Feedback CP COUNT MR OUTPUT ↑ L No change ↓ L Count X H LLLL H = high voltage level, L = low voltage level, X = don’t care, ↑ = transition from low to high level, ↓ = transition from high to low. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 11 CD54HC393, CD74HC393, CD54HCT393, CD74HCT393 www.ti.com SCHS186F – SEPTEMBER 1997 – REVISED MARCH 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC393 CD74HC393 CD54HCT393 CD74HCT393 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8989001CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8989001CA CD54HCT393F3A Samples CD54HC393F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8410001CA CD54HC393F3A Samples CD54HCT393F ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT393F Samples CD54HCT393F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8989001CA CD54HCT393F3A Samples CD74HC393E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC393E Samples CD74HC393M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC393M Samples CD74HC393M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC393M Samples CD74HC393MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC393M Samples CD74HCT393E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT393E Samples CD74HCT393M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT393M Samples CD74HCT393M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT393M Samples CD74HCT393MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT393M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of