CD74HC40103QM96Q1

CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 D Qualified for Automotive Applications D Synchronous or Asynchronous Preset D Cascadable in Synchronous or Ripple D D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V Mode Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads M PACKAGE (TOP VIEW) CP MR TE P0 P1 P2 P3 GND D Balanced Propagation Delay and Transition D Times Significant Power Reduction Compared to LSTTL Logic ICs 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC PE (SYNC) TC P7 P6 P5 P4 PL (ASYNC) description/ordering information The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage synchronous down counter with a single output, which is active when the internal count is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC) output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches zero, if TE is low, and remains low for one full clock period. When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE, or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset (MR) input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long. ORDERING INFORMATION{ −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA SOIC − M Tape and reel TOP-SIDE MARKING CD74HC40103QM96Q1 HC40103Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 description/ordering information (continued) The CD74HC40103 may be cascaded using the TE input and the TC output, in either synchronous or ripple mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads. FUNCTION TABLE CONTROL INPUTS MR PL PE TE H H H H H H H L H H L X H L X X L X X X PRESET MODE ACTION Inhibit counter Synchronous Count down Preset on next positive clock transition Asynchronous Preset asynchronously Clear to maximum count NOTE: H = high voltage level, L = low voltage level, X = don’t care Clock connected to clock input Synchronous operation: changes occur on negative-to-positive clock transitions. Load inputs: MSB = P7, LSB = P0 logic diagram (positive logic) TC 14 13 12 11 10 7 6 5 P7 P6 P5 P4 P3 P2 P1 P0 CP GND 4 15 2 9 3 1 POST OFFICE BOX 655303 2 16 8 • DALLAS, TEXAS 75265 CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Source or sink current per output pin, IO (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VCC = 2 V VIH VCC = 4.5 V High-level High level input voltage VCC = 6 V MIN MAX 2 6 3.15 0.5 1.35 VCC = 6 V VI Input voltage VO Output voltage tt Input transition (rise and fall) time TA Operating free-air temperature V 4.2 VCC = 4.5 V Low-level Low level input voltage V 1.8 0 VCC V V 0 VCC VCC = 2 V 0 1000 VCC = 4.5 V 0 500 0 400 −40 125 VCC = 6 V V 1.5 VCC = 2 V VIL UNIT ns °C NOTES: 3. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IO (mA) TEST CONDITIONS CMOS loads VOH VI = VIH or VIL TTL loads CMOS loads VOL VI = VIH or VIL TTL loads 4 II VI = VCC or GND ICC VI = VCC or GND CIN CL = 50 pF TA = 25°C MIN MAX MIN −0.02 2V 1.9 1.9 −0.02 4.5 V 4.4 4.4 −0.02 6V 5.9 5.9 3.7 MAX UNIT V −4 4.5 V 3.98 −5.2 6V 5.48 0.02 2V 0.1 0.1 0.02 4.5 V 0.1 0.1 0.02 6V 0.1 0.1 4 4.5 V 0.26 0.4 5.2 6V 0.26 0.4 6V ±0.1 ±1 µA 8 160 µA 10 10 pF 0 POST OFFICE BOX 655303 VCC • DALLAS, TEXAS 75265 6V 5.2 V CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER CP tw Pulse duration PL MR fmax CP frequency (see Note 4) P to CP PE to CP tsu To CP, MR inactive P to CP Hold time TE to CP PE to CP TA = 25°C MIN MAX MIN 2V 165 250 4.5 V 33 50 6V 28 43 2V 125 190 4.5 V 25 38 6V 21 32 2V 125 190 4.5 V 25 38 6V 21 32 2V 3 2 4.5 V 15 10 6V 18 12 2V 100 150 4.5 V 20 30 6V 17 26 2V 75 110 4.5 V 15 22 6V 13 19 2V 150 225 4.5 V 30 45 6V 26 38 2V 50 75 4.5 V 10 15 6V 9 13 2V 5 5 4.5 V 5 5 6V 5 5 2V 0 0 4.5 V 0 0 6V 0 0 2V 2 2 4.5 V 2 2 6V 2 2 Setup time TE to CP th VCC MAX UNIT ns MHz ns ns NOTE 4: Noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, count enables (PE or TE) to clock setup times, and count enables (PE or TE) to clock hold times determine maximum clock frequency. For example, with these HC devices: 1 1 + [ 11 MHz CP f max + 60 ) 30 ) 0 CP to TC prop delay ) TE to CP setup time ) TE to CP hold time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) LOAD CAPACITANCE VCC 2V 300 450 TC (asynchronous preset) CL = 50 pF 4.5 V 60 90 6V 51 77 2V 300 450 4.5 V 60 90 51 77 2V 200 300 4.5 V 40 60 6V 34 51 CL = 15 pF CP TC (synchronous preset) CL = 50 pF TE PL TC TC CL = 50 pF TC tt fmax CP 5V TYP 5V MAX MIN MAX 25 5V 2V 275 415 CL = 50 pF 4.5 V 55 83 47 71 2V 275 415 4.5 V 55 83 6V 47 71 CL = 50 pF 23 CL = 15 pF 5V 2V 75 110 CL = 50 pF 4.5 V 15 22 6V 13 19 CL = 15 pF 5V ns 17 6V 5V UNIT 25 CL = 15 pF CL = 15 pF MR MIN 6V CL = 15 pF tpd TA = 25°C TO (OUTPUT) 23 25 ns MHz operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns PARAMETER Cpd TYP Power dissipation capacitance (see Note 5) 25 NOTE 5: Cpd is used to determine the dynamic power consumption per package. PD = (Cpd × VCC2 × fi) + (CL × VCC2 × fO) fI = input frequency fO = output frequency CL = output load capacitance VCC = supply voltage 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0V tPLH VCC Reference Input In-Phase Output 50% 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 CP MR TE PE PL P0 P1 P2 P3 P4 P5 P6 P7 TC Count 255 254 3 2 1 0 255 254 254 253 8 7 Figure 2. Timing Diagram 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 5 4 255 254 253 252 PACKAGE OPTION ADDENDUM www.ti.com 6-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing CD74HC40103QM96Q1 OBSOLETE SOIC D 16 HC40103QM96G4Q1 ACTIVE SOIC D 16 2500 Eco Plan Lead/Ball Finish MSL Peak Temp Samples (3) (Requires Login) (2) TBD Call TI Green (RoHS & no Sb/Br) CU NIPDAU Call TI Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF CD74HC40103-Q1 : • Catalog: CD74HC40103 • Enhanced Product: CD74HC40103-EP Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Jan-2013 • Military: CD54HC40103 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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