CD54HC4511, CD74HC4511, CD74HCT4511
SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
CDx4HC4511, CD74HCT4511 BCD-to-7 Segment Latch/Decoder/Drivers
1 Features
2 Description
•
•
•
The
CD54HC4511,
CD74HC4511,
and
CD74HCT4511 are BCD-to-7 segment latch/decoder/
drivers with four address inputs (D0−D3), an activelow blanking (BL) input, lamp-test (LT) input, and a
latch-enable (LE) input that, when high, enables the
latches to store the BCD inputs. When LE is low, the
latches are disabled, making the outputs transparent
to the BCD inputs.
•
•
•
•
•
•
2-V to 6-V VCC operation ('HC4511)
4.5-V to 5.5-V VCC operation (CD74HCT4511)
High-output sourcing capability
– 7.5 mA at 4.5 V (CD74HCT4511)
– 10 mA at 6 V ('HC4511)
Input latches for BCD code storage
Lamp test and blanking capability
Balanced propagation delays and transition times
Significant power reduction compared to LSTTL
logic IC's
'HC4511
– High noise immunity,
NIL or NIH = 30% of VCC at VCC = 5 V
CD74HCT4511
– Direct LSTTL input logic compatibility, VIL = 0.8
V Maximum, VIH = 2 V minimum
– CMOS input compatibility, II ≤ 1μA at VOL, VOH
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
CD54HC4511
J (CDIP, 16)
24.38 mm × 6.92 mm
CD74HC4511
N (PDIP, 16)
19.31 mm × 6.35 mm
D (SOIC, 16)
9.90 mm × 3.90 mm
PW (TSSOP, 16)
5.00 mm × 4.40 mm
N (PDIP, 16)
19.31 mm × 6.35 mm
CD74HCT4511
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Display
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC4511, CD74HC4511, CD74HCT4511
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions for
'HC4511(1) .................................................................... 4
5.3 Recommended Operating Conditions for
CD74HCT4511(1) ..........................................................4
5.4 Thermal Information....................................................5
5.5 'HC4511 Electrical Characteristics.............................. 5
5.6 CD74HCT4511 Electrical Characteristics................... 5
5.7 'HC4511 Timing Requirements................................... 6
5.8 Switching Characteristics............................................6
5.9 CD74HCT4511 Timing Requirements.........................7
5.10 CD74HCT4511 Switching Characteristics................ 7
5.11 Operating Characteristics..........................................7
6 Parameter Measurement Information............................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Receiving Notification of Documentation Updates..12
10.2 Support Resources................................................. 12
10.3 Trademarks............................................................. 12
10.4 Electrostatic Discharge Caution..............................12
10.5 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
11.1 Tape and Reel Information...................................... 13
11.2 Mechanical Data..................................................... 14
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2003) to Revision E (August 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
4 Pin Configuration and Functions
J, N, D, PW package
16-Pin CDIP, PDIP, SOIC, TSSOP
Top View
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
VCC
Supply voltage
MIN
MAX
– 0.5
7
(1)
UNIT
V
IIK
Input diode current
VI < – 0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output diode current
VO < – 0.5 V or VO > VCC + 0.5 V (1)
±20
mA
IO
Output source or sink current per output pin
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
At distance 1/16 ± 1/32 in (1.59 ± 0.79
mm) from case for 10 s maximum
265
°C
Unit inserted into a PC board (minimum
thickness 1/16 in, 1.59 mm) (with solder
contacting lead tips only)
300
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
Lead temperature (During Soldering)
(1)
– 65
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
5.2 Recommended Operating Conditions for 'HC4511(1)
TA = – 55°C to
125°C
TA = 25°C
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
MIN
NOM
2
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
3.15
3.15
3.15
4.2
4.2
4.2
6
0.5
0.5
0.5
1.35
1.35
1.8
0
1.8
VCC
0
VCC
0
V
V
1.35
0
VCC = 2 V
(1)
2
1.5
VCC = 4.5 V
Input transition rise/fall time
6
1.5
VCC = 6 V
tt
2
1.5
VCC = 2 V
VIL
MAX
TA = – 40°C to
85°C
UNIT
MIN NOM MAX
V
1.8
VCC
0
VCC
0
VCC
V
VCC
V
1000
1000
1000
VCC = 4.5 V
500
500
500
VCC = 6 V
400
400
400
ns
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
5.3 Recommended Operating Conditions for CD74HCT4511(1)
TA = – 55°C to 125°C TA = – 55°C to 125°C
4
VCC
Supply Voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
VO
TA = – 40°C to 85°C
MIN
MAX
MIN
MAX
MIN
4.5
5.5
4.5
5.5
4.5
2
2
MAX
UNIT
5.5 V
2
V
0.8
0.8
Input voltage
VCC
VCC
VCC V
Output voltage
VCC
VCC
VCC V
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0.8
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
5.3 Recommended Operating Conditions for CD74HCT4511(1) (continued)
TA = – 55°C to 125°C TA = – 55°C to 125°C
MIN
tt
MAX
Input transition (rise and fall) time
(1)
MIN
TA = – 40°C to 85°C
MAX
500
MIN
500
MAX
UNIT
500 ns
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.
5.4 Thermal Information
THERMAL
RθJA
(1)
D (SOIC)
N (PDIP)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
UNIT
67
73
108
°C/W
METRIC(1)
Package thermal impedance
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
5.5 'HC4511 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
High level output voltage
MAX
MIN
2V
1.9
1.9
1.9
4.4
4.4
4.4
6V
5.9
5.9
5.9
IOH = −4 mA
4.5 V
3.98
3.7
3.84
6V
5.48
IOL = 20 μA
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
MIN
4.5 V
VI = VIH or VIL
Low level output voltage
MAX
TA = – 40°C
to 85°C
IOH = −20 μA
IOH = −5.2 mA
VOL
TA = – 55°C
to 125°C
TA = 25°C
VCC
5.2
UNIT
MAX
V
5.34
2V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
6V
0.1
0.1
0.1
4.5 V
0.26
0.4
0.33
6V
0.26
0.4
0.33
V
Input leakage current V
VI = VCC or 0
6V
±0.1
±1
±1
μA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
8
160
80
μA
Ci
Input Capacitance
2 V to
6V
10
10
10
pF
5.6 CD74HCT4511 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VOH
High level output
voltage
VI = VIH or VIL
VOL
Low level output
voltage
VI = VIH or VIL
Input leakage current
V
VI = VCC to GND
ICC
Supply current
VI = VCC or 0,
ΔICC (1)
Supply-Current
Change
II
IOH = −20 μA
IOH = −4 mA
IOL = 20 μA
IOL = 4 mA
IO = 0
LT, LE inputs held at VCC – 2.1 V
BL, Dn inputs held at VCC – 2.1 V
4.5 V
TA = −55°C
to 125°C
TA = 25°C
TYP
MAX
MIN
TA= – 40°C to
85°C
UNIT
MAX
MIN MAX
4.4
4.4
4.4
3.98
3.7
3.84
V
0.1
0.1
0.1
0.26
0.4
0.33
5.5 V
±0.1
±1
±1
μA
5.5 V
8
160
80
μA
100
540
735
675
100
108
147
135
4.5 V
4.5 V
to 5.5
V
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
5.6 CD74HCT4511 Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Ci
(1)
TA = −55°C
to 125°C
TA = 25°C
VCC
TYP
MAX
Input Capacitance
MIN
10
TA= – 40°C to
85°C
UNIT
MAX
MIN MAX
10
10
pF
Additional supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC =
5.5 V) specification is 1.8 mA.
5.7 'HC4511 Timing Requirements
TA = 25°C
TA = – 55°C to
125°C
VCC
MIN
tW
tsu
th
Pulse duration, LE low
Setup time, BCD inputs before LE↑
Hold time, BCD inputs before LE↑
MAX
MIN
MAX
TA = – 40°C to
85°C
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
60
90
75
4.5 V
12
18
15
6V
10
15
13
2V
3
3
3
4.5 V
3
3
3
6V
3
3
3
UNIT
MAX
ns
ns
ns
5.8 Switching Characteristics
PARAMETER
FROM
(INPUT)
Dn
TO
LOAD
(OUTPUT) CAPACITANCE
Output
CL = 50 pF
CL = 15 pF
LE
Output
CL = 15 pF
tpd
BL
LT
tt
6
CL = 50 pF
Output
Output
Any
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CL = 50 pF
TA = 25°C
VCC
MIN
TYP
MAX
TA = – 55°C TO TA = – 40°C TO
125°C
85°C
UNIT
MIN MAX
MIN
MAX
2V
300
450
375
4.5 V
60
90
75
6V
51
77
64
2V
270
405
340
4.5 V
54
81
68
6V
46
69
58
2V
220
330
275
4.5 V
44
66
55
37
56
47
5V
5V
25
23
6V
CL = 15 pF
5V
2V
160
240
200
CL = 50 pF
4.5 V
32
48
40
27
41
34
95
ns
18
6V
CL = 15 pF
5V
13
2V
75
110
CL = 50 pF
4.5 V
15
22
19 ns
6V
13
19
16
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
5.9 CD74HCT4511 Timing Requirements
TA = 25°C
MIN
TA = – 55°C TO 125
°C
MAX
MIN
MAX
TA = – 40°C TO 85°C UNIT
MIN
MAX
tw
Pulse duration, LE low
16
24
20
ns
tsu
Setup time, BCD inputs before LE↑
16
24
20
ns
th
Hold time, BCD inputs before LE↑
5
5
5
ns
over operating free-air temperature range (unless otherwise noted)
5.10 CD74HCT4511 Switching Characteristics
PARAMETER
FROM
(INPUT)
Dn
LE
tpd
BL
LT
tt
TO
LOAD
(OUTPUT) CAPACITANCE
Output
Output
Output
Output
Any
MIN
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
CL = 15 pF
5V
CL = 50 pF
4.5 V
TA = – 55°C to TA = – 40°C to
125°C
85°C
TA = 25°C
VCC
TYP
MAX
MIN
MAX
MIN
UNIT
MAX
60
90
75
54
81
68
44
66
55
33
50
41
15
22
19
TYP
UNIT
25
23
ns
18
13
ns
5.11 Operating Characteristics
PARAMETER(1)
Cpd
(1)
Power dissipation capacitance
'HC4511
114
CD74HCT4511
110
pF
Cpd is used to determine the dynamic power consumption, per package.
PD = CpdVCC 2 fi + Σ CL VCC 2fo where:
fi = input frequency
fo = output frequency
CL = output load capacitance
VCC = supply voltage
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6 Parameter Measurement Information
Figure 6-1. 'HC4511
8
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Figure 6-2. CD74HCT4511
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7 Detailed Description
7.1 Overview
The CD54HC4511, CD74HC4511, and CD74HCT4511 are BCD-to-7 segment latch/decoder/drivers with four
address inputs (D0−D3), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable (LE) input
that, when high, enables the latches to store the BCD inputs. When LE is low, the latches are disabled, making
the outputs transparent to the BCD inputs.
These devices have standard-size output transistors, but are capable of sourcing (at standard VOH levels) up to
7.5 mA at 4.5 V. The HC types can supply up to 10 mA at 6 V.
7.2 Functional Block Diagram
Figure 7-1. Function Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS(1)
(1)
(2)
10
LE
BL
X
X
OUTPUTS(2)
LT
D3
D2
D1
D0
a
b
c
d
e
f
g
DISPLAY
X
L
X
X
X
X
H
H
H
H
H
H
H
8
L
H
X
X
X
X
L
L
L
L
L
L
L
Blank
L
H
H
L
L
L
L
H
H
H
H
H
H
L
0
L
H
H
L
L
L
H
L
H
H
L
L
L
L
1
L
H
H
L
L
H
L
H
H
L
H
H
L
H
2
L
H
H
L
L
H
H
H
H
H
H
L
L
H
3
L
H
H
L
H
L
L
L
H
H
L
L
H
H
4
L
H
H
L
H
L
H
H
L
H
H
L
H
H
5
L
H
H
L
H
H
L
L
L
H
H
H
H
H
6
L
H
H
L
H
H
H
H
H
H
L
L
L
L
7
L
H
H
H
L
L
L
H
H
H
H
H
H
H
8
L
H
H
H
L
L
H
H
H
H
L
L
H
H
9
L
H
H
H
L
H
L
L
L
L
L
L
L
L
Blank
L
H
H
H
L
H
H
L
L
L
L
L
L
L
Blank
L
H
H
H
H
L
L
L
L
L
L
L
L
L
Blank
L
H
H
H
H
L
H
L
L
L
L
L
L
L
Blank
L
H
H
H
H
H
L
L
L
L
L
L
L
L
Blank
L
H
H
H
H
H
H
L
L
L
L
L
L
L
Blank
H
H
H
X
X
X
X
t
t
t
t
t
t
t
t
H = High Voltage Level, L = Low Voltage Level, X = Don't caret = Depends on BCD code previously applied when LE = LNOTE:
Display is blank for all illegal input codes (BCD > HLLH).
H = Driving High, L = Driving Low, Z = High Impedance State
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
PTAS6584QDKQQ1
HTQFP
PHD
64
1000
330.0
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
24.4
17.0
17.0
1.5
20.0
24.0
Q2
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CD54HC4511, CD74HC4511, CD74HCT4511
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PTAS6584QPHDRQ1
HTQFP
PHD
64
1000
350.0
350.0
43.0
11.2 Mechanical Data
14
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4511 CD74HC4511 CD74HCT4511
CD54HC4511, CD74HC4511, CD74HCT4511
www.ti.com
SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
PACKAGE OUTLINE
HTQFP - 1.2 mm max height
PHD0064B
PLASTIC QUAD FLATPACK
14.05
13.95
NOTE 3
PIN 1 ID
64
8.00
6.68
B
49
48
1
THERMAL PAD
4
14.05
13.95
NOTE 3
16.15
15.85
TYP
8.00
6.68
16
33
32
17
A
64 X 0.40
0.30
60 X 0.8
4 X 12
0.2
C A B
SEE DETAIL A
C
1.2 MAX
SEATING PLANE
(0.127) TYP
17
32
16
33
0.25
GAGE PLANE
1.05
0.95
0°-7°
0.75
0.45
1
48
64
49
0.15
0.05
0.1 C
DETAIL A
TYPICAL
4224850/A 05/2019
NOTES:
1.
2.
3.
4.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
See technical brief. PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
(www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004) for information regarding recommended board layout.
www.ti.com
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CD54HC4511, CD74HC4511, CD74HCT4511
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SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
EXAMPLE BOARD LAYOUT
HTQFP - 1.2 mm max height
PHD0064B
PLASTIC QUAD FLATPACK
SYMM
49
64
64 X (1.5)
1
48
64 X (0.55)
60 X (0.8)
SYMM
(15.4)
33
16
(R0.05) TYP
32
17
(15.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224850/A 05/2019
NOTES: (continued)
5.
6.
7.
Publication IPC-7351 may have alternate designs.
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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16
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Product Folder Links: CD54HC4511 CD74HC4511 CD74HCT4511
CD54HC4511, CD74HC4511, CD74HCT4511
www.ti.com
SCHS279E – DECEMBER 1998 – REVISED AUGUST 2022
EXAMPLE STENCIL DESIGN
HTQFP - 1.2 mm max height
PHD0064B
PLASTIC QUAD FLATPACK
SYMM
49
64
64 X (1.5)
1
48
64 X (0.55)
60 X (0.8)
SYMM
(15.4)
33
(R0.05) TYP
16
32
17
(15.4)
SOLDER PASTE EXAMPLE
SCALE: 6X
4224850/A 05/2019
NOTES: (continued)
7.
8.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4511 CD74HC4511 CD74HCT4511
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17
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8773301EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8773301EA
CD54HC4511F3A
Samples
CD54HC4511F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8773301EA
CD54HC4511F3A
Samples
CD74HC4511E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4511E
Samples
CD74HC4511EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4511E
Samples
CD74HC4511M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4511M
Samples
CD74HC4511M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4511M
Samples
CD74HC4511M96E4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4511M
Samples
CD74HC4511MG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4511M
Samples
CD74HC4511MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4511M
Samples
CD74HC4511PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4511
Samples
CD74HC4511PWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4511
Samples
CD74HC4511PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4511
Samples
CD74HC4511PWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4511
Samples
CD74HCT4511E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4511E
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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