CD74HC4543E

[ /Title (CD74 HC454 3) /Subject (HighSpeed CMOS Logic BCDto-7 CD74HC4543 Data sheet acquired from Harris Semiconductor SCHS217B High-Speed CMOS Logic BCD to 7-Segment Latch/Decoder/Driver for LCDs February 1998 - Revised July 2003 Features Description • Input Latches for BCD Code Storage The CD74HC4543 high-speed silicon-gate device is a BCD to 7-segment latch/decoder/driver designed primarily for directly driving liquid-crystal displays. It has an active-high disable input (LD), an active-high blanking input (BI) and a phase input (PH) to which a square wave is applied for liquid-crystal applications. This square wave also is applied to the backplane of the liquid-crystal display. • Blanking Capability • Phase Input for Complementing Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads This device also can be used, in conjunction with current amplifying devices, for driving LEDs, incandescent, fluorescent, and gas-discharge displays. For these applications the phase input provides a means to obtain active-high or active-low segment outputs. (See the Function Table.) • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs Ordering Information • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V PART NUMBER TEMP. RANGE (oC) CD74HC4543E Pinout CD74HC4543 (PDIP) TOP VIEW BCD INPUTS LD 1 16 VCC D2 2 15 f D1 3 14 g D3 4 13 e D0 5 12 d PH 6 11 c BI 7 10 b GND 8 9 a 7-SEGMENT OUTPUTS CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 -55 to 125 PACKAGE 16 Ld PDIP CD74HC4543 Functional Diagram PH D3 2 11 DRIVER D2 3 DECODER D1 BCD INPUTS 9 10 LATCH D0 6 5 4 12 13 15 14 1 LD a b c 7 - SEGMENT OUTPUTS d e f g 7 BI GND = 8 VCC = 16 FUNCTION TABLE INPUTS OUTPUTS LD BI PH D3 D2 D1 D0 a b c d e f g DISPLAY X H L X X X X L L L L L L L Blank H L L L L L L H H H H H H L 0 H L L L L L H L H H L L L L 1 H L L L L H L H H L H H L H 2 H L L L L H H H H H H L L H 3 H L L L H L L L H H L L H H 4 H L L L H L H H L H H L H H 5 H L L L H H L H L H H H H H 6 H L L L H H H H H H L L L L 7 H L L H L L L H H H H H H H 8 H L L H L L H H H H H L H H 9 H L L H L H L L L L L L L L Blank H L L H L H H L L L L L L L Blank H L L H H L L L L L L L L L Blank H L L H H L H L L L L L L L Blank H L L H H H L L L L L L L L Blank H L L H H H H L L L L L L L Blank L L L X X X X As Above H As Above Note 1 Note 1 Inverse of Above As Above NOTE: 1. Depends on BCD code previously applied when LD = high. DISPLAY a f b g e 0 1 2 3 4 5 6 2 7 8 9 c d CD74HC4543 7 9 BI a 5 D0 Q0 D0 10 b LATCH LD LD Q0 LD LD 11 c 3 D1 D1 Q1 LATCH LD LD 12 d LD Q1 LD LD Dn Qn Qn 2 D2 D2 LD LD Q2 LD LATCH LD LD LD Dn P N Qn LD Q2 LD 13 e P N LD 4 D3 D3 Q3 15 LATCH LD LD f LD Q3 LD 1 LD LD 14 g 6 LD PH FIGURE 1. LOGIC DIAGRAM 3 Qn CD74HC4543 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 2) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads Quiescent Device Current -55oC TO 125oC VI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX UNITS VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -1 4.5 3.98 - - 3.84 - 3.7 - V -1.3 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V VIL VOH - VIH or VIL VOL VIH or VIL Low Level Output Voltage TTL Loads (Standard Output) Input Leakage Current -40oC TO 85oC SYMBOL High Level Output Voltage TTL Loads (Non-Standard) Low Level Output Voltage CMOS Loads 25oC VCC (V) - - - - - - - - - - V 1 4.5 - - 0.26 - 0.33 - 0.4 V 1.3 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD74HC4543 Prerequisite for Switching Specifications 25oC PARAMETER Setup Time Dn to LD -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tSU 2 60 - - 75 - - 90 - - ns 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns 2 30 - - 40 - - 45 - - ns 4.5 6 - - 8 - - 9 - - ns 6 5 - - 7 - - 8 - - ns 2 50 - - 65 - - 75 - - ns 4.5 10 - - 13 - - 15 - - ns 6 9 - - 11 - - 13 - - ns Hold Time Dn to LD Latch Disable Pulse Width -40oC TO 85oC tH tW Switching Specifications Input tr, tf = 6ns PARAMETER Propagation Delay, Dn to Output Propagation Delay, LD to Output Propagation Delay, BI to Output Propagation Delay, PH to Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 3, 4) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 340 - 425 - 510 ns 4.5 - - 68 - 85 - 102 ns 6 - - 58 - 72 - 87 ns CL = 15pF 5 - 28 - - - - - ns CL = 50pF 2 - - 370 - 465 - 555 ns 4.5 - - 74 - 93 - 111 ns 6 - - 63 - 79 - 94 ns CL = 15pF 5 - 31 - - - - - ns CL = 50pF 2 - - 265 - 330 - 400 ns 4.5 - - 53 - 66 - 80 ns 6 - - 45 - 56 - 68 ns CL = 15pF 5 - 22 - - - - - ns CL = 50pF 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns 6 - - 34 - 43 - 51 ns CL = 15pF 5 - 17 - - - - - ns CL = 50pF 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns 6 - - 43 - 54 - 64 ns tPLH, tPHL tPLH, tPHL tPLH, tPHL tTHL, tTLH CI - - - - 10 - 10 - 10 pF CPD - 5 - 52 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = CPD VCC2 fi + Σ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. 5 CD74HC4543 Test Circuits and Waveforms tfCL trCL CLOCK 90% 10% tWL + tWH = tr = 6ns I fCL 50% 50% VCC 90% 50% 10% INPUT VCC 50% 10% tf = 6ns GND GND tTHL tWL tTLH tWH 90% 50% 10% INVERTING OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL trCL CLOCK INPUT tPLH VCC 90% 50% 10% GND tH(H) tH(L) VCC DATA INPUT 50% GND tSU(H) tSU(L) 90% tTLH tTHL 90% 50% 10% tPLH tPHL OUTPUT tREM VCC SET, RESET OR PRESET 50% GND IC CL 50pF FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 CD74HC4543 Application Circuits APPROPRIATE VOLTAGE HC4543 OUTPUTS ONE OF SEVEN SEGMENTS COMMON BACKPLANE PH HC4543 OUTPUT SQUARE WAVE GND TO VCC PH GND FIGURE 5. CONNECTION TO LIQUID-CRYSTAL (LCD) DISPLAY READOUT FIGURE 6. CONNECTION TO INCANDESCENT DISPLAY READOUT APPROPRIATE VOLTAGE HC4543 OUTPUT HC4543 PH TO FILAMENT SUPPLY OUTPUT GND PH GND OR APPROPRIATE VOLTAGE BELOW GND GND FIGURE 7. CONNECTION TO GAS-DISCHARGE DISPLAY READOUT FIGURE 8. CONNECTION TO FLUORESCENT DISPLAY READOUT 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) CD74HC4543E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4543E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of