CD74HC688E

CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 CDx4HC688, CDx4HCT688 High-Speed CMOS Logic 8-Bit Magnitude Comparator 1 Features 2 Description • • The ’HC688 and ’HCT688 are 8-bit magnitude comparators designed for use in computer and logic applications that require the comparison of two 8-bit binary words. When the compared words are equal the output (Y) is low and can be used as the enabling input for the next device in a cascaded application. • • • • • Cascadable Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads Wide operating temperature range: –55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT types – 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min) – CMOS input compatibility, II ≤ 1 μA at VOL,VOH Package Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC688M SOIC (20) 12.80 mm × 7.50 mm CD74HCT688M SOIC (20) 12.80 mm × 7.50 mm CD74HC688E PDIP (20) 25.40 mm × 6.35 mm CD74HCT688E PDIP (20) 25.40 mm × 6.35 mm CD74HC688NSR SO (20) 15.00 mm × 5.30 mm CD74HC688PWR TSSOP (20) 6.50 mm × 4.40 mm CD54HC688F3A CDIP (20) 26.92 mm × 6.92 mm CD54HCT688F3A CDIP (20) 26.92 mm × 6.92 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. E A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 Y A5 B5 A6 B6 A7 B7 Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings(1) .................................... 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics............................................6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Receiving Notification of Documentation Updates..10 10.2 Support Resources................................................. 10 10.3 Trademarks............................................................. 10 10.4 Electrostatic Discharge Caution..............................10 10.5 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (February 2022) to Revision E (October 2022) Page • Increased RθJA for packages: DW (58 to 109.1); N (69 to 84.6); NS (60 to 113.4); PW (83 to 131.8).............. 4 Changes from Revision C (August 2003) to Revision D (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 4 Pin Configuration and Functions J, N, DW, NS, or PW package 20-Pin CDIP, PDIP, SOIC, SO, TSSOP Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 3 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 5 Specifications 5.1 Absolute Maximum Ratings(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Output source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA ±50 mA 150 °C 150 °C 300 °C Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature range –65 Lead temperature (Soldering 10s) (SOIC - lead tips only) (1) V Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress-only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 5.2 Recommended Operating Conditions MIN VCC Supply voltage range VI, VO Input or output voltage HC types HCT types MAX 2 6 4.5 5.5 0 VCC 2V tt Input rise and fall time TA UNIT V V 1000 4.5 V 500 6V 400 Temperature range –55 125 ns ℃ 5.3 Thermal Information THERMAL METRIC N (PDIP) NS (SO) PW (TSSOP) 20 PINS 20 PINS 20 PINS 20 PINS UNIT 109.1 84.6 113.4 131.8 °C/W 76 72.5 78.6 72.2 °C/W RθJA Junction-to-ambient thermal (1) resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 77.6 65.3 78.4 82.8 °C/W ψJT Junction-to-top characterization parameter 51.5 55.3 47.1 21.5 °C/W ψJB Junction-to-board characterization parameter 77.1 65.2 78.1 82.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W (1) 4 DW (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 5.4 Electrical Characteristics TEST CONDITIONS(2) PARAMETER VCC (V) 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES VIH VIL VOH High level input voltage Low level input voltage High level output voltage High level output voltage VOL Low level output voltage Low level output voltage 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 V 4.2 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 IOH = –20 μA 2 1.9 1.9 1.9 IOH = –20 μA 4.5 4.4 4.4 4.4 IOH = –20 μA 6 5.9 5.9 5.9 IOH = –4 mA 4.5 3.98 3.84 3.7 IOH = –5.2 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 IOL = 20 μA 4.5 0.1 0.1 0.1 IOL = 20 μA 6 0.1 0.1 0.1 5.34 V V 5.2 IOL = 4 mA 4.5 0.26 0.33 0.4 IOL = 5.2 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 0.8 V 0.8 V High level output voltage IOH = –4 mA 4.5 Low level output voltage IOL = 20 μA 4.5 0.1 0.1 0.1 Low level output voltage IOL = 4 mA 4.5 0.26 0.33 0.4 VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA 8 80 160 μA ICC Supply current (1) (2) 0.8 2 IOH = –20 μA Input leakage current (1) 2 High level output voltage II ΔICC 2 Additional supply current per input pin 4.5 4.4 4.4 4.4 V 3.98 3.84 3.7 V VI = VCC or GND 5.5 Enable inputs held at VCC –2.1 4.5 to 5.5 100 252 315 343 μA Data inputs held at VCC –2.1 4.5 to 5.5 100 126 157.5 171.5 μA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 5 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 5.5 Switching Characteristics CL = 50pF. Input tr, tf = 6 ns PARAMETER VCC (V) Propagation delay (Figure 6-1) An to output 4.5 25℃ MIN TYP –40℃ to 85℃ MAX MIN MAX –55℃ to 125℃ MIN MAX UNIT HC TYPES tPLH, tPHL 2 (3) 51 29 36 43 210 255 34 42 51 29 36 43 120 150 180 24 30 36 6 20 26 30 14 (3) 2 CIN 255 42 170 4.5 tTLH, tTHL Output transition time (Figure 6-1) 210 34 2 6 tPLH, tPHL E to output 170 6 4.5 tPLH, tPHL Bn to output 14 9 (3) 2 75 95 110 4.5 15 19 22 6 13 16 19 10 10 10 Input capacitance ns ns ns ns pF 22 (4) 4.5 14 (3) 34 42 51 ns tPLH, tPHL Bn to output 4.5 14 (3) 34 42 51 ns tPLH, tPHL E to output 4.5 9 (3) 24 30 36 ns tTLH, tTHL Output transition time (Figure 6-1) 4.5 15 19 22 ns 10 10 10 pF CPD Power dissipation capacitance(1) (2) pF HCTTYPES tPLH, tPHL CIN Input capacitance CPD Power dissipation capacitance(1) (2) (1) (2) (3) (4) 6 Propagation delay (Figure 6-1) An to output 5 22 (4) pF CPD is used to determine the dynamic power consumption, per gate. PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. CL = 15 pF and VCC = 5 V. CL = 15 pF. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 6 Parameter Measurement Information Figure 6-1. Propagation Delay and Transition Times Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 7 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 7 Detailed Description 7.1 Overview The ’HC688 and ’HCT688 are 8-bit magnitude comparators designed for use in computer and logic applications that require the comparison of two 8-bit binary words. When the compared words are equal the output (Y) is low and can be used as the enabling input for the next device in a cascaded application. 7.2 Functional Block Diagram E A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 Y A5 B5 A6 B6 A7 B7 7.3 Device Functional Modes Table 7-1. Truth Table(1) INPUTS (1) 8 Submit Document Feedback OUPUTS A, B E Y A=B L L A≠B L H X H H H = high voltage level, L = low voltage level, X = don’t care. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 9 CD54HC688, CD74HC688, CD54HCT688, CD74HCT688 www.ti.com SCHS196E – SEPTEMBER 1997 – REVISED OCTOBER 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC688 CD74HC688 CD54HCT688 CD74HCT688 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8685701RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8685701RA CD54HCT688F3A Samples CD54HC688F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8681801RA CD54HC688F3A Samples CD54HCT688F ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT688F Samples CD54HCT688F3A ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8685701RA CD54HCT688F3A Samples CD74HC688E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC688E Samples CD74HC688M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC688M Samples CD74HC688M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC688M Samples CD74HC688NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC688M Samples CD74HC688PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ688 Samples CD74HC688PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ688 Samples CD74HCT688E ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT688E Samples CD74HCT688EE4 ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT688E Samples CD74HCT688M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT688M Samples CD74HCT688M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT688M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of