CD74HC93, CD74HCT93
SCHS138D – NOVEMBER 1998 – REVISED MARCH 2022
CD74HC93, CD74HCT93 High-Speed CMOS Logic 4-Bit Binary Ripple Counter
1 Features
2 Description
•
•
•
The CD74HC93 and CD74HCT93 are high-speed
silicon-gate CMOS devices and are pin-compatible
with low power Schottky TTL (LSTTL). These 4bit binary ripple counters consist of four flip-flops
internally connected to provide a divide-by-two section
and a divide-by-eight section. Each section has
a separate clock input (CP0 and CP1) to initiate
state changes of the counter on the HIGH to LOW
clock transition. State changes of the Qn outputs do
not occur simultaneously because of internal ripple
delays. Therefore, decoded output signals are subject
to decoding spikes and should not be used for clocks
or strobes.
•
•
•
•
•
Can be configured to divide by 2, 8, and 16
Asynchronous reset
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: – 55°C to
125°C
Balances propagation delay and transition times
Signigicant power reduction compared to LSTTL
logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 µA at VOL, VOH
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HC93M
SOIC (14)
8.65 mm × 3.90 mm
CD74HC93E
PDIP (14)
19.31 mm × 6.35 mm
CD74HCT93E
PDIP (14)
19.31 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Shared control logic
MR1
MR2
R
R
D
Q
R
Q
CP0
Q0
Divide-by-two section
R
D
Q
R
Q
CP1
D
Q1
Q
R
Q
D
Q2
Q
R
Q
Q3
Divide-by-eight section
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD74HC93, CD74HCT93
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SCHS138D – NOVEMBER 1998 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics ................. 6
5.6 Switching Characteristics ...........................................6
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Documentation Support.......................................... 12
10.2 Receiving Notification of Documentation Updates..12
10.3 Support Resources................................................. 12
10.4 Trademarks............................................................. 12
10.5 Electrostatic Discharge Caution..............................12
10.6 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2003) to Revision D (March 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS138D – NOVEMBER 1998 – REVISED MARCH 2022
4 Pin Configuration and Functions
N or D package
14-Pin PDIP or SOIC
Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
(2)
IIK
Input diode current
IOK
Output diode current
IO
7
UNIT
V
±20
mA
(VO < – 0.5 V or VO > VCC + 0.5 V)
±20
mA
Output source or sink current per
(VO > – 0.5 V or VO < VCC + 0.5 V)
output pin
±25
mA
Continuous current through VCC or GND
±50
mA
150
°C
150
°C
Junction temperature
Tstg
Storage temperature
(2)
MAX
-0.5
(VI < – 0.5 V or VI > VCC + 0.5 V)
(2)
TJ
(1)
MIN
-65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions
MIN
MAX
UNIT
2
6
4.5
5.5
Input voltage
0
VCC
V
Output voltage
0
VCC
V
VCC
Supply voltage
VI
VO
tt
Input transition rise/fall time
TA
Operating free-air temperature
HC types
NOM
HCT types
2V
V
1000
4.5 V
500
6V
ns
400
– 55
125
°C
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal resistance
(1)
D (SOIC)
N (PDIP)
14 PINS
14 PINS
UNIT
86
80
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS138D – NOVEMBER 1998 – REVISED MARCH 2022
5.4 Electrical Characteristics
PARAMETER
TEST CONDITIONS(1)
VCC
(V)
– 40°C to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
– 55°C to
125°C
MIN
UNIT
MAX
HC TYPES
VIH
VIL
High level input voltage
Low level input voltage
2
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
V
6
4.2
4.2
4.2
V
2
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
V
1.8
V
6
VOH
VOL
High-level output voltage
Input leakage current
ICC
Supply current
ICC
Supply-current change
Ci
Input capacitance
1.8
2
1.9
1.9
1.9
V
IOH = – 20 μA
4.5
4.4
4.4
4.4
V
IOH = – 20 μA
6
5.9
5.9
5.9
V
IOH = – 4 mA
4.5
3.98
3.84
3.7
V
IOH = – 5.2 mA
6
5.48
5.34
5.2
V
Low-level output voltage
II
1.8
IOH = – 20 μA
IOL = 20 μA
2
0.1
0.1
0.1
V
IOL = 20 μA
4.5
0.1
10.1
0.1
V
IOL = 20 μA
6
0.1
0.1
0.1
V
IOL = 4 mA
4.5
0.26
0.33
0.4
V
IOL = 5.2 mA
6
0.26
0.33
0.4
V
VCC or GND
6
±0.1
±1
±1
nA
VCC or GND
6
8
80
160
μA
One input at 0.5 V or
2.4 V, Other inputs at 0
or VCC
5.5
1.4
2.4
2.9
mA
3
10
10
pF
4.5 to
5.5
HCT TYPES
VIH
High level input voltage
4.5 to
5.5
VIL
Low level input voltage
4.5 to
5.5
VOH
High level Output Voltage
2
2
0.8
2
0.8
4.4
V
0.8
IOH = – 20 μA
4.5
4.4
4.4
IOH = – 4 mA
4.5
3.98
IOH = 20 μA
4.5
0.1
0.1
0.1
3.84
V
V
3.7
V
V
VOL
Low level output voltage
IOH = 4 mA
4.5
0.26
0.33
0.4
V
II
Input leakage current
VCC or GND
5.5
±0.1
±1
±1
μA
ICC
Supply current
VCC or GND
5.5
8
80
160
μA
CP0,CP1
4.5 to
5.5
100
216
270
294
CLR1, CLR2
4.5 to
5.5
100
144
180
196
ΔICC (2) Additional supply current
(3)
per input pin
(1)
(2)
(3)
μA
μA
VI = VIH or VIL, unless otherwise noted.
For dual-supply systems theorietical worst case (VI = 2.4 V, VCC = 5.5 V) specifications is 1.8 mA.
Inputs held at VCC – 2.1.
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5.5 Prerequisite for Switching Characteristics
PARAMETER
25°C
VCC (V)
MIN
– 40°C to 85°C
MAX
MIN
MAX
– 55°C to 125°C
MIN
MAX
UNIT
HC TYPES
fMAX
tW
tw
tREM
Maximum clock frequency
Clock pulse width CP0, CP1
Reset pulse width
Reset removal time
2
6
5
4
MHz
4.5
30
24
20
MHz
6
35
28
24
MHz
2
80
100
120
ns
4.5
16
20
24
ns
6
14
17
20
ns
2
80
100
120
ns
4.5
16
20
24
ns
6
14
17
20
ns
2
50
65
75
ns
4.5
10
13
15
ns
6
9
11
13
ns
HCT TYPES
fMAX
Maximum clock frequency
4.5
30
24
20
MHz
tW
Clock pulse width CP0, CP1
4.5
16
20
24
ns
tW
Reset pulse width
4.5
16
20
24
ns
tREM
Reset removal time
4.5
10
13
15
ns
5.6 Switching Characteristics
Input tr, tf = 6ns. CL = 50pF unless otherwise noted
PARAMETER
VCC (V)
25°C
MIN
– 40°C to 85°C
TYP
MAX
MIN
– 55°C to 125°C
MAX
MIN
MAX
UNIT
HC TYPES
2
tPLH, tPHL CP0 to Q0
tPLH, tPHL CP1 to Q1
tPLH, tPHL CP1 to Q2
4.5
(1)
10
tPLH, tPHL MR1, MR2 to Qn
tTLH, tTHL Output transition time
CIN
6
Input capacitance
155
190
ns
25
31
38
ns
6
21
26
32
ns
2
135
170
205
ns
4.5
27
34
41
ns
6
23
29
35
ns
2
185
230
280
ns
4.5
37
46
56
ns
6
31
39
48
ns
245
305
370
ns
49
61
74
ns
2
tPLH, tPHL CP1 to Q3
125
4.5
(1)
21
6
42
52
63
ns
2
155
195
235
ns
4.5
13
(1)
31
39
47
ns
6
26
33
40
ns
2
75
95
110
ns
4.5
15
19
22
ns
6
13
16
19
ns
10
10
10
pF
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SCHS138D – NOVEMBER 1998 – REVISED MARCH 2022
5.6 Switching Characteristics (continued)
Input tr, tf = 6ns. CL = 50pF unless otherwise noted
PARAMETER
CPD
VCC (V)
Power dissipation capacitance
25°C
MIN
– 40°C to 85°C
TYP
MAX
25
MIN
– 55°C to 125°C
MAX
MIN
MAX
UNIT
10
19
pF
34
43
51
ns
34
43
51
ns
HCT TYPES
tPLH, tPHL CP0 to Q0
4.5
tPLH, tPHL CP1 to Q1
4.5
tPLH, tPHL CP1 to Q2
4.5
tPLH, tPHL CP1 to Q3
4.5
tPLH, tPHL MR1, MR2 to Qn
4.5
tTLH, tTHL Output Transition time
4.5
CIN
Input Capacitance
CPD
Power dissipation capacitance
(1)
(1)
14
46
58
69
ns
(1)
58
73
87
ns
(1)
33
41
50
ns
15
19
22
ns
10
10
10
pF
24
13
25
pF
CL = 15pF. VCC = 5.
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6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
VCC
Input
50%
90%
tPLH
tPHL
10%
10%
0V
(1)
tr(1)
(1)
VOH
Output
50%
10%
10%
tr(1)
tPLH(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
VOH
50%
VOH
90%
Output
VOL
Output
0V
tf(1)
90%
50%
tPHL(1)
VCC
90%
Input
50%
Figure 6-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
3V
Input
1.3V
1.3V
0V
tPLH
(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
8
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7 Detailed Description
7.1 Overview
The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low
power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four flip-flops internally connected
to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0
and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the
Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks or strobes.
A gated AND asynchronous reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all
flip-flops.
Because the output from the divide-by-two section is not internally connected to the succeeding stages, the
device may be operated in various counting modes.
In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are
applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2,
and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to
input CP1.
Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the
first flipflop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.
7.2 Functional Block Diagram
Shared control logic
MR1
MR2
R
R
D
Q
R
Q
CP0
Q0
Divide-by-two section
R
D
Q
R
Q
CP1
D
Q1
Q
R
Q
D
Q2
Q
R
Q
Q3
Divide-by-eight section
Figure 7-1. Functional Block Diagram
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7.3 Device Functional Modes
Truth Table
COUNT
(1)
OUTPUTS(1)
Q0
Q1
Q2
Q3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
10
L
H
L
H
11
H
H
L
H
12
L
L
H
H
13
H
L
H
H
14
L
H
H
H
15
H
H
H
H
H = High voltage level, L = Low voltage level.
Table 7-1. Mode Selection
OUTPUTS(1)
RESET OUTPUTS
(1)
10
MR1
MR2
Q0
Q1
Q2
Q3
H
H
L
L
L
L
Count
Count
Count
Count
L
H
H
L
L
L
H = High voltage level, L = Low voltage level.
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SCHS138D – NOVEMBER 1998 – REVISED MARCH 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD74HC93E
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC93E
Samples
CD74HC93EE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC93E
Samples
CD74HC93M
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC93M
Samples
CD74HC93M96
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC93M
Samples
CD74HC93MT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC93M
Samples
CD74HCT93E
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT93E
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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