CD74HCT165MT

CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 CDx4HC165, CDx4HCT165 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register 1 Features 2 Description • • • • The ’HC165 and ’HCT165 are 8-bit parallel or serialin shift registers with complementary serial outputs (QH and Q H) available from the last stage. When the parallel load (SH/LD) input is LOW, parallel data from the A to H inputs are loaded into the register asynchronously. When the SH/LD is HIGH, data enters the register serially at the SER input and shifts one place to the right (A→B→C, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by connecting the QH output to the SER input of the succeeding device. • • • • • Buffered inputs Asynchronous parallel load Complementary outputs Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads Wide operating temperature range: -55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC Types – 2 V to 6 V Operation – High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types – 4.5 V to 5.5 V Operation – Direct LSTTL Input Logic Compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) – CMOS Input Compatibility, II ≤ 1 μA at VOL, VOH Device Information PACKAGE BODY SIZE (NOM) CD54HC165F3A CDIP (16) 24.38 mm × 6.92 mm CD74HC165M SOIC (16) 9.90 mm × 3.90 mm CD74HC165E PDIP (16) 19.31 mm × 6.35 mm CD54HCT165F3A CDIP (16) 24.38 mm × 6.92 mm CD74HCT165M SOIC (16) 9.90 mm × 3.90 mm CD74HCT165E PDIP (16) 19.31 mm × 6.35 mm (1) A B (1) PART NUMBER C For all available packages, see the orderable addendum at the end of the data sheet. D E F G H SH/LD 5 Additional Shift Register Stages SER S R S R S R D Q D Q D Q QH Q QH CLK INH CLK Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Reccomended Operating Conditions.......................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Prerequisite for Switching Characteristics.................. 6 5.6 Switching Characteristics............................................7 6 Parameter Measurement Information............................ 8 7 Detailed Description......................................................10 7.1 Overview................................................................... 10 7.2 Functional Block Diagram......................................... 10 7.3 Device Functional Modes..........................................10 8 Power Supply Recommendations................................11 9 Layout............................................................................. 11 9.1 Layout Guidelines..................................................... 11 10 Device and Documentation Support..........................12 10.1 Receiving Notification of Documentation Updates..12 10.2 Support Resources................................................. 12 10.3 Trademarks............................................................. 12 10.4 Electrostatic Discharge Caution..............................12 10.5 Glossary..................................................................12 11 Mechanical, Packaging, and Orderable Information.................................................................... 12 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2003) to Revision D (November 2021) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 • Updated pin names to match current TI naming conventions. PL is now SH/LD, CP is now CLK, D4 is now E, D5 is now F, D6 is now G, D7 is now H, Q 7 is now Q H, Q7 is now QH, DS is now SER, D0 is now A, D1 is now B, D2 is now C, D3 is now D, CE is now CLK INH......................................................................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 4 Pin Configuration and Functions SH/LD 1 16 VCC CLK 2 CLK INH E F 3 15 14 4 13 G 5 12 C B H QH 6 11 A 7 8 10 SER QH GND 9 D J, N, or D package 16-Pin CDIP, PDIP, SOIC Top View Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 3 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 7 UNIT VCC Supply voltage V IIK Input diode current For VI < -0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current For VO < -0.5 V or VO > VCC + 0.5 V ±20 mA IO Drain current per output For VO < -0.5 V VO > VCC + 0.5 V ±25 mA IO Output source or sink current per output pin For VO > -0.5 V or VO < VCC + 0.5 V ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction temperature 150 °C Tstg Storage temperature 150 °C 300 °C -65 Lead temperature (Soldering 10s) (SOIC- Lead tips only) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Reccomended Operating Conditions MIN VCC Supply voltage range VI, VO Input or output voltage HC Types HCT Types 2 6 4.5 5.5 0 2V tt TA Input rise and fall time MAX UNIT VCC V V 1000 4.5 V 500 6V 400 Temperature range –55 125 ns ℃ 5.3 Thermal Information CD74HC165, CD74HCT165 THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) D (SOIC) N (PDIP) 16 PINS 16 PINS UNIT 73 67 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ MIN TYP -40℃ to 85℃ MAX MIN -55℃ to 125℃ MAX MIN MAX UNIT HC TYPES High level input voltage VIH Low level input voltage VIL High level output voltage VOH High level output voltage Low level output voltage VOL Low level output voltage 2 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 6 4.2 4.2 4.2 V 2 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 6 1.8 1.8 1.8 V IOH = – 20 μA 2 1.9 1.9 1.9 V IOH = – 20 μA 4.5 4.4 4.4 4.4 V IOH = – 20 μA 6 5.9 5.9 5.9 V IOH = – 4 mA 4.5 3.98 3.84 3.7 V IOH = – 5.2 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 V IOL = 20 μA 4.5 0.1 0.1 0.1 V IOL = 20 μA 6 0.1 0.1 0.1 V 5.34 5.2 V IOL = 4 mA 4.5 0.26 0.33 0.4 V IOL = 5.2 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 2 2 0.8 2 0.8 V 0.8 V High level output voltage IOH = – 20 μA 4.5 4.4 4.4 4.4 V High level output voltage IOH = – 4 mA 4.5 3.98 3.84 3.7 V Low level output voltage IOL = 20 μA 4.5 0.1 0.1 0.1 V Low level output voltage IOL = 4 mA 4.5 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 5.5 8 80 160 μA 126 157.5 171.5 ΔICC (1) (2) (1) Additional quiescent device current per input pin SER, A to H 4.5 to inputs held at VCC 5.5 – 2.1 100 CLK and SH/LD 4.5 to inputs held at VCC 5.5 – 2.1 100 μA 234 292.5 318.5 For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. VI = VIH or VIL. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 5 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 5.5 Prerequisite for Switching Characteristics PARAMETER tWL, tWH tWL VCC (V) CLK Pulse Width SH/LD Pulse Width Set-up Time SER to CLK tSU tSU(L) CLK INH to CLK tSU A-H to SH/LD Hold Time SER to CLK or CLK INH tH tH CLK INH to CLK Recovery Time SH/LD to CLK tREC Maximum Clock Pulse Frequency fMAX 25℃ MIN -40℃ to 85℃ MAX MIN -55℃ to 125℃ MAX MIN 2 80 100 120 4.5 16 20 24 6 14 17 20 2 80 100 120 4.5 16 20 24 6 14 17 20 2 80 100 120 4.5 16 20 24 6 14 17 20 2 80 100 120 4.5 16 20 24 6 14 17 20 2 80 100 120 4.5 16 20 24 6 14 17 20 2 35 45 55 4.5 7 9 11 6 6 8 9 2 0 0 0 4.5 0 0 0 6 0 0 0 2 100 125 150 4.5 20 25 30 6 17 21 26 2 6 5 4 4.5 30 24 20 6 35 28 24 MAX UNIT ns ns ns ns ns ns ns ns MHz HCT TYPES 6 tWL, tWH CLK Pulse Width 4.5 18 23 27 ns tWL SH/LD Pulse Width 4.5 20 25 30 ns tSU Set-up Time SER to CLK 4.5 20 25 30 ns tSU(L) CLK INH to CLK 4.5 20 25 30 ns tSU A-H to SH/LD 6 20 25 30 ns tH Hold Time SER to CLK or CLK INH 4.5 7 9 11 ns tS, tH CLK INH to CLK 4.5 0 0 0 ns tREC Recovery Time SH/LD to CLK 4.5 20 25 30 ns fMAX Maximum Clock Pulse Frequency 4.5 27 22 18 MHz Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 5.6 Switching Characteristics Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF PARAMETER VCC(V) -40℃ to 85℃ 25℃ TYP -55℃ to 125℃ UNIT MAX MAX MAX 165 205 250 ns 33 41 50 ns HC TYPES 2 CLK or CLK INH to QH or QH SH/LD to QH or Q H tpd 4.5 13(3) 6 28 35 43 ns 2 175 220 265 ns 35 44 53 ns 30 37 45 ns 150 190 225 ns 30 38 45 ns 6 26 33 38 ns 2 75 95 110 ns 4.5 15 19 22 ns 6 13 16 19 ns 10 10 10 pF 4.5 14(3) 6 2 H to QH or Q H tt Output Transition Times CIN Input Capacitance CPD Power Dissipation Capacitance(1) (2) 4.5 5 12(3) 17 pF HCT TYPES tpd CLK or CLK INH to QH or QH 4.5 17(3) 40 50 60 ns SH/LD to QH or Q H 4.5 17(3) 40 50 60 ns 14(3) 35 44 53 ns 15 19 22 ns 10 10 10 pF H to QH or Q H 4.5 tt Output Transition Times 4.5 CIN Input Capacitance CPD Power Dissipation Capacitance(1) (2) (1) (2) (3) 5 24 pF CPD is used to determine the dynamic power consumption, per package. PD = VCC 2 fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CL = 15 pF and VCC = 5 V. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 7 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. Test Point From Output Under Test CL(1) (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs tw VCC Clock Input VCC Input 50% 50% 50% 0V 0V Figure 6-2. Voltage Waveforms, Standard CMOS Inputs Pulse Duration th tsu VCC Data Input 50% 50% 0V Figure 6-3. Voltage Waveforms, Standard CMOS Inputs Setup and Hold Times VCC Input 50% 90% Input 50% tPLH tPHL tr(1) (1) VOH Output 50% VOL tPHL tPLH (1) VOH Output 50% 0V tf(1) 90% VOH 90% Output 50% (1) 10% 10% 0V (1) VCC 90% 50% 10% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 6-5. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Input Devices VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-4. Voltage Waveforms, Standard CMOS Inputs Setup Propagation Delays 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 tw 3V Clock Input 3V Input 1.3V 1.3V 1.3V 0V 0V tsu Figure 6-6. Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration th 3V Data Input 1.3V 1.3V 0V Figure 6-7. Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times 3V Input 1.3V 1.3V 0V tPLH(1) tPHL(1) VOH Output Waveform 1 50% 50% VOL tPHL(1) tPLH(1) VOH Output Waveform 2 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-8. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 9 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 7 Detailed Description 7.1 Overview The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (QH and Q H) available from the last stage. When the parallel load (SH/LD) input is LOW, parallel data from the A to H inputs are loaded into the register asynchronously. When the SH/LD is HIGH, data enters the register serially at the SER input and shifts one place to the right (A→B→C, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by connecting the QH output to the SER input of the succeeding device. For predictable operation the LOW-to-HIGH transition of CLK INH should only take place while CLK is HIGH. Also, CLK and CLK INH should be LOW before the LOW-to-HIGH transition of SH/LD to prevent shifting the data when SH/LD goes HIGH. 7.2 Functional Block Diagram A B C D E F H G SH/LD 5 Additional Shift Register Stages SER S R S R S R D Q D Q D Q QH Q QH CLK INH CLK 7.3 Device Functional Modes Table 7-1. Truth Table(1) OPERATING MODE Parallel Load Serial Shift Hold (Do Nothing) (1) 10 INPUTS QnREGISTER SHLD CLK INH CLK SER A-H QA L X X X L L L X X X H H H L ↑ l X L H L ↑ h X H H H X X X qA QB - QG OUTPUTS QH QH L-L L H H-H H L qA - qF qG qG qA - qF qG qG qB - qG qH qH H = High voltage level. h = High voltage level one set-up time prior to the low-to-high clock transition. l = Low voltage level one set-up time prior to the low-to-high clock transition. L = Low voltage level. X = Don’t care. ↑ = Transition from low to high level. qn = Lower case letters indicate the state of the reference output clock transition. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 11 CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 www.ti.com SCHS156D – FEBRUARY 1998 – REVISED NOVEMBER 2021 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD54HC165 CD74HC165 CD54HCT165 CD74HCT165 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8685501EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8685501EA CD54HCT165F3A Samples CD54HC165F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8409501EA CD54HC165F3A Samples CD54HCT165F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8685501EA CD54HCT165F3A Samples CD74HC165E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC165E Samples CD74HC165M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC165M Samples CD74HC165M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC165M Samples CD74HC165M96G4 ACTIVE SOIC D 16 2500 TBD Call TI Call TI -55 to 125 CD74HC165ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC165M Samples CD74HC165MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC165M Samples CD74HC165MTE4 ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC165M Samples CD74HCT165E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT165E Samples CD74HCT165M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT165M Samples CD74HCT165M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HCT165M Samples CD74HCT165M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT165M Samples CD74HCT165ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT165M Samples CD74HCT165MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT165M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of