CD54HC4094, CD74HC4094, CD74HCT4094
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus
Register, Three-State
1 Features
2 Description
•
•
The CDx4HC4094 and CD74HCT4094 are 8-stage
serial shift registers having a storage latch associated
with each stage for strobing data from the serial
input to parallel buffered tri-state outputs. The parallel
outputs may be connected directly to common bus
lines. Data is shifted on positive clock transitions. The
data in each shift register stage is transferred to the
storage register when the Strobe input is high. Data in
the storage register appears at the outputs whenever
the Output-Enable signal is high.
•
•
•
•
•
•
Buffered inputs
Separate serial outputs synchronous to both
positive and negative clock edges for cascading
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temp range: −55°C to 125°C
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
logic ICs
HC types
– 2- to 6-V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5- to 5.5-V operation
– Direct LSTTL input logic compatibility,
VIL= 0.8 V (Max), VIH = 2 V (Min)
– CMOS input compatibility, Il ≤ 1μA at VOL, VOH
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
CD54HC4094F3A
CDIP (16)
24.38 mm × 6.92 mm
CD74HC4094M
SOIC (16)
9.90 mm × 3.90 mm
CD74HC4094E
PDIP (16)
19.31 mm × 6.35 mm
CD74HC4094NSR
SO (16)
6.20 mm × 5.30 mm
CD74HC4094PW
TSSOP (16)
5.00 mm × 4.40 mm
CD74HCT4094M
SOIC (16)
9.90 mm × 3.90 mm
CD74HCT4094E
PDIP (16)
19.31 mm × 6.35 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
OE
STR
CP
DATA
D
Q
D
S
D
Q
Q
Q0
Q
Q1
D
S
Q2
Q3
Q4
Q5
Q6
D
Q
D
S
Q
Q7
QS1
D
Q
QS2
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics.................. 6
5.6 Switching Characteristics............................................7
6 Parameter Measurement Information............................ 9
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Device Functional Modes..........................................11
8 Power Supply Recommendations................................12
9 Layout.............................................................................12
9.1 Layout Guidelines..................................................... 12
10 Device and Documentation Support..........................13
10.1 Documentation Support.......................................... 13
10.2 Receiving Notification of Documentation Updates..13
10.3 Support Resources................................................. 13
10.4 Trademarks............................................................. 13
10.5 Electrostatic Discharge Caution..............................13
10.6 Glossary..................................................................13
11 Mechanical, Packaging, and Orderable
Information.................................................................... 13
3 Revision History
Changes from Revision E (December 2010) to Revision F (March 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
4 Pin Configuration and Functions
STROBE
1
16
VCC
DATA
2
OE
CP
Q0
3
15
14
4
13
Q1
5
12
Q5
Q6
Q2
Q3
6
11
Q7
7
8
10
QS2
QS1
GND
9
Q4
J, N, D, NS, or PW package
16-Pin CDIP, PDIP, SOIC, SO, or TSSOP
Top View
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
Submit Document Feedback
3
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
IIK
Input diode current
For VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output diode current
For VO < –0.5 V or VO > VCC + 0.5 V
±20
mA
IO
Output source or sink current per output pin
For VO > –0.5 V or VO < VCC + 0.5 V
±25
mA
±50
mA
150
°C
150
°C
300
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
– 65
Maximum lead temperature (Soldering 10s) (SOIC - lead tips only)
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
5.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage range
VI,
VO
Input or output voltage
HC types
HCT types
NOM
MAX
2
6
4.5
5.5
0
VCC
2V
tt
TA
Input rise and fall time
UNIT
V
V
1000
4.5 V
500
6V
400
Temperature range
–55
125
ns
°C
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
(2)
4
Junction-to-ambient thermal resistance(1)
N (PDIP)
D (SOIC)(2)
NS (SOP)
PW (TSSOP)
PINS
PINS
PINS
PINS
67
73
64
108
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Lead tips only
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
5.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS(2)
PARAMETER
VCC
(V)
25°C
MIN
TYP
–40°C to 85°C
MAX
MIN
MAX
–55°C to 125°C
MIN
MAX
UNIT
HC TYPES
VIH
High-level input voltage
VIL
Low-level input voltage
High-level output voltage
CMOS loads
VOH
High-level output voltage
TTL loads
Low-level output voltage
CMOS loads
VOL
2
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
V
6
4.2
4.2
4.2
V
2
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
V
6
1.8
1.8
1.8
V
IOH = – 20μA
2
1.9
1.9
1.9
V
IOH = – 20μA
4.5
4.4
4.4
4.4
V
IOH = – 20μA
6
5.9
5.9
5.9
V
IOH = – 6mA
4.5
3.98
3.84
3.7
V
6
5.48
5.34
5.2
V
IOH = – 7.8mA
IOL = 20μA
2
0.1
0.1
0.1
V
IOL = 20μA
4.5
0.1
0.1
0.1
V
IOL = 20μA
6
0.1
0.1
0.1
V
Low-level output voltage
TTL loads
IOL = 6mA
4.5
0.26
0.33
0.4
V
IOL = 7.8mA
6
0.26
0.33
0.4
V
II
Input leakage current
VCC or GND
6
±0.1
±1
±1
µA
ICC
Supply current
VCC or GND
6
8
80
160
µA
HCT TYPES
VIH
High-level input voltage
4.5 to
5.5
VIL
Low-level input voltage
4.5 to
5.5
2
2
0.8
2
0.8
V
0.8
V
High-level output voltage
CMOS loads
IOH = – 20μA
4.5
4.4
4.4
4.4
V
High-level output voltage
TTL loads
IOH = – 6mA
4.5
3.98
3.84
3.7
V
Low-level output voltage
CMOS loads
IOL = 20μA
4.5
0.1
0.1
0.1
V
Low-level output voltage
TTL loads
IOL = 6mA
4.5
0.26
0.33
0.4
V
II
Input leakage current
VCC and GND
5.5
±0.1
±1
±1
µA
ICC
Supply Current
VCC and GND
5.5
8
80
160
µA
VOH
VOL
ΔICC (1) (3)
(1)
(2)
(3)
Additional quiescent
device current per input
pin: 1 unit load
D
4.5 to
5.5
40
144
180
196
µA
CP, OE
4.5 to
5.5
150
540
675
735
µA
STR
4.5 to
5.5
100
360
450
490
µA
For dual−supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
VI = VIH or VIL, unless otherwise noted.
Inputs held at VCC – 2.1.
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
Submit Document Feedback
5
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
5.5 Prerequisite for Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
25°C
–40 to 85°C
–55 to 125°C
PARAMETER
VCC (V)
2
80
100
120
CP pulse duration
4.5
16
20
24
6
14
17
20
2
80
100
120
4.5
16
20
24
6
14
17
20
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
HC TYPES
tW
tWH
STR pulse duration
tSU
Data set-up time
tH
Data hold time
tSU
STR set-up time
tH
STR hold time
ƒCL (MAX)
Maximum CP frequency
2
50
65
75
4.5
10
13
15
6
9
11
13
2
3
3
3
4.5
3
3
3
6
3
3
3
2
100
125
150
4.5
20
25
30
6
17
21
26
2
0
0
0
4.5
0
0
0
6
0
0
0
2
6
5
4
4.5
30
24
20
6
35
28
24
ns
ns
ns
ns
ns
ns
MHz
HCT TYPES
6
tW
CP pulse duration
4.5
16
20
24
ns
tWH
STR pulse duration
4.5
16
20
24
ns
tSU
Data set-up time
4.5
10
13
15
ns
tH
Data hold time
4.5
4
4
4
ns
tSU
STR set-up time
4.5
20
25
30
ns
tH
STR hold time
4.5
0
0
0
ns
ƒCL (MAX)
Maximum CP frequency
4.5
30
24
20
MHz
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
5.6 Switching Characteristics
Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF Parameter Measurement Information
PARAMETER
VCC (V)
25°C
MIN
TYP
–40 to 85°C
MAX
MIN
–55 to 125°C
MAX
MIN
MAX
UNIT
HC TYPES
2
tpd
tpd
Propagation delay time
CP to QS1
4.5
STR to Qn
tPZH,
tPZL
Output enable to Qn
tPHZ,
tPLZ
Output disable to Qn
33
38
170
205
27
34
41
23
29
35
195
245
295
39
49
59
6
33
42
50
2
180
225
270
4.5
36
45
54
11(3)
16(3)
6
31
38
46
2
175
220
265
4.5
35
44
53
6
30
37
45
2
125
155
190
4.5
25
31
38
6
21
26
32
2
75
95
110
4.5
15
19
22
6
13
16
19
tTLH,
tTHL
Output transition time
tPHZ,
tPLZ
Output disabling time
5
10(3)
ƒMAX
Maximum CP frequency
5
60(3)
CIN
Input capacitance
Power dissipation
45
26
2
tt
225
38
135
4.5
CP to Qn
190
30
2
6
tpd
150
6
4.5
CP to QS2
12(3)
CPD
(2)
CO
Tri-state output capacitance
5
ns
ns
ns
ns
ns
ns
ns
MHz
10
capacitance(1),
ns
10
10
90(3)
pF
pF
15
15
15
pF
HCT TYPES
Propagation delay time
CP to QS1
4.5
16(3)
39
ns
CP to QS2
4.5
15(3)
36
ns
CP to Qn
4.5
18(3)
43
ns
STR to Qn
4.5
39
ns
tPZH,
tPZL
Output enable to Qn
4.5
35
ns
tPHZ,
tPLZ
Output disable to Qn
4.5
35
ns
tTLH,
tTHL
Output transition time
4.5
15
ns
tPHZ,
tPLZ
Output disabling time
5
14(3)
ns
ƒMAX
Maximum CP frequency
5
60(3)
MHz
CIN
Input capacitance
tPLH,
tPHL
10
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
10
10
pF
Submit Document Feedback
7
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF Parameter Measurement Information
PARAMETER
Power dissipation capacitance(1),
CPD
(2)
CO
Tri-state output capacitance
(1)
(2)
(3)
8
VCC (V)
5
25°C
MIN
TYP
–40 to 85°C
MAX
MIN
–55 to 125°C
MAX
MIN
MAX
110(3)
UNIT
pF
15
15
15
pF
CPD is used to determine the dynamic power consumption, per register.
PD = VCC 2 ƒi (CPD + CL) where ƒi = Input frequency, CL = Output load capacitance, VCC = Supply voltage.
Typical value tested at 5V, CL = 15pF
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
6 Parameter Measurement Information
tPD is the maximum between tPLH and tPHL
tt is the maximum between tTLH and tTHL
Figure 6-1. HC and HCT transition times and
propagation delay times, combination logic
Figure 6-3. HC three-state propagation delay
waveform
Figure 6-2. HCT transition times and tpopationg
delay times, combination logic
Figure 6-4. HCT three-state propagation delay
waveform
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test
circuit is Output RL = 1kΩ to VCC, CL = 50pF.
Figure 6-5. HC and HCT three-state propagation delay test circuit
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
Submit Document Feedback
9
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
7 Detailed Description
7.1 Overview
The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with
each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may
be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift
register stage is transferred to the storage register when the Strobe input is high. Data in the storage register
appears at the outputs whenever the Output-Enable signal is high.
Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial
output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock
rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge,
provides a means for cascading these devices when the clock rise time is slow.
7.2 Functional Block Diagram
OE
STR
CP
DATA
D
Q
D
S
D
Q
Q
Q0
Q
Q1
D
S
Q2
Q3
Q4
Q5
Q6
D
Q
D
S
Q
Q7
QS1
D
10
Submit Document Feedback
Q
QS2
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
7.3 Device Functional Modes
Table 7-1. Truth Table
Inputs(2)
(1)
(2)
Parallel Outputs
Serial Outputs
CP
OE
STR
D
Q0
Qn
QS1 (1)
QS2
↑
L
X
X
Z
Z
Q6
NC
↓
L
X
X
Z
Z
NC
Q7
↑
H
L
X
NC
NC
Q6
NC
↑
H
H
L
L
Qn – 1
Q6
NC
↑
H
H
H
H
Qn – 1
Q6
NC
↓
H
H
H
NC
NC
NC
Q7
At the positive clock edge the information in the seventh register stage is transferred to the eighth
register stage and QS1 output.
H = High voltage level, L = Low voltage level, X = Don't care, NC = No charge, Z = High-impedance
off−state, ↑ = Transition from low-to-high level, ↓ = Transition from high to low.
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
Submit Document Feedback
11
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
12
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
CD54HC4094, CD74HC4094, CD74HCT4094
www.ti.com
SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC4094 CD74HC4094 CD74HCT4094
Submit Document Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CD54HC4094F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC4094F3A
CD74HC4094E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4094E
CD74HC4094M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094M96G3
ACTIVE
SOIC
D
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094M96G4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094NSRE4
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HC4094PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HC4094PWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HC4094PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HCT4094E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4094E
CD74HCT4094EE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4094E
CD74HCT4094M
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4094M
CD74HCT4094M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HCT4094M
CD74HCT4094ME4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4094M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
