CD54HC540, CD74HC540, CD54HC541, CD74HC541, CD74HCT540, CD54HCT541, CD74HCT541
SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
CDx4HC(T)541 High-Speed CMOS Logic Octal Buffer and Line Drivers Three-State
1 Features
2 Description
•
•
•
•
•
•
The ’HC540 and CD74HCT540 are Inverting Octal
Buffers and Line Drivers with Three-State Outputs
and the capability to drive 15 LSTTL loads.
The ’HC541 and ’HCT541 are Noninverting Octal
Buffers and Line Drivers with Three-State Outputs
that can drive 15 LSTTL loads. The Output Enables
(OE1) and (OE2) control the Three-State Outputs. If
either OE1 or OE2 is HIGH the outputs will be in the
high impedance state. For data output OE1 and OE2
both must be LOW.
•
•
•
•
•
•
’HC540, CD74HCT540: inverting
’HC541, ’HCT541: non-inverting
Buffered inputs
Three-state outputs
Bus line driving capability
Typical propagation delay = 9 ns at VCC = 5 V,
CL = 15 pF, TA = 25℃
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: –55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility,
VIL = 0.8 V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
Package Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HC540M
SOIC (20)
12.80 mm × 7.50 mm
CD74HC540E
PDIP (20)
25.40 mm × 6.35 mm
CD54HC540F3A
CDIP (20)
26.92 mm × 6.92 mm
CD74HC541M
SOIC (20)
12.80 mm × 7.50 mm
CD74HC541E
PDIP (20)
25.40 mm × 6.35 mm
CD54HC541F
CDIP (20)
26.92 mm × 6.92 mm
CD74HCT540M
SOIC (20)
12.80 mm × 7.50 mm
CD74HCT540E
PDIP (20)
25.40 mm × 6.35 mm
CD74HCT541M
SOIC (20)
12.80 mm × 7.50 mm
CD74HCT541E
PDIP (20)
25.40 mm × 6.35 mm
CD54HCT541F
CDIP (20)
26.92 mm × 6.92 mm
CD74HCT541PW
TSSOP (20)
6.50 mm × 4.40 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC540, CD74HC540, CD54HC541, CD74HC541, CD74HCT540, CD54HCT541, CD74HCT541
SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Switching Characteristics............................................6
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2022) to Revision E (October 2022)
Page
• Increased RθJA for packages: DW (58 to 109.1); N (69 to 84.6); PW (83 to 131.8).......................................... 4
Changes from Revision C (July 2004) to Revision D (January 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-refrences throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
HC540
J, N, or DW package
20- Pin CDIP, PDIP, or SOIC
Top View
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HC541
J, N, DW, or PW
20-Pin CDIP, PDIP, SOIC, or TSSOP
Top View
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
V
IIK
Input diode current
For VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output diode current
For VO < –0.5 V or VO > VCC + 0.5 V
±20
mA
IO
Drain current, per output
For –0.5 V < VO < VCC + 0.5 V
±35
mA
IO
Output source or sink current per output pin
For VO > –0.5 V or VO < VCC + 0.5 V
±25
mA
Continuous current through VCC or ground current
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature range
150
°C
300
°C
– 65
Lead temperature (Soldering 10s) (SOIC - Lead Tips Only)
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
5.2 Recommended Operating Conditions
TA
Temperature range
VCC
Supply voltage range
VI, VO
Input or output voltage
HC types
HCT types
MIN
MAX
UNIT
–55
125
℃
2
6
4.5
5.5
0
VCC
2V
Input rise and fall time
V
V
1000
4.5 V
500
6V
400
ns
5.3 Thermal Information
THERMAL METRIC
N (PDIP)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
UNIT
109.1
84.6
131.8
°C/W
76
72.5
72.2
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
77.6
65.3
82.8
°C/W
ψJT
Junction-to-top characterization
parameter
51.5
55.3
21.5
°C/W
ψJB
Junction-to-board characterization
parameter
77.1
65.2
82.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
°C/W
(1)
4
(1)
DW (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
5.4 Electrical Characteristics
PARAMETER
TEST
(2)
CONDITIONS
VCC(V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
VIH
VIL
VOH
VOL
High level input
voltage
Low level input
voltage
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
V
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
1.8
1.8
1.8
High level output
voltage
CMOS loads
IOH = – 20 μA
2
1.9
1.9
1.9
IOH = – 20 μA
4.5
4.4
4.4
4.4
IOH = – 20 μA
6
5.9
5.9
5.9
High level output
voltage
TTL loads
IOH = – 6 mA
4.5
3.98
3.84
3.7
IOH = – 7.8 mA
6
5.48
5.34
5.2
Low level output
voltage
CMOS loads
IOL = 20 μA
2
0.1
0.1
0.1
IOL = 20 μA
4.5
0.1
0.1
0.1
IOL = 20 μA
6
0.1
0.1
0.1
Low level output
voltage
TTL loads
IOL = 6 mA
4.5
0.26
0.33
0.4
IOL = 7.8 mA
6
0.26
0.33
0.4
V
V
V
II
Input leakage current
VI = VCC or GND
6
±0.1
±1
±1
μA
ICC
Quiescent device
current
VI = VCC or GND
6
8
80
160
μA
IOZ
Three-state leakage
current
VO = VCC or GND
6
±0.5
±5.0
±10
μA
HCT TYPES
VIH
High level input
voltage
4.5 to
5.5
VIL
Low level input
voltage
4.5 to
5.5
VOH
VOL
High level output
voltage
CMOS loads
VOH = – 20 μA
High level output
voltage
TTL loads
VOH = – 6 mA
4.5
Low level output
voltage
CMOS loads
VOL = 20 μA
4.5
Low level output
voltage
TTL loads
VOL = 6 mA
4.5
2
2
0.8
4.4
2
0.8
4.4
V
0.8
V
4.4
V
3.98
3.84
0.1
3.7
0.1
0.1
V
4.5
0.26
0.33
0.4
II
Input leakage current VI = VCC and GND
5.5
±0.1
±1
±1
μA
ICC
Quiescent device
current
VI = VCC and GND
5.5
8
80
160
μA
IOZ
Three-state leakage
current
VO = VCC or GND
5.5
±0.5
±5.0
±10
μA
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
5.4 Electrical Characteristics (continued)
TEST
(2)
CONDITIONS
VCC(V)
A0 - A7 inputs held
at VCC–2.1
PARAMETER
HCT540
Additional quiescent
device current per
input pin
ΔICC
(1)
HCT541
Additional quiescent
device current per
input pin
(1)
(2)
25℃
MIN
–40℃ to 85℃
MIN
–55℃ to 125℃
MAX
MIN
MAX
UNIT
TYP
MAX
4.5 to
5.5
100
360
450
490
μA
OE2 input held at
VCC–2.1
4.5 to
5.5
100
270
337.5
367.5
μA
OE1 input held at
VCC–2.1
4.5 to
5.5
100
414
517.5
563.5
μA
A0 - A7 inputs held
at VCC–2.1
4.5 to
5.5
100
144
180
196
μA
OE2 input held at
VCC–2.1
4.5 to
5.5
100
270
337.5
367.5
μA
OE1 input held at
VCC–2.1
4.5 to
5.5
100
414
517.5
563.5
μA
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8mA.
VI = VIH or VOL, unless otherwise noted.
5.5 Switching Characteristics
PARAMETER
TEST
VCC (V)
CONDITIONS
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
tPLH,
tPHL
tPLZ,
tPHZ
tPLZ,
tPHZ
tPLZ,
tPHZ
Propagation delay
Data to outputs (540)
CL = 50 pF
Output enable and disable to
outputs (540)
Output enable and disable to
outputs (541)
tTHL,
tTLH
Output transition time
CI
Input capacitance
CO
Three-state output capacitance
110
140
165
4.5
22
28
33
CL = 15 pF
5
CL = 50 pF
6
19
24
28
2
115
145
175
4.5
23
29
35
CL = 50 pF
Data to outputs (541)
2
CL = 15 pF
5
CL = 50 pF
6
20
25
30
2
160
200
240
4.5
32
40
48
CL = 50 pF
CPD
Power dissipation
(540)
CPD
Power dissipation capacitance(1) (2)
(541)
9
CL = 15 pF
5
CL = 50 pF
6
27
34
41
2
160
200
240
4.5
32
40
48
CL = 50 pF
13
ns
ns
ns
ns
ns
5
CL = 50 pF
6
23
29
35
2
60
75
90
4.5
12
15
18
6
10
13
15
10
10
10
10
pF
20
20
20
20
pF
CL = 50 pF
14
ns
CL = 15 pF
CL = 50 pF
capacitance(1) (2)
9
ns
ns
ns
CL = 15 pF
5
50
pF
CL = 15 pF
5
48
pF
CL = 50 pF
4.5
CL = 15 pF
5
HCT TYPES
tPHL,
tPLH
6
Propagation delay
Data to outputs (540)
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24
30
9
36
ns
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
5.5 Switching Characteristics (continued)
PARAMETER
TEST
VCC (V)
CONDITIONS
CL = 50 pF
4.5
CL = 15 pF
5
Output enable and disable to
outputs (540, 541)
CL = 50 pF
4.5
CL = 15 pF
5
tTLH,
tTHL
Output transition time
CL = 50 pF
4.5
CI
Input capacitance
CL = 50 pF
CO
Three-state output capacitance
tPHL,
tPLH
Data to outputs (541)
tPLZ,
tPHZ
CPD
(1)
(2)
Power dissipation
(540, 541)
capacitance(1) (2)
CL = 15 pF
5
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
28
35
42
35
44
53
12
15
18
ns
10
10
10
10
pF
20
20
20
20
pF
11
14
55
ns
ns
pF
CPD is used to determine the dynamic power consumption, per channel.
PD = VCC 2fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
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6 Parameter Measurement Information
tpd is the maximum between tPLH and tPHL
tt is the maximum between tTLH and tTHL
Figure 6-1. HC Transition Times and Propagation
Delay Times, Combination Logic
Figure 6-2. HCT Transition Times and Propagation
Delay Times, combination Logic
Figure 6-3. HC Three-State Propagation Delay
Waveform
Figure 6-4. HCT Three-State Propagation Delay
Waveform
A.
Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50 pF.
Figure 6-5. HC and HCT Three-State Propagation Delay Test Circuit
8
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
7 Detailed Description
7.1 Overview
The ’HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the
capability to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Noninverting Octal Buffers and Line Drivers
with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the
Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data
output OE1 and OE2 both must be LOW.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Truth Table(1)
INPUTS
(1)
OUTPUTS
OE1
OE2
An
540
541
L
L
H
L
H
H
X
X
Z
Z
X
H
X
Z
Z
L
L
L
H
L
H = high voltage level, L = low voltage level, X= don’t care, Z =
high impedance
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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SCHS189E – JANUARY 1998 – REVISED OCTOBER 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD54HC540F3A
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC540F3A
Samples
CD54HC541F
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC541F
Samples
CD54HC541F3A
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC541F3A
Samples
CD54HCT541F
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HCT541F
Samples
CD54HCT541F3A
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HCT541F3A
Samples
CD74HC540E
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC540E
Samples
CD74HC540M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC540M
Samples
CD74HC540M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC540M
Samples
CD74HC541E
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC541E
Samples
CD74HC541EE4
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC541E
Samples
CD74HC541M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC541M
Samples
CD74HC541M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC541M
Samples
CD74HC541M96G4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC541M
Samples
CD74HC541PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ541
Samples
CD74HC541PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ541
Samples
CD74HCT540E
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT540E
Samples
CD74HCT540M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT540M
Samples
CD74HCT540M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT540M
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
14-Oct-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD74HCT541E
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT541E
Samples
CD74HCT541M
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT541M
Samples
CD74HCT541M96
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT541M
Samples
CD74HCT541M96E4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT541M
Samples
CD74HCT541M96G4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT541M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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