CD74HCT7046AEG4

[ /Title (CD74 HC704 6A, CD74 HCT70 46A) /Subject (PhaseLocked Loop CD74HC7046A, CD74HCT7046A Data sheet acquired from Harris Semiconductor SCHS218C Phase-Locked Loop with VCO and Lock Detector February 1998 - Revised October 2003 Features Description • Center Frequency of 18MHz (Typ) at VCC = 5V, Minimum Center Frequency of 12MHz at VCC = 4.5V The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively. • Choice of Two Phase Comparators - Exclusive-OR - Edge-Triggered JK Flip-Flop • Excellent VCO Frequency Linearity • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption • Minimal Frequency Drift • Zero Voltage Offset Due to Op-Amp Buffer The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a secondorder loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. • Operating Power-Supply Voltage Range - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V - Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH TEMP. RANGE (oC) -55 to 125 16 Ld PDIP CD74HC7046AM -55 to 125 16 Ld SOIC CD74HC7046AMT -55 to 125 16 Ld SOIC CD74HC7046AM96 -55 to 125 16 Ld SOIC CD74HCT7046AE -55 to 125 16 Ld PDIP CD74HCT7046AM -55 to 125 16 Ld SOIC CD74HCT7046AMT -55 to 125 16 Ld SOIC CD74HCT7046AM96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Applications • FM Modulation and Demodulation • Frequency Synthesis and Multiplication • Frequency Discrimination • Tone Decoding • Data Synchronization and Conditioning • Voltage-to-Frequency Conversion • Motor-Speed Control • Related Literature - AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE CD74HC7046AE 1 0.1 CD74HC7046A, CD74HCT7046A Pinout Functional Diagram CD74HC7046A, CD74HCT7046A (PDIP, SOIC) TOP VIEW 2 3 COMPIN LD 1 16 VCC 14 PC1OUT 2 15 CLD COMPIN 3 14 SIGIN VCOOUT 4 13 PC2OUT φ 13 SIGIN 12 R2 C1A 6 11 R1 C1B 7 10 DEMOUT 1 PC1OUT CLD PC2OUT LD 6 C1A INH 5 C1B R1 R2 9 VCOIN GND 8 15 VCOIN 7 4 11 12 VCOOUT VCO 10 9 DEMOUT 5 INH C1 7 4 C1A C1B 3 14 SIGIN COMPIN PC1OUT + VREF VCOOUT 6 12 R2 150Ω - R2 2 1.5K VCO LOCK DETECTOR 1 11 R1 15 CLD LOCK DETECTOR CAPACITOR R1 R5 + VCC VCC - DEMOUT 10 LOCK DETECTOR OUTPUT D - Q UP p CP Q RD + 13 PC2OUT R3 C2 n VCC D Q CP Q RD INH VCOIN 5 9 GND DOWN FIGURE 1. LOGIC DIAGRAM 2 CD74HC7046A, CD74HCT7046A Phase Comparator 1 (PC1) Pin Descriptions PIN NO. SYMBOL 1 LD 2 PC1OUT Phase Comparator 1 Output 3 COMPIN Comparator Input 4 VCOOUT VCO Output 5 INH Inhibit Input 6 C1A Capacitor C1 Connection A 7 C1B Capacitor C1 Connection B 8 Gnd Ground (0V) 9 VCOIN 10 DEMOUT 11 R1 Resistor R1 Connection 12 R2 Resistor R2 Connection 13 PC2OUT 14 SIGIN 15 CLD Lock Detector Capacitor Input 16 VCC Positive Supply Voltage This is an Exclusive-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: NAME AND FUNCTION Lock Detector Output (Active High) VDEMOUT = (VCC/π) (φSIGIN - φCOMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Figure 2. The average of VDEM is equal to 1/2 VCC when there is no signal or noise at SIGIN, and with this input the VCO oscillates at the center frequency (fo). Typical waveforms for the PC1 loop locked at fo shown in Figure 3. VCO Input Demodulator Output The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. Phase Comparator 2 Output Signal Input With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock behavior even with very noisy input signals. Typical of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO center frequency. General Description VCO The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and Gnd) or two external resistors R1 and R2 (between R1 and Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required. See logic diagram, Figure 1. Phase Comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control-gating and a three-state output stage. The circuit functions as an up-down counter (Figure 1) where SIGIN causes an up-count and COMPIN a downcount. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is: The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to Gnd; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequency-divider. The VCO output signal has a specified duty factor of 50%. A LOW level at the inhibit input (INH) enables the VCO, while a HIGH level disables the VCO to minimize standby power consumption. VDEMOUT = (VCC/4π) (φSIGN - φCOMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter). The average output voltage from PC2, fed to the VCO via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Figure 4. Typical waveforms for the PC2 loop locked at fo are shown in Figure 5. When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase differences (φDEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”. Phase Comparators The signal input (SIGIN) can be directly coupled to the selfbiasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels, Capacitive coupling is required for signals with smaller swings. When the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n-type and p-type drivers are “OFF” (three-state). If the SIGIN fre- 3 CD74HC7046A, CD74HCT7046A biased and the time constant in the path that charges the lock detector capacitor is T = (150Ω x CLD). quency is lower than the COMPIN frequency, then it is the ntype driver that is held “ON” for most of the cycle. Subsequently, the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in three-state and the VCO input at pin 9 is a high impedance. During the fall time of the pulse the capacitor discharges through the 1.5kΩ and the 150Ω resistors and the channel resistance of the n-device of the NOR gate to ground (T = (1.5kΩ + 150Ω + Rn-channel) x CLD). The waveform preset at the capacitor resembles a sawtooth as shown in Figure 7. The lock detector capacitor value is determined by the VCO center frequency. The typical range of capacitor for a frequency of 10MHz is about 10pF and for a frequency of 100kHz is about 1000pF. The chart in Figure 8 can be used to select the proper lock detector capacitor value. As long as the loop remains locked and tracking, the level of the sawtooth will not go below the switching threshold of the Schmitt-trigger inverter. If the loop breaks lock, the width of the error pulse will be wide enough to allow the sawtooth waveform to go below threshold and a level change at the output of the Schmitt trigger will indicate a loss of lock, as shown in Figure 9. The lock detector capacitor also acts to filter out small glitches that can occur when the loop is either seeking or losing lock. Thus, for PC2, no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p-type and n-type drivers are “OFF” for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIGIN, the VCO adjusts, via PC2, to its lowest frequency. Lock Detector Theory of Operation Detection of a locked condition is accomplished by a NOR gate and an envelope detector as shown in Figure 6. When the PLL is in Lock, the output of the NOR gate is High and the lock detector output (Pin 1) is at a constant high level. As the loop tracks the signal on Pin 14 (signal in), the NOR gate outputs pulses whose widths represent the phase differences between the VCO and the input signal. The time between pulses will be approximately equal to the time constant of the VCO center frequency. During the rise time of the pulse, the diode across the 1.5kΩ resistor is forward Note: When using phase comparator 1, the detector will only indicate a lock condition on the fundamental frequency and not on the harmonics, which PC1 will also lock on. If a detection of lock is needed over the harmonic locking range of PC1, then the lock detector output must be OR-ed with the output of PC1. VCC SIGIN VDEMOUT (AV) COMPIN VCOOUT 1/2 VCC PC1OUT VCC VCOIN 0 GND 0o 90o φDEMOUT 180o FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN - φCOMPIN); φDEMOUT = (φSIGIN - φCOMPIN) FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 1, LOOP LOCKED AT fo 4 CD74HC7046A, CD74HCT7046A VCC SIGIN COMPIN VDEMOUT (AV) VCOOUT 1/2 VCC VCC PC2OUT GND HIGH IMPEDANCE OFF - STATE VCOIN 0 -360o 0o φDEMOUT PCPOUT 360o FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC2OUT = (VCC/π) (φSIGIN - φCOMPIN); φDEMOUT = (φSIGIN - φCOMPIN) FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 2, LOOP LOCKED AT fo 7046 LOCK DETECTOR CIRCUITRY PHASE DIFFERENCE SIGIN UP FF PIN 1 1.5kΩ COMPIN 150Ω LOCK DETECTOR OUTPUT DN FF PIN 15 CLD LOCK DETECTOR CAPACITOR FIGURE 6. CD74HC/HCT7046A LOCK DETECTOR CIRCUIT PIN 1 1.5kΩ 150Ω PIN 15 LOCK DETECTOR OUTPUT CLD LOCK DETECTOR CAPACITOR VCAP VTH FIGURE 7. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN IN LOCK 5 LOCK DETECTOR CAPACITOR VALUE (pF) CD74HC7046A, CD74HCT7046A 10M 1M 100K 10K 1K 100 10 10 100 1K 10K 100K 1M f, VCO CENTER FREQUENCY (HZ) 10M 100M FIGURE 8. LOCK DETECTOR CAPACITOR SELECTION CHART LOSS OF LOCK PIN 1 1.5kΩ 150Ω PIN 15 CLD LOCK DETECTOR CAPACITOR LOCK DETECTOR OUTPUT VCAP VTH FIGURE 9. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN UNLOCKED 6 CD74HC7046A, CD74HCT7046A Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) INH High Level Input Voltage VIH - - INH Low Level Input Voltage VIL VCOOUT High Level Output Voltage CMOS Loads VOH VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES VCO SECTION - VIH or VIL VCOOUT High Level Output Voltage TTL Loads VCOOUT Low Level Output Voltage CMOS Loads VOL VIH or VIL VCOOUT Low Level Output Voltage TTL Loads C1A, C1B Low Level Output Voltage (Test Purposes Only) VOL VIL or VOL - 3 2.1 - - 2.1 - 2.1 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 3 - - 0.9 - 0.9 - 0.9 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 3 2.9 - - 2.9 - 2.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V 4 4.5 - - 0.40 - 0.47 - 0.54 V 5.2 6 - - 0.40 - 0.47 - 0.54 V 7 CD74HC7046A, CD74HCT7046A DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) INH VCOIN Input Leakage Current II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA R1 Range (Note 2) - - - 4.5 3 - - - - - - kΩ R2 Range (Note 2) - - - 4.5 3 - - - - - - kΩ C1 Capacitance Range - - - 3 - - - - - - pF 4.5 40 - No Limit - - - - pF 6 - - - - - - pF PARAMETER VCOIN Operating Voltage Range - Over the range specified for R1 for Linearity See Figure 8, and 35 - 38 (Note 3) MIN TYP MAX MIN MAX MIN MAX UNITS 3 1.1 - 1.9 - - - - V 4.5 1.1 - 3.2 - - - - V 6 1.1 - 4.6 - - - - V PHASE COMPARATOR SECTION SIGIN, COMPIN DC Coupled High-Level Input Voltage VIH SIGIN, COMPIN DC Coupled Low-Level Input Voltage VIL LD, PCnOUT HighLevel Output Voltage CMOS Loads VOH LD, PCnOUT HighLevel Output Voltage TTL Loads VOH LD, PCnOUT LowLevel Output Voltage CMOS Loads VOL LD, PCnOUT LowLevel Output Voltage TTL Loads VOL SIGIN, COMPIN Input Leakage Current II PC2OUT Three-State Off-State Current IOZ SIGIN, COMPIN Input Resistance RI - - VIL or VIH VIL or VIH VIL or VIH VIL or VIH VCC or GND VIL or VIH - - -0.02 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V 2 1.9 - - 1.9 - 1.9 - V 4.5 4.4 - - 4.4 - 4.4 - V 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 2 - - ±3 - ±4 - ±5 µA 3 - - ±7 - ±9 - ±11 µA 4.5 - - ±18 - ±23 - ±29 µA 6 - - ±30 - ±38 - ±45 µA 6 - - ±0.5 - ±5 - ±10 µA - VI at Self-Bias Operation Point: ∆VI = 0.5V, See Figure 8 3 - 800 - - - - - kΩ 4.5 - 250 - - - - - kΩ 6 - 150 - - - - - kΩ 3 10 - 300 - - - - kΩ 4.5 10 - 300 - - - - kΩ 6 10 - 300 - - - - kΩ DEMODULATOR SECTION Resistor Range RS at RS > 300kΩ Leakage Current Can Influence VDEMOUT 8 CD74HC7046A, CD74HCT7046A DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL Offset Voltage VCOIN to VDEM VOFF Dynamic Output Resistance at DEMOUT RO Quiescent Device Current ICC VI (V) IO (mA) VI = VVCOIN = VCC 2 Values taken over RS Range See Figure 15 VDEMOUT = VCC 2 Pins 3, 5 and 14 at VCC Pin 9 at GND, II at Pins 3 and 14 to be excluded VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 3 - ±30 - - - - - mV 4.5 - ±20 - - - - - mV 6 - ±10 - - - - - mV 3 - 25 - - - - - Ω 4.5 - 25 - - - - - Ω 6 - 25 - - - - - Ω 6 - - 8 - 80 - 160 µA HCT TYPES VCO SECTION INH High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V INH Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VCOOUT High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 4 4.5 - - 0.40 - 0.47 - 0.54 V 5.5 - ±0.1 - ±1 - ±1 µA VCOOUT High Level Output Voltage TTL Loads VCOOUT Low Level Output Voltage CMOS Loads VOL VIH or VIL VCOOUT Low Level Output Voltage TTL Loads C1A, C1B Low Level Output Voltage (Test Purposes Only) VOL VIH or VIL INH VCOIN Input Leakage Current II R1 Range (Note 2) - - - 4.5 3 - - - - - - kΩ R2 Range (Note 2) - - - 4.5 3 - - - - - - kΩ C1 Capacitance Range - - - 4.5 40 - No Limit - - - - pF VCOIN Operating Voltage Range - 4.5 1.1 - 3.2 - - - - V 4.5 to 5.5 3.15 - - 3.15 - 3.15 - V Any Voltage Between VCC and GND Over the range specified for R1 for Linearity See Figure 8, and 35 - 38 (Note 3) PHASE COMPARATOR SECTION SIGIN, COMPIN DC Coupled High-Level Input Voltage VIH - - 9 CD74HC7046A, CD74HCT7046A DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) SIGIN, COMPIN DC Coupled Low-Level Input Voltage VIL - - LD, PCnOUT HighLevel Output Voltage CMOS Loads VOH VIL or VIH LD, PCnOUT HighLevel Output Voltage TTL Loads VOH LD, PCnOUT LowLevel Output Voltage CMOS Loads VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 - - 1.35 - 1.35 - 1.35 V - 4.5 4.4 - - 4.4 - 4.4 - V VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V VOL VIL or VIH - 4.5 - - 0.1 - 0.1 - 0.1 V LD, PCnOUT LowLevel Output Voltage TTL Loads VOL VIL or VIH - 4.5 - - 0.26 - 0.33 - 0.4 V SIGIN, COMPIN Input Leakage Current II Any Voltage Between VCC and GND - 5.5 - - ±30 ±45 µA PC2OUT Three-State Off-State Current IOZ VIL or VIH - 5.5 - - ±0.5 ±5 - - ±10 µA SIGIN, COMPIN Input Resistance RI VI at Self-Bias Operation Point: ∆V, 0.5V, See Figure 8 4.5 - 250 - - - - - kΩ at RS > 300kΩ Leakage Current Can Influence VDEMOUT 4.5 10 - 300 - - - - kΩ VI = VVCOIN = VCC 2 Values taken over RS Range See Figure 15 4.5 - ±20 - - - - - mV VDEMOUT = VCC 2 4.5 - 25 - - - - - Ω PARAMETER ±38 DEMODULATOR SECTION Resistor Range Offset Voltage VCOIN to VDEM RS VOFF Dynamic Output Resistance at DEMOUT RO Quiescent Device Current ICC VCC or GND - 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 4) VCC -2.1 (Excluding Pin 5) - 4.5 to 5.5 - 100 360 - 450 - 490 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTES: 2. The value for R1 and R2 in parallel should exceed 2.7kΩ; R1 and R2 values above 300kΩ may contribute to frequency shift due to leakage currents. 3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage. 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. 10 CD74HC7046A, CD74HCT7046A HCT Input Loading Table INPUT UNIT LOADS INH 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns 6 - - 34 - 43 - 51 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 2 - - 280 - 350 - 420 ns 4.5 - - 56 - 70 - 84 ns 6 - - 48 - 60 - 71 ns 2 - - 325 - 405 - 490 ns 4.5 - - 65 - 81 - 98 ns 6 - - 55 - 69 - 83 ns 3 - 11 - - - - - mV 4.5 - 15 - - - - - mV 6 - 33 - - - - - mV 3 - - - Typ 0.11 - - %/oC 4.5 - - - - - %/oC 6 - - - - - %/oC 3 - - - - - - - MHz 4.5 - 24 - - - - - MHz 6 - - - - - - - MHz 3 - - - - - - - MHz 4.5 - 38 - - - - - MHz 6 - - - - - - - MHz 3 7 10 - - - - - MHz 4.5 12 17 - - - - - MHz 6 14 21 - - - - - MHz 3 - - - - - - - % 4.5 - 0.4 - - - - - % 6 - - - - - - - % HC TYPES PHASE COMPARATOR SECTION Propagation Delay SIGIN, COMPIN to PC1OUT Output Transition Time Output Enable Time, SIGIN, COMPIN to PC2OUT Output Disable Time, SIGIN, COMPIN to PC2OUT tPLH, tPHL tTHL, tTLH tPZH, tPZL tPHZ, tPLZ AC Coupled Input Sensitivity (PP) at SIGIN or COMPIN VI(P-P) VCO SECTION Frequency Stability with Temperature Change Maximum Frequency ∆f ∆T fMAX R1 = 100kΩ, R2 = ∞ C1 = 50pF R1 = 3.5kΩ R2 = ∞ C1 = 0pF R1 = 9.1kΩ R2 = ∞ Center Frequency Frequency Linearity fo ∆fVCO C1 = 40pF R1 = 3kΩ R2 = ∞ VCOIN = VCC/2 R1 = 100kΩ R2 = ∞ C1 = 100pF 11 CD74HC7046A, CD74HCT7046A Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns (Continued) SYMBOL Offset Frequency -40oC TO 85oC 25oC -55oC TO 125oC TEST CONDITIONS VCC (V) MIN R2 = 220kΩ C1 = 1nF 3 - - - - - - - kHz 4.5 - 400 - - - - - kHz 6 - - - - - - - kHz 3 - - - - - - - mV/kHz 4.5 - 330 - - - - - mV/kHz 6 - - - - - - - mV/kHz 4.5 - - 45 - 56 - 68 ns TYP MAX MIN MAX MIN MAX UNITS DEMODULATOR SECTION VOUT vs fIN R1 = 100kΩ R2 = ∞ C1 = 100pF R5 = 10kΩ R3 = 100kΩ C2 = 100pF HCT TYPES PHASE COMPARATOR SECTION Propagation Delay tPLH, tPHL SIGIN, COMPIN to PC1OUT Output Transition Time tTHL, tTLH 4.5 - - 15 - 19 - 22 ns Output Enable Time, SIGIN, COMPIN to PC2OUT tPZH, tPZL 4.5 - - 60 - 75 - 90 ns Output Disable Time, SIGIN, COMPIN to PCZOUT tPHZ, tPLZ 4.5 - - 70 - 86 - 105 ns 3 - 11 - - - - - mV 4.5 - 15 - - - - - mV 6 - 33 - - - - - mV AC Coupled Input Sensitivity (P-P) at SIGIN or COMPIN VI(P-P) VCO SECTION Frequency Stability with Temperature Change Maximum Frequency Center Frequency Frequency Linearity Offset Frequency ∆f ∆T R1 = 100kΩ, R2 = ∞ 4.5 - - - Typ 0.11 - - %/oC fMAX C1 = 50pF R1 = 3.5kΩ R2 = ∞ 4.5 - 24 - - - - - MHz C1 = 0pF R1 = 9.1kΩ R2 = ∞ 4.5 - 38 - - - - - MHz fo C1 = 40pF R1 = 3kΩ R2 = ∞ VCOIN = VCC/2 4.5 12 17 - - - - - MHz ∆fVCO R1 = 100kΩ R2 = ∞ C1 = 100pF 4.5 - 0.4 - - - - - % R2 = 220kΩ C1 = 1nF 4.5 - 400 - - - - - kHz R1 = 100kΩ R2 = ∞ C1 = 100pF R5 = 10kΩ R3 = 100kΩ C2 = 100pF 4.5 - 330 - - - - - mV/kHz DEMODULATOR SECTION VOUT vs fIN 12 CD74HC7046A, CD74HCT7046A Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 10. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 11. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC Typical Performance Curves 108 II R1 = 2.2K R1 = 22K R1 = 220K R1 = 2.2M R1 = 11M CENTER FREQUENCY (Hz) 107 ∆VI 106 105 104 103 102 VCOIN = 0.5 VCC VCC = 4.5V R2 = ∞ 10 SELF-BIAS OPERATING POINT 1 1 10 FIGURE 12. TYPICAL INPUT RESISTANCE CURVE AT SIGIN, COMPIN 108 CENTER FREQUENCY (Hz) CENTER FREQUENCY (Hz) 106 105 104 103 102 VCOIN = 0.5 VCC VCC = 6.0V 10 106 1 10 104 106 105 104 103 102 VCOIN = 0.5 VCC VCC = 3.0V R2 = ∞ 1 1 103 105 R1 = 1.5K R1 = 15K R1 = 150K R1 = 1.5M R1 = 7.5M 107 10 R2 = ∞ 102 104 FIGURE 13. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1 R1 = 3K R1 = 30K R1 = 330K R1 = 3M R1 = 15M 107 103 CAPACITANCE, C1 (pF) VI 108 102 105 106 1 10 102 103 104 105 106 CAPACITANCE, C1 (pF) CAPACITANCE, C1 (pF) FIGURE 14. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1 FIGURE 15. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1 13 CD74HC7046A, CD74HCT7046A Typical Performance Curves (Continued) 108 106 CENTER FREQUENCY (Hz) 107 CENTER FREQUENCY (Hz) 108 R1 = 2.2K R1 = 22K R1 = 220K R1 = 2.2M R1 = 11M 105 104 103 102 VCOIN = 0.5 VCC VCC = 4.5V 10 R2 = ∞ 102 10 106 105 104 103 102 VCOIN = 0.5 VCC VCC = 5.5V R2 = ∞ 10 1 1 R1 = 3K R1 = 30K R1 = 300K R1 = 3M R1 = 15M 107 103 104 105 1 106 1 102 10 CAPACITANCE, C1 (pF) 105 106 FIGURE 17. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1 90 140 C1 = 50pF R1 = 1.5M R2 = ∞ VCC = 6V 100 VCC = 4.5V 80 VCC = 3V 60 C1 = 0.1µF R1 = 1.5M R2 = ∞ 80 VCO FREQUENCY (Hz) 120 VCO FREQUENCY (kHz) 104 CAPACITANCE, C1 (pF) FIGURE 16. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1 40 VCC = 6V 70 VCC = 4.5V 60 50 VCC = 3V 40 30 20 10 20 0 1 2 3 4 5 0 6 1 2 VCOIN (V) 3 4 5 6 VCOIN (V) FIGURE 18. HC7046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 19. HC7046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 1.5MΩ, C1 = 0.1µF) 18 800 C1 = 0.1µF R1 = 150K R2 = ∞ VCC = 6V 600 VCC = 4.5V 500 400 VCC = 3V 300 200 VCC = 6V C1 = 0.1µF R1 = 5.6k R2 = ∞ 16 VCO FREQUENCY (kHz) 700 VCO FREQUENCY (Hz) 103 VCC = 4.5V 14 VCC = 3V 12 10 8 6 4 100 2 0 1 2 3 4 5 6 0 1 2 3 4 5 6 VCOIN (V) VCOIN (V) FIGURE 20. HC7046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 150kΩ, C1 = 0.1µF) FIGURE 21. HC7046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 5.6kΩ, C1 = 0.1µF) 14 CD74HC7046A, CD74HCT7046A Typical Performance Curves (Continued) 24 1400 VCO FREQUENCY (kHz) 1000 VCO FREQUENCY (MHz) C1 = 50pF R1 = 150K R2 = ∞ 1200 VCC = 4.5V 800 VCC = 3V 600 VCC = 6V C1 = 50pF R1 = 5.6K R2 = ∞ VCC = 6V 20 VCC = 4.5V 16 12 VCC = 3V 8 400 4 200 0 1 2 3 4 5 0 6 1 2 20 R1 = 1.5M VCO FREQUENCY CHANGE, ∆f (%) VCO FREQUENCY CHANGE, ∆f (%) 24 16 12 R1 = 150K 8 4 0 R1 = 3K -4 -8 -12 -16 -75 -50 -25 0 25 50 5 6 FIGURE 23. HC7046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 5.6kΩ, C1 = 50pF) FIGURE 22. HC7046A TYPICAL VCO FREQUENCY vs VCOIN (R1 = 150kΩ, C1 = 0.1µF) VCOIN = 0.5 VCC C1 = 50pF, VCC = 3V R2 = ∞ 4 VCOIN (V) VCOIN (V) 20 3 75 100 125 16 R1 = 2.2M 12 R1 = 220K 8 4 0 R1 = 2.2K -4 -8 -12 -75 150 VCOIN = 0.5 VCC C1 = 50pF, VCC = 4.5V R2 = ∞ -50 -25 0 25 50 75 100 125 150 AMBIENT TEMPERATURE, TA (oC) AMBIENT TEMPERATURE, TA (oC) FIGURE 24. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 (VCC = 3V) FIGURE 25. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 15 CD74HC7046A, CD74HCT7046A Typical Performance Curves 12 R1 = 3M 8 VCO FREQUENCY CHANGE, ∆f (%) VCO FREQUENCY CHANGE, ∆f (%) 20 VCOIN = 0.5 VCC C1 = 50pF, VCC = 6.0V R2 = ∞ 16 (Continued) R1 = 300K 4 0 -4 R1 = 3K -8 -12 -75 -50 -25 0 25 50 75 100 125 VCOIN = 0.5 VCC C1 = 50pF, VCC = 5.5V R2 = ∞ 16 12 8 R1 = 300K 4 0 R1 = 3K -4 -8 -12 -75 150 -50 -25 AMBIENT TEMPERATURE, TA (oC) OFFSET FREQUENCY (Hz) VCO FREQUENCY CHANGE, ∆f (%) 4 0 -4 R1 = 2.2K -8 106 R2 = 22K 104 103 R2 = 220K 102 R2 = 2.2M VCOIN = 0.5 VCC VCC = 4.5V 25 50 75 100 125 1 150 1 10 107 107 OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) 108 R2 = 1.5K 105 104 R2 = 15K 103 R2 = 150K 102 R2 = 1.5M VCOIN = GND VCC = 3V 1 10 104 105 106 R2 = 2.2K 105 104 R2 = 22K 103 R2 = 220K 102 R2 = 2.2M VCOIN = GND VCC = 4.5V 1 103 104 106 10 R2 = 7.5M 102 103 FIGURE 29. HC7046A OFFSET FREQUENCY vs R2, C1 108 106 102 R2 = 11M CAPACITANCE, C1 (pF) FIGURE 28. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 1 150 R2 = 2.2K AMBIENT TEMPERATURE, TA (oC) 10 125 105 10 0 100 107 R1 = 220K -25 75 R1 = 2.2M 8 -50 50 FIGURE 27. HCT7046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 12 -12 -75 25 108 VCOIN = 0.5 VCC C1 = 50pF, VCC = 4.5V R2 = ∞ 16 0 AMBIENT TEMPERATURE, TA (oC) FIGURE 26. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs AMBIENT TEMPERATURE AS A FUNCTION OF R1 20 R1 = 3M 105 106 1 CAPACITANCE, C1 (pF) 10 R2 = 11M 102 103 104 105 106 CAPACITANCE, C1 (pF) FIGURE 30. HC7046A OFFSET FREQUENCY vs R2, C1 FIGURE 31. HCT7046A OFFSET FREQUENCY vs R2, C1 16 CD74HC7046A, CD74HCT7046A Typical Performance Curves (Continued) 108 107 106 R2 = 3K 105 fMAX /fMIN OFFSET FREQUENCY (Hz) VCOIN = VCC - 0.9V FOR fMAX VCOIN = 0V FOR fMIN VCC = 3V, 4.5V, 6V 102 R2 = 30K 104 R2 = 300K 103 10 R2 = 3M 102 VCOIN = GND HC - VCC = 6V HCT - VCC = 5.5V 10 R2 = 15M 1 1 102 10 103 104 105 1 10-2 106 10-1 CAPACITANCE, C1 (pF) FIGURE 32. HC7046A AND HCT7046A OFFSET FREQUENCY vs R2, C1 102 1 R2/R1 10 102 FIGURE 33. HC7046A fMIN/fMAX vs R2/R1 VCOIN = VCC - 0.9V FOR fMAX VCOIN = 0V FOR fMIN VCC = 4.5V TO 5.5V fMAX /fMIN f f2 f0 10 ∆V = 0.5V OVER THE VCC RANGE: FOR VCO LINEARITY f’o = f1 + f2 2 f’o - fo x 100% LINEARITY = f’ f0’ f1 o ∆V 1 10-2 10-1 1 R2/R1 10 MIN 102 FIGURE 34. HCT7046A fMAX/fMIN vs R2/R1 6 VCOIN = 2.25V ± 0.45V 0 -2 0 -6 -6 1M -8 1K 10M FIGURE 36. HC7046A VCO LINEARITY vs R1 VCOIN = 1.50V ± 0.3V -2 -4 100K R1 (OHMS) VCOIN = 1.50V ± 0.4V 2 -4 10K C1 = 50pF VCC = 3V R2 = ∞ 4 VCOIN = 2.25V ± 1V 2 -8 1K MAX VVCOIN 8 C1 = 50pF VCC = 4.5V R2 = ∞ LINEARITY (%) LINEARITY (%) 4 1/2VCC FIGURE 35. DEFINITION OF VCO FREQUENCY LINEARITY 8 6 ∆V 10K 100K R1 (OHMS) 1M FIGURE 37. HC7046A VCO LINEARITY vs R1 17 10M CD74HC7046A, CD74HCT7046A Typical Performance Curves (Continued) 8 8 VCC = 5.5V, 6 VCOIN = 2.75V ±1.3V VCC = 4.5V, 4 VCOIN = 2.25V ±1.0V C1 = 50pF VCC = 6V R2 = ∞ 6 VCOIN = 3V ± 1.5V LINEARITY (%) LINEARITY (%) 4 2 0 -2 2 0 -2 VCC = 5.5V, VCOIN = 2.75V ±0.55V VCC = 4.5V, VCOIN = 2.25V ±0.45V -4 -4 VCOIN = 3V ± 0.6V -6 -6 -8 1K 10K 100K R1 (OHMS) 1M -8 1K 10M 104 VCOIN = 0.5 VCC 103 VCC = 6V 102 VCC = 3V VCC = 4.5V 10 1 1K 10K 100K 100K R1 (OHMS) 1M VCOIN = 0.5 VCC R1 = R2 = OPEN 103 VCC = 6V 102 VCC = 3V 10 1 1K 10K VCC = 6V C1 = 50pF VCC = 6V C1 = 1µF VCC = 4.5V C1 = 50pF 104 VCC = 3V C1 = 1µF 103 VCC = 3V C1 = 50pF VCC = 4.5V C1 = 1µF 102 1K VCC = 6V C1 = 50pF VCOIN = 0V (AT fMIN) R1 = RS = ∞ CL = 50pF 105 VCC = 4.5V C1 = 50pF 104 VCC = 4.5V C1 = 1µF VCC = 6V C1 = 1µF 103 102 1K 10K 1M FIGURE 41. HCT7046A DEMODULATOR POWER DISSIPATION vs RS (TYP) (VCC = 3V, 4.5V, 6V) VCO POWER DISSIPATION, PD (µW) VCO POWER DISSIPATION, PD (µW) 100K 106 105 VCC = 4.5V RS (OHMS) FIGURE 40. HC7046A DEMODULATOR POWER DISSIPATION vs RS (TYP) VCOIN = 0.5VCC R2 = RS = OPEN CL = 50pF 10M 104 RS (OHMS) 106 1M FIGURE 39. HCT7046A VCO LINEARITY vs R1 DEMODULATOR POWER DISSIPATION, PD (µW) DEMODULATOR POWER DISSIPATION, PD (µW) FIGURE 38. HC7046A VCO LINEARITY vs R1 10K C1 = 50pF R2 = OPEN 100K 1M 10K 100K R2 (OHMS) R1 (OHMS) FIGURE 42. HC7046A VCO POWER DISSIPATION vs R1 (C1 = 50pF, 1µF) FIGURE 43. HCT7046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1µF) 18 1M CD74HC7046A, CD74HCT7046A Typical Performance Curves VCC = 5.5V C1 = 50pF 105 106 VCOIN = 0.5V R2 = RS = ∞ VCO POWER DISSIPATION, PD (µW) VCO POWER DISSIPATION, PD (µW) 106 (Continued) VCC = 4.5V C1 = 50pF 104 VCC = 5.5V C1 = 1µF 103 VCC = 4.5V C1 = 1µF 102 1K 10K 100K VCC = 6V C1 = 50pF 105 VCC = 4.5V C1 = 50pF VCC = 6V C1 = 1µF 104 VCC = 3V C1 = 1µF VCC = 3V C1 = 50pF 103 VCC = 4.5V C1 = 1µF 102 1M 1K R1 (OHMS) VCOIN = 0V (AT fMIN) R1 = RS = ∞ CL = 50pF 10K 100K 1M R2 (OHMS) FIGURE 44. HCT7046A VCO POWER DISSIPATION vs R1 (C1 = 50pF, 1µF) FIGURE 45. HC7046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1µF) 19 CD74HC7046A, CD74HCT7046A References should be made to Figures 13 through 23 and Figures 36 through 41 as indicated in the table. HC/HCT7046A CPD CHIP SECTION HC HCT UNIT Comparator 1 48 50 pF Comparator 2 39 48 pF VCO 61 53 pF Values of the selected components should be within the following ranges: R1 Application Information > 3kΩ; R2 > 3kΩ; R1 || R2 parallel value > 2.7kΩ; C1 greater than 40pF This information is a guide for the approximation of values of external components to be used with the CD74HC7046A and CD74HCT7046A in a phase-lock-loop system. SUBJECT VCO Frequency Without Extra Offset (R2 = ∞) PHASE COMPARATOR PC1 or PC2 DESIGN CONSIDERATIONS VCO Frequency Characteristic The characteristics of the VCO operation are shown in Figures 13 - 23. fMAX fVCO fo 2fL fMIN MIN 1/2 VCC VVCOIN MAX FIGURE 46. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE PC1 Selection of R1 and C1 Given fo, determine the values of R1 and C1 using Figures 13 - 17. PC2 Given fMAX calculate fo as fMAX/2 and determine the values of R1 and C1 using Figures 13 - 17. To obtain 2fL: 2fL ≈ 2(∆VCOIN) where 0.9V < VCOIN < VCC - 0.9V is the range of ∆VCOIN R1C1 VCO Frequency with Extra Offset (R2 > 3kΩ) PC1 or PC2 VCO Frequency Characteristic The characteristics of the VCO operation are shown in Figures 29 - 32. fMAX fVCO 2fL fo fMIN MIN 1/2 VCC VVCOIN MAX FIGURE 47. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE PC1 or PC2 Selection of R1, R2 and C1 Given fo and fL, offset frequency, fMIN, may be calculated from fMIN ≈ fo - 1.6 fL. Obtain the values of C1 and R2 by using Figures 29 - 32. Calculate the values of R1 from Figures 33 - 34. 20 PHASE COMPARATOR SUBJECT DESIGN CONSIDERATIONS PLL Conditions with No Signal at the SIGIN Input PC1 VCO adjusts to fo with φDEMOUT = 90o and VVCOIN = 1/2 VCC (see Figure 2) PC2 VCO adjusts to fMIN with φDEMOUT = -360o and VVCOIN = 0V (see Figure 4) PLL Frequency Capture Range PC1 or PC2 Loop Filter Component Selection |F(jω)| R3 INPUT C2 -1/τ OUTPUT ω (A) τ1 = R3 x C2 (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM 1/2 (1/π) (2πfL/τ1.) A small capture range (2fc) is obtained if τ > 2fc ≈ FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET R3 |F(jω)| R4 INPUT m= R4 R3 + R4 OUTPUT m C2 (A) τ2 = R4 x C2; τ3 = (R3 + R4) x C2 1/τ3 1/τ2 ω (B) AMPLITUDE CHARACTERISTIC -1/τ2 -1/τ3 (C) POLE-ZERO DIAGRAM FIGURE 49. SIMPLE LOOP FILTER FOR PLL WITH OFFSET PLL Locks on Harmonics at Center Frequency PC1 Yes PC2 No Noise Rejection at Signal Input PC1 High PC2 Low AC Ripple Content when PLL is Locked PC1 fr = 2fi, large ripple content at φDEMOUT = 90o PC2 fr = fi, small ripple content at φDEMOUT = 0o Lock Detector Circuit The lock detector feature is very useful in data synchronization, motor speed control, and demodulation. By adjusting the value of the lock detector capacitor so that the lock output will change slightly before actually losing lock, the designer can create an “early warning” indication allowing corrective measures to be implemented. The reverse is also true, especially with motor speed controls, generators, and clutches that must be set up before actual lock occurs or disconnected during loss of lock. When using phase comparator 1, the detector will only indicate a lock condition on the fundamental frequency and not on the harmonics, which PC1 will lock on. 21 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD74HC7046AE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC7046AE Samples CD74HC7046AM ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC7046AM Samples CD74HC7046AM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC7046AM Samples CD74HC7046AMT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC7046AM Samples CD74HCT7046AE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT7046AE Samples CD74HCT7046AEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT7046AE Samples CD74HCT7046AM ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT7046AM Samples CD74HCT7046AM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT7046AM Samples CD74HCT7046AMT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT7046AM Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of