CD74HCT74E

CD74HC74, CD54HC74 SCHS124E – JANUARY 1998 – REVISED MAY 2021 CDx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features 3 Description • • • The CDx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each. • • Buffered inputs Wide operating voltage range: 2 V to 6 V Wide operating temperature range: -55°C to +125°C Supports fanout up to 10 LSTTL loads Significant power reduction compared to LSTTL logic ICs Device Information(1) PART NUMBER 2 Applications • • Convert a momentary switch to a toggle switch Divide a clock signal by 2 or 4 xCLK PACKAGE BODY SIZE (NOM) CD74HC74M SOIC (14) 8.70 mm × 3.90 mm CD74HC74E PDIP (14) 19.30 mm × 6.40 mm CD54HC74F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. C C xPRE C xQ C C C xD C C C xQ C xCLR Functional block diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 Recommended Operating Conditions.........................4 6.3 Thermal Information....................................................4 6.4 Electrical Characteristics.............................................5 6.5 Timing Requirements.................................................. 5 6.6 Switching Characteristics............................................6 6.7 Operating Characteristics........................................... 6 6.8 Typical Characteristics................................................ 6 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes..........................................10 9 Application and Implementation.................................. 11 9.1 Application Information..............................................11 9.2 Typical Application.................................................... 11 10 Power Supply Recommendations..............................14 11 Layout........................................................................... 15 11.1 Layout Guidelines................................................... 15 11.2 Layout Example...................................................... 15 12 Device and Documentation Support..........................16 12.1 Documentation Support.......................................... 16 12.2 Related Links.......................................................... 16 12.3 Support Resources................................................. 16 12.4 Trademarks............................................................. 16 12.5 Electrostatic Discharge Caution..............................16 12.6 Glossary..................................................................16 13 Mechanical, Packaging, and Orderable Information.................................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2003) to Revision E (June 2020) Page • Updated to new data sheet standards................................................................................................................ 1 • Moved the HCT devices to a standalone data sheet (SCHS409) ......................................................................1 • RθJA increased for the D package from 86 to 133.6 ℃/W and decreased for the N package from 80 to 62.2 ℃/W ...........................................................................................................................................................4 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 5 Pin Configuration and Functions 1CLR 1 14 VCC 1D 2 13 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 1Q 5 10 1Q 6 9 2Q GND 7 8 2Q 2PRE D, N, or J Package 14-Pin SOIC, PDIP, or CDIP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. 1 CLR 1 Input Channel 1, Clear Input, Active Low 1D 2 Input Channel 1, Data Input 1CLK 3 Input Channel 1, Positive edge triggered clock input 1 PRE 4 Input Channel 1, Preset Input, Active Low 1Q 5 Output Channel 1, Output 1Q 6 Output Channel 1, Inverted Output GND 7 — 2Q 8 Output Channel 2, Inverted Output 2Q 9 Output Channel 2, Output 2 PRE 10 Input Channel 2, Preset Input, Active Low 2CLK 11 Input Channel 2, Positive edge triggered clock input 2D 12 Input Channel 2, Data Input 2 CLR 13 Input Channel 2, Clear Input, Active Low VCC 14 — Ground Positive Supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 3 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input clamp current(2) VI < –0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output clamp current(2) VO < –0.5 V or VO > VCC + 0.5 V ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA Plastic package 150 Hermetic package or die 175 SOIC - lead tips only 300 °C 150 °C Continuous current through VCC or GND Junction temperature(3) TJ Lead temperature (soldering 10s) Tstg (1) (2) (3) Storage temperature –65 V °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Guaranteed by design. 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VIH High-level input voltage MIN NOM MAX 2 5 6 VCC = 2 V VCC = 4.5 V V 4.2 VCC = 2 V 0.5 VCC = 4.5 V Low-level input voltage V 1.5 3.15 VCC = 6 V VIL UNIT 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V tt Input transition time TA Operating free-air temperature VCC = 2 V 1000 VCC = 4.5 V 500 VCC = 6 V ns 400 –55 125 °C 6.3 Thermal Information CD74HC74 THERMAL METRIC(1) 4 N (PDIP) D (SOIC) UNIT 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 62.2 133.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.9 89.0 °C/W RθJB Junction-to-board thermal resistance 41.9 89.5 °C/W ΨJT Junction-to-top characterization parameter 29.5 45.5 °C/W ΨJB Junction-to-board characterization parameter 41.7 89.1 °C/W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 CD74HC74 THERMAL METRIC(1) RθJC(bot) (1) N (PDIP) D (SOIC) 14 PINS 14 PINS N/A N/A Junction-to-case (bottom) thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.4 Electrical Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) PARAMETER TEST CONDITIONS VCC 25°C MIN IOH = –20 µA VOH High-level output voltage VI = VIH or IOH = –4 VIL mA IOL = 20 µA Low-level output VI = VIH or voltage VIL TYP MAX MIN TYP –55°C to 125°C MAX MIN 2V 1.9 1.9 1.9 4.5 V 4.4 4.4 4.4 6V 5.9 5.9 5.9 4.5 V 3.98 3.84 3.7 6V 5.48 5.34 5.2 TYP UNIT MAX V IOH = –5.2 mA VOL –40°C to 85°C 2V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 0.1 0.1 0.1 IOL = 4 mA 4.5 V 6V 0.26 0.33 0.4 IOL = 5.2 mA 6V 0.26 0.33 0.4 V II Input leakage current VI = VCC or 0 6V ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or IO = 0 0 6V 4 40 80 µA Ci Input capacitance 5V 10 10 10 pF 6.5 Timing Requirements over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) VCC 25°C MIN tsu th trem Setup time Data to CP Hold time Removal time R, S, to CP TYP –40°C to 85°C MAX MIN TYP –55°C to 125°C MAX MIN 2V 60 75 90 4.5 V 12 15 18 6V 10 13 15 2V 3 3 3 4.5 V 3 3 3 6V 3 3 3 2V 30 40 45 4.5 V 6 8 9 6V 5 7 8 TYP UNIT MAX ns ns ns Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 5 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). Operating free-air temperature (TA) VCC 25°C MIN R, S tw Pulse width CP CP frequency TYP MAX MIN TYP UNIT –55°C to 125°C MAX MIN 2V 80 100 120 4.5 V 16 20 24 6V 14 17 20 2V 80 100 120 4.5 V 16 20 24 6V 14 17 20 2V fmax –40°C to 85°C 6 5 4 4.5 V 30 25 20 6V 35 29 23 TYP MAX ns MHz 6.6 Switching Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER FROM TO Operating free-air temperature (TA) TEST CONDITIO NS VCC 25°C –40°C to 85°C –55°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX 175 220 265 4.5 V 35 44 53 6V 30 37 45 200 250 300 4.5 V 40 50 60 6V 34 43 51 2V 75 95 110 4.5 V 15 19 22 6V 13 16 19 2V CP tpd Q, Q CL = 50 pF CL = 15 pF Propagation delay 14 2V R, S Q, Q CL = 50 pF CL = 15 pF tt 5V Transition-time Y CL = 50 pF 5V UNIT ns 17 ns 6.7 Operating Characteristics over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load per gate VCC 2 V to 6 V MIN TYP 25 MAX UNIT pF 6.8 Typical Characteristics TA = 25°C 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 SCHS124E – JANUARY 1998 – REVISED MAY 2021 7 0.3 6 0.25 VOL Output Low Voltage (V) VOH Output High Voltage (V) www.ti.com 5 4 3 2 2-V 4.5-V 6-V 1 0 2-V 4.5-V 6-V 0.2 0.15 0.1 0.05 0 0 1 2 3 4 IOH Output High Current (mA) 5 6 Figure 6-1. Typical output voltage in the high state (VOH) 0 1 2 3 4 IOL Output Low Current (mA) 5 6 Figure 6-2. Typical output voltage in the high state (VOL) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 7 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 7 Parameter Measurement Information • • Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. The outputs are measured one at a time, with one input transition per measurement. Test Point 90% VCC 90% Input 10% 10% tr(1) From Output Under Test CL(1) 0V tf(1) 90% VOH 90% Output 10% A. 10% tr(1) CL= 50 pF and includes probe and jig capacitance. A. Figure 7-1. Load Circuit tt is the greater of tr and tf. tw VCC 50% Input 0V tsu 50% 50% 50% 0V th Figure 7-4. Voltage Waveforms Pulse Width VCC Data Input VOL Figure 7-2. Voltage Waveforms Transition Times VCC Clock Input tf(1) 50% 0V Figure 7-3. Voltage Waveforms Setup and Hold Times VCC Input 50% 50% 0V tPLH (1) tPHL (1) VOH Output 50% 50% VOL tPLH(1) tPHL(1) VOH Output 50% 50% VOL A. The maximum between tPLH and tPHL is used for tpd. Figure 7-5. Voltage Waveforms Propagation Delays 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 8 Detailed Description 8.1 Overview The CDx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each. 8.2 Functional Block Diagram xCLK C C xPRE C xQ C C C xD C C C xQ C xCLR 8.3 Feature Description 8.3.1 Balanced CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined in the Section 6.1 must be followed at all times. The CD74HC74 can drive a load with a total capacitance less than or equal to the maximum load listed in the Section 6.6 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to limit output current to the values given in the Section 6.1. 8.3.2 Standard CMOS Inputs Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the Section 6.4. The worst case resistance is calculated with the maximum input voltage, given in the Section 6.1, and the maximum input leakage current, given in the Section 6.4, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Section 6.2 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 9 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Section 6.1 table can cause damage to the device. The recommended input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. VCC Device +IIK +IOK Logic Input Output -IIK -IOK GND Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes Table 8-1. Function Table INPUTS (1) 10 OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information Toggle switches are typically large, mechanically complex and relatively expensive. It is desirable to use a momentary switch instead because they are small, mechanically simple and low cost. Some systems require a toggle switch's functionality but are space or cost constrained and must use a momentary switch instead. If the data input (D) of the D-type flip-flop is tied to the inverted output ( Q), then each clock pulse will cause the value at the output (Q) to toggle. The momentary switch can be debounced and connected through a Schmitt-trigger buffer to the clock input (CLK) to toggle the output. This application also utilizes a power-on reset circuit to ensure that the output always starts in the LOW state when power is applied. 9.2 Typical Application VCC R1 R2 C1 VCC VCC R3 PRE D CLK Q CLR Q Output C2 Figure 9-1. Typical application schematic 9.2.1 Design Requirements 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Section 6.2. The supply voltage sets the device's electrical characteristics as described in the Section 6.4. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the CD74HC74 plus the maximum supply current, ICC, listed in the Section 6.4. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Section 6.1. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 11 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 CAUTION The maximum junction temperature, TJ(max) listed in the Section 6.1, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are provided to prevent damage to the device. 9.2.1.2 Input Considerations Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the CD74HC74, as specified in the Section 6.4, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. The CD74HC74 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Section 6.2. Refer to the Section 8.3 for additional information regarding the inputs for this device. 9.2.1.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Section 6.4. Similarly, the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Section 6.4. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Section 8.3 for additional information regarding the outputs for this device. 9.2.1.4 Timing Considerations The CD74HC74 is a clocked device. As such, it requires special timing considerations to ensure normal operation. Primary timing factors to consider: • • • • Maximum clock frequency: the maximum operating clock frequency defined in Section 6.5 is the maximum frequency at which the device is guaranteed to function. This value refers specifically to the triggering waveform, measuring from one trigger level to the next. Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as defined in the Section 6.5. Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined in the Section 6.5. Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event, as defined in the Section 6.5. 9.2.2 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11. 2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC74 to the receiving device. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation Voltage (2 V/div) Voltage (2 V/div) 9.2.3 Application Curves Vout Vin Vout Vin Time (200 ms/div) Time (100 Ps/div) D001 Figure 9-2. Waveform for non-debounced switch. D002 Figure 9-3. Waveform for debounced switch. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 13 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Section 6.2. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F Unused input tied to GND Avoid 90° corners for signal lines Bypass capacitor placed close to the device 1CLR 1 14 VCC Unused inputs tied to VCC 1D 2 13 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 1Q 5 10 2PRE 1Q 6 9 2Q GND 7 8 2Q Unused output left floating Figure 11-1. Example layout for the CD74HC74 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 15 CD74HC74, CD54HC74 www.ti.com SCHS124E – JANUARY 1998 – REVISED MAY 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • HCMOS Design Considerations • CMOS Power Consumption and CPD Calculation • Designing with Logic 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC74 CD54HC74 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD54HC74F ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC74F Samples CD54HC74F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8405601CA CD54HC74F3A Samples CD74HC74E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC74E Samples CD74HC74EE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC74E Samples CD74HC74M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC74M Samples CD74HC74M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC74M Samples CD74HC74MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC74M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of