CDC2509BPWG4


      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps Jitter (peak − peak) at 66 MHz to 100 MHz Is ±80 ps Jitter (cycle − cycle) at 66 MHz to 100 MHz Is |100 ps| Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V PW PACKAGE (TOP VIEW) AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN description The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. They are specifically designed for use with synchronous DRAMs. The CDC2509B operates at 3.3-V VCC. They also provide integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509B does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2509B requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001 − 2004, Texas Instruments Incorporated 
  !" # $%&" !#  '%()$!" *!"& *%$"# $ " #'&$$!"# '& "+& "&#  &,!# #"%&"# #"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*& "&#"/  !)) '!!&"&# POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 description (continued) The CDC2509B is characterized for operation from 0°C to 70°C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039). FUNCTION TABLE INPUTS OUTPUTS CLK 1Y (0:4) 2Y (0:3) 1G 2G FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H functional block diagram 1G 11 3 4 5 8 9 2G 20 24 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ PLL FBIN AVCC 13 23 AVAILABLE OPTIONS 2 1Y1 1Y2 1Y3 1Y4 14 21 CLK 1Y0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 16 12 2Y0 2Y1 2Y2 2Y3 FBOUT 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 PACKAGE TA SMALL OUTLINE (PW) 0°C to 70°C CDC2509BPWR Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDC2509B and the CDC2510B clock drivers. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 1G 11 I Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. 2G 14 I Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor. 1Y (0:4) 3, 4, 5, 8, 9 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output has an integrated 25-Ω series-damping resistor. 2Y (0:3) 16, 17, 20, 21 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output has an integrated 25-Ω series-damping resistor. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC GND 2, 10, 15, 22 Power Power supply 6, 7, 18, 19 Ground Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range: AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. AVCC must not exceed VCC. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 5) MIN MAX Supply voltage, VCC, AVCC 3 3.6 High-level input voltage, VIH 2 Low-level input voltage, VIL 0 High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA 0 NOTE 5: Unused inputs must be held high or low to prevent them from floating. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.8 Input voltage, VI UNIT V VCC −12 mA V 12 mA 70 °C 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II = −18 mA IOH = −100 µA VOH IOH = −12 mA IOH = − 6 mA VOL II ICC‡ ∆ICC Ci Co VCC, AVCC 3V MIN MIN to MAX 3V VCC−0.2 2.1 3V 2.4 IOL = 100 µA IOL = 12 mA TYP† VI = VCC or GND, One input at VCC − 0.6 V, IO = 0, Outputs: low or high Other inputs at VCC or GND V 0.2 3V 0.8 3V 0.55 V 3.6 V ±5 µA 3.6 V 10 µA 500 µA 3.3 V to 3.6 V VI = VCC or GND VO = VCC or GND UNIT −1.2 V MIN to MAX IOL = 6 mA VI = VCC or GND MAX 3.3 V 4 pF 3.3 V 6 pF † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ For ICC of AVCC, and ICC vs Frequency (see Figures 7 and 8). timing requirements over recommended ranges of supply voltage and operating free-air temperature fclk Clock frequency Input clock duty cycle Stabilization time§ MIN MAX UNIT 25 125 MHz 40% 60% 1 ms § Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Note 6 and Figures 1 and 2)¶ PARAMETER tphase error, − jitter (see Notes 7 and 8, Figures 3, 4, and 5) tsk(o)# FROM (INPUT)/CONDITION TO (OUTPUT) CLKIN↑ = 66 MHz to100 MHz FBIN↑ Any Y or FBOUT Any Y or FBOUT Jitter(pk-pk) (see Figure 6) Jitter(cycle-cycle) (see Figure 6) Duty cycle VCC, AVCC = 3.3 V ± 0.165 V VCC, AVCC = 3.3 V ± 0.3 V MIN MAX MIN 150 −200 −150 Any Y or FBOUT TYP −80 TYP 200 ps 200 ps 80 CLKIN = 66 MHz to 100 MHz ps Any Y or FBOUT F(CLKIN > 60 MHz) UNIT MAX Any Y or FBOUT |100| 45% 55% tr Any Y or FBOUT 1.3 1.9 0.8 2.1 tf Any Y or FBOUT 1.7 2.5 1.2 2.7 ¶ These parameters are not production tested. # The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. This is considered as static phase error. 8. Phase error does not include jitter. The total phase error is − 230 ps to 230 ps for the 5% VCC range. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns 5 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 500 W Output 30 pF 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS PHASE ADJUSTMENT SLOPE AND PHASE ERROR vs LUMPED FEEDBACK CAPACITANCE AT FBIN 250 50 VCC = 3.3 V fc = 100 MHz CLY = 30 pF TA = 25°C Phase Error Measured from CLK to Y 30 20 200 150 Phase Error 100 50 10 0 0 −10 −50 −20 −100 −30 Phase Error − ps Phase Adjustment Slope − ps/pF 40 −150 Phase Adjustment Slope −200 −40 −250 −50 0 5 10 15 20 25 30 35 40 45 50 CLF − Lumped Feedback Capacitance at FBIN − pF Figure 3 PHASE ERROR vs CLOCK FREQUENCY 400 VCC = 3.3 V CLY = CLF = 30 pF TA = 25°C Phase Error Measured from CLK to FBIN Phase Error − ps 300 200 100 0 −100 35 45 55 65 75 85 95 105 115 125 fc − Clock Frequency − MHz Figure 4 NOTES: A. CLY = Lumped capacitive load at Y B. CLF = Lumped feedback capacitance at FBIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

      
 

   SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS PHASE ERROR vs SUPPLY VOLTAGE JITTER vs CLOCK FREQUENCY 400 400 350 300 fc = 100 MHz CLY = CLF = 30 pF TA = 25°C Phase Error Measured from CLK to FBIN VCC = 3.3 V TA = 25°C 350 300 Jitter − ps Phase Error − ps 250 200 150 100 250 200 150 Peak to Peak 50 100 0 50 −50 −100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Cycle to Cycle 0 35 3.7 45 Figure 5 95 105 115 125 250 VCC = 3.6 V TA = 25°C CLY = CLF = 30 pF AVCC = 3.6 V Bias = 0/3 V CLY = CLF = 30 pF TA = 25°C 200 I CC − Supply Current − mA AI CC − Analog Supply Current − mA 85 SUPPLY CURRENT vs CLOCK FREQUENCY 16 10 8 6 4 150 100 50 2 0 10 0 20 40 60 80 100 120 140 20 40 fc − Clock Frequency − MHz Figure 7 60 80 100 120 fclk − Clock Frequency − MHz Figure 8 NOTES: A. CLY = Lumped capacitive load at Y B. CLF = Lumped feedback capacitance at FBIN 8 75 Figure 6 ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 12 65 fc − Clock Frequency − MHz VCC − Supply Voltage − V 14 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 140 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDC2509BPWR NRND TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CK2509B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of